From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1778) id 0018C385C40F; Mon, 3 Oct 2022 22:05:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0018C385C40F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664834717; bh=ZP+nfQ5VsBjH7eB9qbTO5mYknlLJFu3WGDKkynIzjc0=; h=From:To:Subject:Date:From; b=S6wKSNsAZ/w5DrGYIBxO1Dqd2Q+grqfIu7w5FXq7lHDkCDdjwTKFp1TVI8ddFejrA KMzu6Ucc1I0Y6TzPIRozV+frJXovmTpW0WIYU63ijnjKZu2dvYF5UqssLzKvvdBMiO E2ZmviLmhvzx/3Gji/nj35VUnBBa90jca3W27lJE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Aurelien Jarno To: glibc-cvs@sourceware.org Subject: [glibc/release/2.33/master] x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation X-Act-Checkin: glibc X-Git-Author: Aurelien Jarno X-Git-Refname: refs/heads/release/2.33/master X-Git-Oldrev: 068c8d5aa994d868bb9307dc0d4c8e3f060b2cf3 X-Git-Newrev: 38e321f4ac70b6aecb35a8af7d1a2fbe366ab482 Message-Id: <20221003220517.0018C385C40F@sourceware.org> Date: Mon, 3 Oct 2022 22:05:16 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=38e321f4ac70b6aecb35a8af7d1a2fbe366ab482 commit 38e321f4ac70b6aecb35a8af7d1a2fbe366ab482 Author: Aurelien Jarno Date: Mon Oct 3 23:16:46 2022 +0200 x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation The AVX2 memrchr implementation uses the 'shlxl' instruction, which belongs to the BMI2 CPU feature and uses the 'lzcnt' instruction, which belongs to the LZCNT CPU feature. Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S") Partially resolves: BZ #29611 Reviewed-by: Noah Goldstein (cherry picked from commit 3c0c78afabfed4b6fc161c159e628fbf14ff370b) Diff: --- sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 + sysdeps/x86_64/multiarch/ifunc-impl-list.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h index 6de72f7272..52bd00ea5c 100644 --- a/sysdeps/x86_64/multiarch/ifunc-avx2.h +++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h @@ -31,6 +31,7 @@ IFUNC_SELECTOR (void) if (CPU_FEATURE_USABLE_P (cpu_features, AVX2) && CPU_FEATURE_USABLE_P (cpu_features, BMI2) + && CPU_FEATURE_USABLE_P (cpu_features, LZCNT) && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load)) { if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index 81640cf006..d1fc1e75d6 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -174,15 +174,21 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/memrchr.c. */ IFUNC_IMPL (i, name, memrchr, IFUNC_IMPL_ADD (array, i, memrchr, - CPU_FEATURE_USABLE (AVX2), + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (BMI2) + && CPU_FEATURE_USABLE (LZCNT)), __memrchr_avx2) IFUNC_IMPL_ADD (array, i, memrchr, (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (BMI2) + && CPU_FEATURE_USABLE (LZCNT) && CPU_FEATURE_USABLE (RTM)), __memrchr_avx2_rtm) IFUNC_IMPL_ADD (array, i, memrchr, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2) + && CPU_FEATURE_USABLE (LZCNT)), __memrchr_evex) IFUNC_IMPL_ADD (array, i, memrchr, 1, __memrchr_sse2))