From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1791) id C910F3858C2F; Tue, 4 Oct 2022 13:00:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C910F3858C2F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664888406; bh=XkgIM0tr/WOu9dVITcPjS0BIXUMJ/nhovkfEH8X0+3o=; h=From:To:Subject:Date:From; b=Lxn/rMfqgskAUDLOMiWzF0xbZIQjBBJMWNyYWB5Osb5ebvZ//2vU+k8V65mvIAH5f vnXnMKVGM9tkVHd+0eFjoriRxSwZWDqCSOepI4LQ1dzAXTyxAyA9LMAG+j9DhFDF9R GIYoduyICUNGQJBaAEoeV1a+5etv3+AuhDvg3/wU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Adhemerval Zanella To: glibc-cvs@sourceware.org Subject: [glibc/azanella/clang] x86: Remove cast on assembly inline input/outputs X-Act-Checkin: glibc X-Git-Author: Adhemerval Zanella X-Git-Refname: refs/heads/azanella/clang X-Git-Oldrev: ae1617a30df34f669f3cf239f75533bc3ffaf1de X-Git-Newrev: 412039e9a42f78ca01b217badb9861338b7a226a Message-Id: <20221004130006.C910F3858C2F@sourceware.org> Date: Tue, 4 Oct 2022 13:00:06 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=412039e9a42f78ca01b217badb9861338b7a226a commit 412039e9a42f78ca01b217badb9861338b7a226a Author: Adhemerval Zanella Date: Tue Jul 26 08:45:41 2022 -0300 x86: Remove cast on assembly inline input/outputs Diff: --- sysdeps/x86/fpu/sfp-machine.h | 94 +++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/sysdeps/x86/fpu/sfp-machine.h b/sysdeps/x86/fpu/sfp-machine.h index 89a73642b1..9324450828 100644 --- a/sysdeps/x86/fpu/sfp-machine.h +++ b/sysdeps/x86/fpu/sfp-machine.h @@ -69,71 +69,71 @@ typedef unsigned int UTItype __attribute__ ((mode (TI))); "adc{l} {%9,%2|%2,%9}\n\t" \ "adc{l} {%7,%1|%1,%7}\n\t" \ "adc{l} {%5,%0|%0,%5}" \ - : "=r" ((USItype) (r3)), \ - "=&r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "%0" ((USItype) (x3)), \ - "g" ((USItype) (y3)), \ - "%1" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "%2" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "%3" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r3), \ + "=&r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "%0" (x3), \ + "g" (y3), \ + "%1" (x2), \ + "g" (y2), \ + "%2" (x1), \ + "g" (y1), \ + "%3" (x0), \ + "g" (y0)) # define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \ __asm__ ("add{l} {%8,%2|%2,%8}\n\t" \ "adc{l} {%6,%1|%1,%6}\n\t" \ "adc{l} {%4,%0|%0,%4}" \ - : "=r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "%0" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "%1" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "%2" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "%0" (x2), \ + "g" (y2), \ + "%1" (x1), \ + "g" (y1), \ + "%2" (x0), \ + "g" (y0)) # define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \ __asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \ "sbb{l} {%9,%2|%2,%9}\n\t" \ "sbb{l} {%7,%1|%1,%7}\n\t" \ "sbb{l} {%5,%0|%0,%5}" \ - : "=r" ((USItype) (r3)), \ - "=&r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "0" ((USItype) (x3)), \ - "g" ((USItype) (y3)), \ - "1" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "2" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "3" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r3), \ + "=&r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "0" (x3), \ + "g" (y3), \ + "1" (x2), \ + "g" (y2), \ + "2" (x1), \ + "g" (y1), \ + "3" (x0), \ + "g" (y0)) # define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \ __asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \ "sbb{l} {%6,%1|%1,%6}\n\t" \ "sbb{l} {%4,%0|%0,%4}" \ - : "=r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "0" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "1" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "2" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "0" (x2), \ + "g" (y2), \ + "1" (x1), \ + "g" (y1), \ + "2" (x0), \ + "g" (y0)) # define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \ __asm__ ("add{l} {%4,%3|%3,%4}\n\t" \ "adc{l} {$0,%2|%2,0}\n\t" \ "adc{l} {$0,%1|%1,0}\n\t" \ "adc{l} {$0,%0|%0,0}" \ - : "+r" ((USItype) (x3)), \ - "+&r" ((USItype) (x2)), \ - "+&r" ((USItype) (x1)), \ - "+&r" ((USItype) (x0)) \ - : "g" ((USItype) (i))) + : "+r" (x3), \ + "+&r" (x2), \ + "+&r" (x1), \ + "+&r" (x0) \ + : "g" (i)) # define _FP_MUL_MEAT_S(R,X,Y) \