From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1944) id 1D1363854167; Wed, 26 Oct 2022 14:49:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1D1363854167 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666795774; bh=PioS81gUQS3QjUyUldTrASaNzGv0Yi0PkwwP/AjjK2w=; h=From:To:Subject:Date:From; b=Owy+yQxNz6sZYeeLAYo30sPI7am0mxCDw22vKlinzVUavS/RrqGa70514SWbyPRyQ N9fi/TzQLgyM6kkTEzixPTuQ4pWN5jqc99qpoOXixeY8q149pCdSSA9vCfR39IrGD7 DDlwEFPSUL05NSbCuFnqbit0gpN+4XYytdtvD77Y= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Szabolcs Nagy To: glibc-cvs@sourceware.org Subject: [glibc/arm/morello/main] TODO(uapi): cheri: start: restrict auxv capability permissions X-Act-Checkin: glibc X-Git-Author: Szabolcs Nagy X-Git-Refname: refs/heads/arm/morello/main X-Git-Oldrev: df30ef1b0d68ffde8dfb0a18ac08b97fe375d813 X-Git-Newrev: e8d0e61aa2392f852c02725eb9af9b2f4139d076 Message-Id: <20221026144934.1D1363854167@sourceware.org> Date: Wed, 26 Oct 2022 14:49:34 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=e8d0e61aa2392f852c02725eb9af9b2f4139d076 commit e8d0e61aa2392f852c02725eb9af9b2f4139d076 Author: Szabolcs Nagy Date: Fri Oct 21 09:52:47 2022 +0100 TODO(uapi): cheri: start: restrict auxv capability permissions TODO: not needed with full pcuabi Diff: --- elf/dl-support.c | 2 ++ elf/rtld.c | 2 ++ sysdeps/aarch64/morello/dl-machine.h | 2 ++ sysdeps/aarch64/morello/start.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/elf/dl-support.c b/elf/dl-support.c index ffc1d8d01b..f2f0bdbaf4 100644 --- a/elf/dl-support.c +++ b/elf/dl-support.c @@ -258,7 +258,9 @@ _dl_aux_init (ElfW(auxv_t) *av) # ifdef __CHERI_PURE_CAPABILITY__ _dl_main_map.l_map_start = auxv_values[AT_CHERI_EXEC_RX_CAP]; + _dl_main_map.l_map_start = __builtin_cheri_perms_and (_dl_main_map.l_map_start, CAP_PERM_MASK_RX); _dl_main_map.l_rw_start = auxv_values[AT_CHERI_EXEC_RW_CAP]; + _dl_main_map.l_rw_start = __builtin_cheri_perms_and (_dl_main_map.l_rw_start, CAP_PERM_MASK_RW); # endif } #endif diff --git a/elf/rtld.c b/elf/rtld.c index 753211772c..daff17a9e1 100644 --- a/elf/rtld.c +++ b/elf/rtld.c @@ -1724,9 +1724,11 @@ dl_main (const ElfW(Phdr) *phdr, { case AT_CHERI_EXEC_RX_CAP: main_map->l_map_start = av->a_un.a_val; + main_map->l_map_start = __builtin_cheri_perms_and (main_map->l_map_start, CAP_PERM_MASK_RX); break; case AT_CHERI_EXEC_RW_CAP: main_map->l_rw_start = av->a_un.a_val; + main_map->l_rw_start = __builtin_cheri_perms_and (main_map->l_rw_start, CAP_PERM_MASK_RW); break; } #endif diff --git a/sysdeps/aarch64/morello/dl-machine.h b/sysdeps/aarch64/morello/dl-machine.h index 0f681b1925..7da7c5bfc0 100644 --- a/sysdeps/aarch64/morello/dl-machine.h +++ b/sysdeps/aarch64/morello/dl-machine.h @@ -152,6 +152,8 @@ elf_machine_rtld_base_setup (struct link_map *map, void *args) cap_rw = cap_exe_rw; ldso_base = cap_rx; /* Assume load segments start at vaddr 0. */ } + cap_rx = __builtin_cheri_perms_and (cap_rx, CAP_PERM_MASK_RX); + cap_rw = __builtin_cheri_perms_and (cap_rw, CAP_PERM_MASK_RW); map->l_addr = ldso_base; map->l_map_start = cap_rx; map->l_rw_start = cap_rw; diff --git a/sysdeps/aarch64/morello/start.c b/sysdeps/aarch64/morello/start.c index de7aeab4c9..5d413ae78e 100644 --- a/sysdeps/aarch64/morello/start.c +++ b/sysdeps/aarch64/morello/start.c @@ -124,9 +124,11 @@ get_caps (uintptr_t *cap_rx, uintptr_t *cap_rw, const uintptr_t *auxv) return; case AT_CHERI_EXEC_RX_CAP: *cap_rx = auxv[1]; + *cap_rx = __builtin_cheri_perms_and (*cap_rx, CAP_PERM_MASK_RX); break; case AT_CHERI_EXEC_RW_CAP: *cap_rw = auxv[1]; + *cap_rw = __builtin_cheri_perms_and (*cap_rw, CAP_PERM_MASK_RW); break; } auxv += 2;