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From: Adhemerval Zanella <azanella@sourceware.org>
To: glibc-cvs@sourceware.org
Subject: [glibc] riscv: Get level 3 cache's information
Date: Wed,  9 Nov 2022 14:41:54 +0000 (GMT)	[thread overview]
Message-ID: <20221109144155.5C9AE38356B9@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=38caf7a1cc92e6a546ea655701c8237ee727d0d3

commit 38caf7a1cc92e6a546ea655701c8237ee727d0d3
Author: Zong Li <zong.li@sifive.com>
Date:   Wed Nov 9 11:40:59 2022 -0300

    riscv: Get level 3 cache's information
    
    RISC-V architecture extends the cache information for level 3 cache
    in AUX vector in Linux v.6.1-rc1. This patch supports sysconf to get
    the level 3 cache information.
    
    Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
    Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

Diff:
---
 sysdeps/unix/sysv/linux/riscv/sysconf.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sysdeps/unix/sysv/linux/riscv/sysconf.c b/sysdeps/unix/sysv/linux/riscv/sysconf.c
index b768ebf781..85b9faff71 100644
--- a/sysdeps/unix/sysv/linux/riscv/sysconf.c
+++ b/sysdeps/unix/sysv/linux/riscv/sysconf.c
@@ -90,6 +90,12 @@ __sysconf (int name)
 	return sysconf_get_cache_associativity (AT_L2_CACHEGEOMETRY);
       case _SC_LEVEL2_CACHE_LINESIZE:
 	return sysconf_get_cache_linesize (AT_L2_CACHEGEOMETRY);
+      case _SC_LEVEL3_CACHE_SIZE:
+       return sysconf_get_cache_size (AT_L3_CACHESIZE);
+      case _SC_LEVEL3_CACHE_ASSOC:
+       return sysconf_get_cache_associativity (AT_L3_CACHEGEOMETRY);
+      case _SC_LEVEL3_CACHE_LINESIZE:
+       return sysconf_get_cache_linesize (AT_L3_CACHEGEOMETRY);
       default:
 	return linux_sysconf (name);
     }

                 reply	other threads:[~2022-11-09 14:41 UTC|newest]

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