From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1791) id B074F3858032; Thu, 9 Feb 2023 19:49:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B074F3858032 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1675972149; bh=UxSLOhrymfBVZiyBdHvJwWSmScgEYO3hq0VcCNpPkxQ=; h=From:To:Subject:Date:From; b=F/bpZV7c/wACO1+Mb/kcK4EEGkq48+V3FHH/12na+exq1Havr6EL0nvbWsIurqPKT jEMt46vKIYsXtLrcAX2zYZwMTF+izhZc261XD9fa8w2/XtbeDaWaAXTdALZZARUEo7 q38Z5FFm4pgbizKyWagb3hLQ1rFWOPrbeL00zN34= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Adhemerval Zanella To: glibc-cvs@sourceware.org Subject: [glibc/azanella/clang] x86: Remove cast on assembly inline input/outputs X-Act-Checkin: glibc X-Git-Author: Adhemerval Zanella X-Git-Refname: refs/heads/azanella/clang X-Git-Oldrev: 6482496df97cdf50def5128b7402a075b9fb20e3 X-Git-Newrev: 9d88899dcd37b0745a65d0e53dd89b148f213e38 Message-Id: <20230209194909.B074F3858032@sourceware.org> Date: Thu, 9 Feb 2023 19:49:09 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=9d88899dcd37b0745a65d0e53dd89b148f213e38 commit 9d88899dcd37b0745a65d0e53dd89b148f213e38 Author: Adhemerval Zanella Date: Tue Jul 26 08:45:41 2022 -0300 x86: Remove cast on assembly inline input/outputs Diff: --- sysdeps/x86/fpu/sfp-machine.h | 94 +++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/sysdeps/x86/fpu/sfp-machine.h b/sysdeps/x86/fpu/sfp-machine.h index 89a73642b1..9324450828 100644 --- a/sysdeps/x86/fpu/sfp-machine.h +++ b/sysdeps/x86/fpu/sfp-machine.h @@ -69,71 +69,71 @@ typedef unsigned int UTItype __attribute__ ((mode (TI))); "adc{l} {%9,%2|%2,%9}\n\t" \ "adc{l} {%7,%1|%1,%7}\n\t" \ "adc{l} {%5,%0|%0,%5}" \ - : "=r" ((USItype) (r3)), \ - "=&r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "%0" ((USItype) (x3)), \ - "g" ((USItype) (y3)), \ - "%1" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "%2" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "%3" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r3), \ + "=&r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "%0" (x3), \ + "g" (y3), \ + "%1" (x2), \ + "g" (y2), \ + "%2" (x1), \ + "g" (y1), \ + "%3" (x0), \ + "g" (y0)) # define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \ __asm__ ("add{l} {%8,%2|%2,%8}\n\t" \ "adc{l} {%6,%1|%1,%6}\n\t" \ "adc{l} {%4,%0|%0,%4}" \ - : "=r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "%0" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "%1" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "%2" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "%0" (x2), \ + "g" (y2), \ + "%1" (x1), \ + "g" (y1), \ + "%2" (x0), \ + "g" (y0)) # define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \ __asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \ "sbb{l} {%9,%2|%2,%9}\n\t" \ "sbb{l} {%7,%1|%1,%7}\n\t" \ "sbb{l} {%5,%0|%0,%5}" \ - : "=r" ((USItype) (r3)), \ - "=&r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "0" ((USItype) (x3)), \ - "g" ((USItype) (y3)), \ - "1" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "2" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "3" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r3), \ + "=&r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "0" (x3), \ + "g" (y3), \ + "1" (x2), \ + "g" (y2), \ + "2" (x1), \ + "g" (y1), \ + "3" (x0), \ + "g" (y0)) # define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \ __asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \ "sbb{l} {%6,%1|%1,%6}\n\t" \ "sbb{l} {%4,%0|%0,%4}" \ - : "=r" ((USItype) (r2)), \ - "=&r" ((USItype) (r1)), \ - "=&r" ((USItype) (r0)) \ - : "0" ((USItype) (x2)), \ - "g" ((USItype) (y2)), \ - "1" ((USItype) (x1)), \ - "g" ((USItype) (y1)), \ - "2" ((USItype) (x0)), \ - "g" ((USItype) (y0))) + : "=r" (r2), \ + "=&r" (r1), \ + "=&r" (r0) \ + : "0" (x2), \ + "g" (y2), \ + "1" (x1), \ + "g" (y1), \ + "2" (x0), \ + "g" (y0)) # define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \ __asm__ ("add{l} {%4,%3|%3,%4}\n\t" \ "adc{l} {$0,%2|%2,0}\n\t" \ "adc{l} {$0,%1|%1,0}\n\t" \ "adc{l} {$0,%0|%0,0}" \ - : "+r" ((USItype) (x3)), \ - "+&r" ((USItype) (x2)), \ - "+&r" ((USItype) (x1)), \ - "+&r" ((USItype) (x0)) \ - : "g" ((USItype) (i))) + : "+r" (x3), \ + "+&r" (x2), \ + "+&r" (x1), \ + "+&r" (x0) \ + : "g" (i)) # define _FP_MUL_MEAT_S(R,X,Y) \