From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1624) id 4DAA0385842C; Mon, 19 Jun 2023 22:00:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4DAA0385842C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1687212016; bh=HVaAujacliM/ircgHqAStDarssA8xjSi4Y8CztqGmNc=; h=From:To:Subject:Date:From; b=JvPXr1sckOqkMr2S2VQUORQQwbDvusrS6Zb1pbVtAf0/Mbph6N8s86fL23PYA3I7A t548UgErH/1ywG62bUUoKvcpsrcb8SrXqEIiC4Zjtn8QW4D7hTB9QZLIk/8pdUYzi6 LSFKx1z2N86nWgQ96HEG13uVAqyXhcYoLOgNmWik= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Paul Pluzhnikov To: glibc-cvs@sourceware.org Subject: [glibc] Fix misspellings -- BZ 25337 X-Act-Checkin: glibc X-Git-Author: Paul Pluzhnikov X-Git-Refname: refs/heads/master X-Git-Oldrev: 2d88df541132f09454d947c498103aa7be76b652 X-Git-Newrev: 4290aed05135ae4c0272006442d147f2155e70d7 Message-Id: <20230619220016.4DAA0385842C@sourceware.org> Date: Mon, 19 Jun 2023 22:00:16 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=4290aed05135ae4c0272006442d147f2155e70d7 commit 4290aed05135ae4c0272006442d147f2155e70d7 Author: Paul Pluzhnikov Date: Mon Jun 19 21:58:33 2023 +0000 Fix misspellings -- BZ 25337 Diff: --- sysdeps/x86/cpu-features.c | 2 +- sysdeps/x86/dl-cacheinfo.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 525828f59c..9ac195810f 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -579,7 +579,7 @@ intel_get_fam6_microarch (unsigned int model, else -> Skylake-avx512 - These are all microarchitecturally indentical, so use + These are all microarchitecturally identical, so use Skylake-avx512 for all of them. */ return INTEL_BIGCORE_SKYLAKE_AVX512; diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index fb1a6cf4a9..c98fa57a7b 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -745,7 +745,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) /* The default setting for the non_temporal threshold is [1/8, 1/2] of size of the chip's cache (depending on `cachesize_non_temporal_divisor` which - is microarch specific. The defeault is 1/4). For most Intel and AMD + is microarch specific. The default is 1/4). For most Intel and AMD processors with an initial release date between 2017 and 2023, a thread's typical share of the cache is from 18-64MB. Using a reasonable size fraction of L3 is meant to estimate the point where non-temporal stores