From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7910) id 917643858C33; Wed, 19 Jul 2023 15:01:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 917643858C33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1689778866; bh=IobSNpQetoVoxnb22RAPXvUQYghDIqO7JeaC+IoPgbM=; h=From:To:Subject:Date:From; b=qnqZpeia+p4uDOtCf5Xz2wWE2Y0FKolvqd3PJM0tkjzU10Am8pZ/ppBEZ7NccLGwO CkZzXzzG2gtPaLL6xFGygbqS7GEOM833ZfCD+rCe3ZQZ8L+I5SkrVFjsmxbTWtseOv AsgGVm0MAjcYGBmb8ijPRI1jNvzgMQPCZ2KI9Eb8= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Andreas K. Huttel To: glibc-cvs@sourceware.org Subject: [glibc] Update x86_64 libm-test-ulps (x32 ABI) X-Act-Checkin: glibc X-Git-Author: =?utf-8?q?Andreas_K=2E_H=C3=BCttel?= X-Git-Refname: refs/heads/master X-Git-Oldrev: 5d72e7e41a7860b911251bfc8dd3641460cc20a0 X-Git-Newrev: 6d457ff36a45872d66762fb31106145ff753060d Message-Id: <20230719150106.917643858C33@sourceware.org> Date: Wed, 19 Jul 2023 15:01:06 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=6d457ff36a45872d66762fb31106145ff753060d commit 6d457ff36a45872d66762fb31106145ff753060d Author: Andreas K. Hüttel Date: Wed Jul 19 16:56:54 2023 +0200 Update x86_64 libm-test-ulps (x32 ABI) Based on feedback by Mike Gilbert Linux-6.1.38-dist x86_64 AMD Phenom-tm- II X6 1055T Processor -march=amdfam10 failures occur for x32 ABI Signed-off-by: Andreas K. Hüttel Diff: --- sysdeps/x86_64/fpu/libm-test-ulps | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/sysdeps/x86_64/fpu/libm-test-ulps b/sysdeps/x86_64/fpu/libm-test-ulps index 9e47fdfa87..e0015347d0 100644 --- a/sysdeps/x86_64/fpu/libm-test-ulps +++ b/sysdeps/x86_64/fpu/libm-test-ulps @@ -77,7 +77,7 @@ double: 2 Function: "acosh_vlen4": double: 2 -float: 1 +float: 2 Function: "acosh_vlen4_avx2": double: 2 @@ -158,11 +158,11 @@ float128: 4 ldouble: 5 Function: "asinh_vlen2": -double: 1 +double: 2 Function: "asinh_vlen4": double: 1 -float: 1 +float: 2 Function: "asinh_vlen4_avx2": double: 1 @@ -289,11 +289,11 @@ Function: "atanh_vlen16": float: 1 Function: "atanh_vlen2": -double: 1 +double: 2 Function: "atanh_vlen4": double: 1 -float: 1 +float: 2 Function: "atanh_vlen4_avx2": double: 1 @@ -664,7 +664,7 @@ Function: "cbrt_vlen16": float: 1 Function: "cbrt_vlen2": -double: 1 +double: 4 Function: "cbrt_vlen4": double: 1 @@ -1363,11 +1363,11 @@ Function: "erfc_vlen16": float: 1 Function: "erfc_vlen2": -double: 1 +double: 5 Function: "erfc_vlen4": double: 1 -float: 1 +float: 3 Function: "erfc_vlen4_avx2": double: 1 @@ -1413,7 +1413,7 @@ Function: "exp10_vlen16": float: 3 Function: "exp10_vlen2": -double: 1 +double: 2 Function: "exp10_vlen4": double: 1 @@ -1743,11 +1743,11 @@ Function: "log10_vlen16": float: 1 Function: "log10_vlen2": -double: 1 +double: 2 Function: "log10_vlen4": double: 1 -float: 1 +float: 2 Function: "log10_vlen4_avx2": double: 1 @@ -2046,7 +2046,7 @@ double: 2 Function: "sinh_vlen4": double: 2 -float: 1 +float: 2 Function: "sinh_vlen4_avx2": double: 2 @@ -2129,10 +2129,11 @@ Function: "tanh_vlen16": float: 1 Function: "tanh_vlen2": -double: 1 +double: 2 Function: "tanh_vlen4": double: 1 +float: 2 Function: "tanh_vlen4_avx2": double: 1