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From: Noah Goldstein <nwg@sourceware.org> To: glibc-cvs@sourceware.org Subject: [glibc/release/2.37/master] x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold. Date: Mon, 28 Aug 2023 20:02:53 +0000 (GMT) [thread overview] Message-ID: <20230828200253.E451238582A3@sourceware.org> (raw) https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=cc8243fb0b711ab05ac6dcf235f0555025921b5e commit cc8243fb0b711ab05ac6dcf235f0555025921b5e Author: Noah Goldstein <goldstein.w.n@gmail.com> Date: Tue Jul 18 10:27:59 2023 -0500 x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold. On some machines we end up with incomplete cache information. This can make the new calculation of `sizeof(total-L3)/custom-divisor` end up lower than intended (and lower than the prior value). So reintroduce the old bound as a lower bound to avoid potentially regressing code where we don't have complete information to make the decision. Reviewed-by: DJ Delorie <dj@redhat.com> (cherry picked from commit 8b9a0af8ca012217bf90d1dc0694f85b49ae09da) Diff: --- sysdeps/x86/dl-cacheinfo.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index f5b04f489e..d99c0b0e75 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -757,12 +757,21 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) provides proper LRU hints so that the maximum thrashing capped at 1/associativity. */ unsigned long int non_temporal_threshold = shared / 4; + + /* If the computed non_temporal_threshold <= 3/4 * per-thread L3, we most + likely have incorrect/incomplete cache info in which case, default to + 3/4 * per-thread L3 to avoid regressions. */ + unsigned long int non_temporal_threshold_lowbound + = shared_per_thread * 3 / 4; + if (non_temporal_threshold < non_temporal_threshold_lowbound) + non_temporal_threshold = non_temporal_threshold_lowbound; + /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run a higher risk of actually thrashing the cache as they don't have a HW LRU hint. As well, their performance in highly parallel situations is noticeably worse. */ if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)) - non_temporal_threshold = shared_per_thread * 3 / 4; + non_temporal_threshold = non_temporal_threshold_lowbound; /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best if that operation cannot overflow. Minimum of 0x4040 (16448) because the
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