From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7844) id 44B183858024; Tue, 5 Sep 2023 22:17:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 44B183858024 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693952279; bh=9X7oxXT7+sucIxCrimfvw3gtTXap5FrR2qVavFRw8Bs=; h=From:To:Subject:Date:From; b=bwN5DMhrHaUsbBnI7j7f03xCR+jhxQepwRJNCtIP7SbshIsesD3E/48J1oZAdFq2c 9m50wAmeOIcQ3pPF2uNiv+lJL1q5KJNzZ+3gIM17D0uot6P1wb7yXZouWJSmj2c1Qk 0jnL+shHGHPnnLnigHTetdqEPunfojoHlUo7ZEOQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Noah Goldstein To: glibc-cvs@sourceware.org Subject: [glibc/release/2.35/master] x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold. X-Act-Checkin: glibc X-Git-Author: Noah Goldstein X-Git-Refname: refs/heads/release/2.35/master X-Git-Oldrev: 47c7d2eb033eee558c837ba9cedc76ca701e9b6c X-Git-Newrev: 1c3ecf5858b1765379cb6232203b9fe29a2516e7 Message-Id: <20230905221759.44B183858024@sourceware.org> Date: Tue, 5 Sep 2023 22:17:59 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1c3ecf5858b1765379cb6232203b9fe29a2516e7 commit 1c3ecf5858b1765379cb6232203b9fe29a2516e7 Author: Noah Goldstein Date: Tue Jul 18 10:27:59 2023 -0500 x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold. On some machines we end up with incomplete cache information. This can make the new calculation of `sizeof(total-L3)/custom-divisor` end up lower than intended (and lower than the prior value). So reintroduce the old bound as a lower bound to avoid potentially regressing code where we don't have complete information to make the decision. Reviewed-by: DJ Delorie (cherry picked from commit 8b9a0af8ca012217bf90d1dc0694f85b49ae09da) Diff: --- sysdeps/x86/dl-cacheinfo.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index 79fb8cc5e3..627cf57efe 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -872,12 +872,21 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) provides proper LRU hints so that the maximum thrashing capped at 1/associativity. */ unsigned long int non_temporal_threshold = shared / 4; + + /* If the computed non_temporal_threshold <= 3/4 * per-thread L3, we most + likely have incorrect/incomplete cache info in which case, default to + 3/4 * per-thread L3 to avoid regressions. */ + unsigned long int non_temporal_threshold_lowbound + = shared_per_thread * 3 / 4; + if (non_temporal_threshold < non_temporal_threshold_lowbound) + non_temporal_threshold = non_temporal_threshold_lowbound; + /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run a higher risk of actually thrashing the cache as they don't have a HW LRU hint. As well, their performance in highly parallel situations is noticeably worse. */ if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)) - non_temporal_threshold = shared_per_thread * 3 / 4; + non_temporal_threshold = non_temporal_threshold_lowbound; /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best if that operation cannot overflow. Minimum of 0x4040 (16448) because the