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From: Adhemerval Zanella <azanella@sourceware.org>
To: glibc-cvs@sourceware.org
Subject: [glibc/azanella/bz30944-memcpy-zen] x86: Expand the comment on when REP STOSB is used on memset
Date: Fri, 27 Oct 2023 12:30:08 +0000 (GMT)	[thread overview]
Message-ID: <20231027123008.230ED3853519@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=b0fe1533ff7283e765a2e590d210999ca045ca4c

commit b0fe1533ff7283e765a2e590d210999ca045ca4c
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Fri Oct 27 08:14:14 2023 -0300

    x86: Expand the comment on when REP STOSB is used on memset

Diff:
---
 sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
index 3d9ad49cb9..0821b32997 100644
--- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
+++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
@@ -21,7 +21,9 @@
    2. If size is less than VEC, use integer register stores.
    3. If size is from VEC_SIZE to 2 * VEC_SIZE, use 2 VEC stores.
    4. If size is from 2 * VEC_SIZE to 4 * VEC_SIZE, use 4 VEC stores.
-   5. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with
+   5. On machines ERMS feature, if size is greater or equal than
+      __x86_rep_stosb_threshold then REP STOSB will be used.
+   6. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with
       4 VEC stores and store 4 * VEC at a time until done.  */
 
 #include <sysdep.h>

                 reply	other threads:[~2023-10-27 12:30 UTC|newest]

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