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From: Adhemerval Zanella <azanella@sourceware.org>
To: glibc-cvs@sourceware.org
Subject: [glibc] linux: Sync Linux 6.6 elf.h
Date: Fri,  3 Nov 2023 13:02:47 +0000 (GMT)	[thread overview]
Message-ID: <20231103130247.2545F3857028@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=d3476c20b29782453aa5d432a62eed4dde7d6269

commit d3476c20b29782453aa5d432a62eed4dde7d6269
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Oct 31 13:32:38 2023 -0300

    linux: Sync Linux 6.6 elf.h
    
    It adds NT_X86_SHSTK (2fab02b25ae7cf5), NT_RISCV_CSR/NT_RISCV_VECTOR
    (9300f00439743c4), and NT_LOONGARCH_HW_BREAK/NT_LOONGARCH_HW_WATCH
    (1a69f7a161a78ae).

Diff:
---
 elf/elf.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/elf/elf.h b/elf/elf.h
index 73a64baa79..5c1c1972d1 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -796,6 +796,7 @@ typedef struct
 #define NT_386_TLS	0x200		/* i386 TLS slots (struct user_desc) */
 #define NT_386_IOPERM	0x201		/* x86 io permission bitmap (1=deny) */
 #define NT_X86_XSTATE	0x202		/* x86 extended state using xsave */
+#define NT_X86_SHSTK	0x204		/* x86 SHSTK state */
 #define NT_S390_HIGH_GPRS	0x300	/* s390 upper register halves */
 #define NT_S390_TIMER	0x301		/* s390 timer register */
 #define NT_S390_TODCMP	0x302		/* s390 TOD clock comparator register */
@@ -834,6 +835,8 @@ typedef struct
 #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers.  */
 #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode.  */
 #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers.  */
+#define NT_RISCV_CSR	0x900		/* RISC-V Control and Status Registers */
+#define NT_RISCV_VECTOR	0x901		/* RISC-V vector registers */
 #define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers.  */
 #define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and
 					   status registers.  */
@@ -843,6 +846,8 @@ typedef struct
 					   SIMD Extension registers.  */
 #define NT_LOONGARCH_LBT	0xa04	/* LoongArch Loongson Binary
 					   Translation registers.  */
+#define NT_LOONGARCH_HW_BREAK	0xa05   /* LoongArch hardware breakpoint registers */
+#define NT_LOONGARCH_HW_WATCH	0xa06   /* LoongArch hardware watchpoint registers */
 
 /* Legal values for the note segment descriptor types for object files.  */

                 reply	other threads:[~2023-11-03 13:02 UTC|newest]

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