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From: Yinyu Cai <caiyinyu@sourceware.org>
To: glibc-cvs@sourceware.org
Subject: [glibc/release/2.38/master] LoongArch: Delete excessively allocated memory.
Date: Wed, 13 Dec 2023 02:03:27 +0000 (GMT)	[thread overview]
Message-ID: <20231213020327.B73883858C2F@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=44f757a6364a546359809d48c76b3debd26e77d4

commit 44f757a6364a546359809d48c76b3debd26e77d4
Author: caiyinyu <caiyinyu@loongson.cn>
Date:   Thu Oct 26 17:27:21 2023 +0800

    LoongArch: Delete excessively allocated memory.
    
    Backported from glibc 2.39 development.

Diff:
---
 sysdeps/loongarch/dl-trampoline.h | 68 +++++++++++++++++++--------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/sysdeps/loongarch/dl-trampoline.h b/sysdeps/loongarch/dl-trampoline.h
index 02375286f8..99fcacab76 100644
--- a/sysdeps/loongarch/dl-trampoline.h
+++ b/sysdeps/loongarch/dl-trampoline.h
@@ -19,9 +19,9 @@
 /* Assembler veneer called from the PLT header code for lazy loading.
    The PLT header passes its own args in t0-t2.  */
 #ifdef USE_LASX
-# define FRAME_SIZE (-((-9 * SZREG - 8 * SZFREG - 8 * SZXREG) & ALMASK))
+# define FRAME_SIZE (-((-9 * SZREG - 8 * SZXREG) & ALMASK))
 #elif defined USE_LSX
-# define FRAME_SIZE (-((-9 * SZREG - 8 * SZFREG - 8 * SZVREG) & ALMASK))
+# define FRAME_SIZE (-((-9 * SZREG - 8 * SZVREG) & ALMASK))
 #elif !defined __loongarch_soft_float
 # define FRAME_SIZE (-((-9 * SZREG - 8 * SZFREG) & ALMASK))
 #else
@@ -44,23 +44,23 @@ ENTRY (_dl_runtime_resolve)
 	REG_S	a7, sp, 8*SZREG
 
 #ifdef USE_LASX
-	xvst	xr0, sp, 9*SZREG + 8*SZFREG + 0*SZXREG
-	xvst	xr1, sp, 9*SZREG + 8*SZFREG + 1*SZXREG
-	xvst	xr2, sp, 9*SZREG + 8*SZFREG + 2*SZXREG
-	xvst	xr3, sp, 9*SZREG + 8*SZFREG + 3*SZXREG
-	xvst	xr4, sp, 9*SZREG + 8*SZFREG + 4*SZXREG
-	xvst	xr5, sp, 9*SZREG + 8*SZFREG + 5*SZXREG
-	xvst	xr6, sp, 9*SZREG + 8*SZFREG + 6*SZXREG
-	xvst	xr7, sp, 9*SZREG + 8*SZFREG + 7*SZXREG
+	xvst	xr0, sp, 9*SZREG + 0*SZXREG
+	xvst	xr1, sp, 9*SZREG + 1*SZXREG
+	xvst	xr2, sp, 9*SZREG + 2*SZXREG
+	xvst	xr3, sp, 9*SZREG + 3*SZXREG
+	xvst	xr4, sp, 9*SZREG + 4*SZXREG
+	xvst	xr5, sp, 9*SZREG + 5*SZXREG
+	xvst	xr6, sp, 9*SZREG + 6*SZXREG
+	xvst	xr7, sp, 9*SZREG + 7*SZXREG
 #elif defined USE_LSX
-	vst	vr0, sp, 9*SZREG + 8*SZFREG + 0*SZVREG
-	vst	vr1, sp, 9*SZREG + 8*SZFREG + 1*SZVREG
-	vst	vr2, sp, 9*SZREG + 8*SZFREG + 2*SZVREG
-	vst	vr3, sp, 9*SZREG + 8*SZFREG + 3*SZVREG
-	vst	vr4, sp, 9*SZREG + 8*SZFREG + 4*SZVREG
-	vst	vr5, sp, 9*SZREG + 8*SZFREG + 5*SZVREG
-	vst	vr6, sp, 9*SZREG + 8*SZFREG + 6*SZVREG
-	vst	vr7, sp, 9*SZREG + 8*SZFREG + 7*SZVREG
+	vst	vr0, sp, 9*SZREG + 0*SZVREG
+	vst	vr1, sp, 9*SZREG + 1*SZVREG
+	vst	vr2, sp, 9*SZREG + 2*SZVREG
+	vst	vr3, sp, 9*SZREG + 3*SZVREG
+	vst	vr4, sp, 9*SZREG + 4*SZVREG
+	vst	vr5, sp, 9*SZREG + 5*SZVREG
+	vst	vr6, sp, 9*SZREG + 6*SZVREG
+	vst	vr7, sp, 9*SZREG + 7*SZVREG
 #elif !defined __loongarch_soft_float
 	FREG_S	fa0, sp, 9*SZREG + 0*SZFREG
 	FREG_S	fa1, sp, 9*SZREG + 1*SZFREG
@@ -92,23 +92,23 @@ ENTRY (_dl_runtime_resolve)
 	REG_L	a7, sp, 8*SZREG
 
 #ifdef USE_LASX
-	xvld	xr0, sp, 9*SZREG + 8*SZFREG + 0*SZXREG
-	xvld	xr1, sp, 9*SZREG + 8*SZFREG + 1*SZXREG
-	xvld	xr2, sp, 9*SZREG + 8*SZFREG + 2*SZXREG
-	xvld	xr3, sp, 9*SZREG + 8*SZFREG + 3*SZXREG
-	xvld	xr4, sp, 9*SZREG + 8*SZFREG + 4*SZXREG
-	xvld	xr5, sp, 9*SZREG + 8*SZFREG + 5*SZXREG
-	xvld	xr6, sp, 9*SZREG + 8*SZFREG + 6*SZXREG
-	xvld	xr7, sp, 9*SZREG + 8*SZFREG + 7*SZXREG
+	xvld	xr0, sp, 9*SZREG + 0*SZXREG
+	xvld	xr1, sp, 9*SZREG + 1*SZXREG
+	xvld	xr2, sp, 9*SZREG + 2*SZXREG
+	xvld	xr3, sp, 9*SZREG + 3*SZXREG
+	xvld	xr4, sp, 9*SZREG + 4*SZXREG
+	xvld	xr5, sp, 9*SZREG + 5*SZXREG
+	xvld	xr6, sp, 9*SZREG + 6*SZXREG
+	xvld	xr7, sp, 9*SZREG + 7*SZXREG
 #elif defined USE_LSX
-	vld	vr0, sp, 9*SZREG + 8*SZFREG + 0*SZVREG
-	vld	vr1, sp, 9*SZREG + 8*SZFREG + 1*SZVREG
-	vld	vr2, sp, 9*SZREG + 8*SZFREG + 2*SZVREG
-	vld	vr3, sp, 9*SZREG + 8*SZFREG + 3*SZVREG
-	vld	vr4, sp, 9*SZREG + 8*SZFREG + 4*SZVREG
-	vld	vr5, sp, 9*SZREG + 8*SZFREG + 5*SZVREG
-	vld	vr6, sp, 9*SZREG + 8*SZFREG + 6*SZVREG
-	vld	vr7, sp, 9*SZREG + 8*SZFREG + 7*SZVREG
+	vld	vr0, sp, 9*SZREG + 0*SZVREG
+	vld	vr1, sp, 9*SZREG + 1*SZVREG
+	vld	vr2, sp, 9*SZREG + 2*SZVREG
+	vld	vr3, sp, 9*SZREG + 3*SZVREG
+	vld	vr4, sp, 9*SZREG + 4*SZVREG
+	vld	vr5, sp, 9*SZREG + 5*SZVREG
+	vld	vr6, sp, 9*SZREG + 6*SZVREG
+	vld	vr7, sp, 9*SZREG + 7*SZVREG
 #elif !defined __loongarch_soft_float
 	FREG_L	fa0, sp, 9*SZREG + 0*SZFREG
 	FREG_L	fa1, sp, 9*SZREG + 1*SZFREG

                 reply	other threads:[~2023-12-13  2:03 UTC|newest]

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