From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1791) id 867E13858427; Wed, 7 Feb 2024 14:07:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 867E13858427 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1707314870; bh=+a04Vq96WhfMqsJ1ueUEpDs5L6KVnwxQtBWadjlqxtM=; h=From:To:Subject:Date:From; b=AhNCrnDZMcj5iYykQ+hEcWl19RXrapsWtsf50b7ocSItlndsW0+XBs13H/JBlYeMF /Y3doFODvsEUPMl4MG4+22k9spCzB0q7ewwEE8Nm7t/yh4Dk/YoDwU7buL1HWSsr/K CeUa4CicvMVvWVOGRScu6SWyzvKJdHKCTDPxlZDc= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Adhemerval Zanella To: glibc-cvs@sourceware.org Subject: [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers X-Act-Checkin: glibc X-Git-Author: Adhemerval Zanella X-Git-Refname: refs/heads/azanella/clang X-Git-Oldrev: 4b26cd2ef61f90ed0ee1b73a2614e7a7d5bda04c X-Git-Newrev: cef28530dc50d397ca764f648268c2d180441348 Message-Id: <20240207140750.867E13858427@sourceware.org> Date: Wed, 7 Feb 2024 14:07:50 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=cef28530dc50d397ca764f648268c2d180441348 commit cef28530dc50d397ca764f648268c2d180441348 Author: Adhemerval Zanella Date: Tue Mar 15 18:08:21 2022 -0300 aarch64: Use 64-bit variable to access the special registers clang issues: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths] while tryng to use 32 bit variables with 'mrs' to get/set the fpsr, dczid_el0, and ctr. Since all of 64 bit register, use the expected variable size. Diff: --- sysdeps/aarch64/fpu/fpu_control.h | 36 ++++++++++++++++++-------- sysdeps/aarch64/fpu/fraiseexcpt.c | 2 +- sysdeps/aarch64/sfp-machine.h | 2 +- sysdeps/unix/sysv/linux/aarch64/cpu-features.c | 2 +- sysdeps/unix/sysv/linux/aarch64/sysconf.c | 2 +- 5 files changed, 29 insertions(+), 15 deletions(-) diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 263cf36c05..743c2e5b15 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -29,17 +29,31 @@ # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) #else -# define _FPU_GETCW(fpcr) \ - __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) - -# define _FPU_SETCW(fpcr) \ - __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) - -# define _FPU_GETFPSR(fpsr) \ - __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr)) - -# define _FPU_SETFPSR(fpsr) \ - __asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr)) +# define _FPU_GETCW(fpcr) \ + ({ \ + unsigned long int __fpcr; \ + __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (__fpcr)); \ + fpcr = __fpcr; \ + }) + +# define _FPU_SETCW(fpcr) \ + ({ \ + unsigned long int __fpcr = fpcr; \ + __asm__ __volatile__ ("msr fpcr, %0" : : "r" (__fpcr)); \ + }) + +# define _FPU_GETFPSR(fpsr) \ + ({ \ + unsigned long int __fpsr; \ + __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (__fpsr)); \ + fpsr = __fpsr; \ + }) + +# define _FPU_SETFPSR(fpsr) \ + ({ \ + unsigned long int __fpsr = fpsr; \ + __asm__ __volatile__ ("msr fpsr, %0" : : "r" (__fpsr)); \ + }) #endif /* Reserved bits should be preserved when modifying register diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c index 5abf498443..c48ba50777 100644 --- a/sysdeps/aarch64/fpu/fraiseexcpt.c +++ b/sysdeps/aarch64/fpu/fraiseexcpt.c @@ -23,7 +23,7 @@ int __feraiseexcept (int excepts) { - int fpsr; + unsigned long int fpsr; const float fp_zero = 0.0; const float fp_one = 1.0; const float fp_max = FLT_MAX; diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h index a9ecdbf961..b4b34e98e9 100644 --- a/sysdeps/aarch64/sfp-machine.h +++ b/sysdeps/aarch64/sfp-machine.h @@ -74,7 +74,7 @@ do { \ const float fp_1e32 = 1.0e32f; \ const float fp_zero = 0.0; \ const float fp_one = 1.0; \ - unsigned fpsr; \ + unsigned long int fpsr; \ if (_fex & FP_EX_INVALID) \ { \ __asm__ __volatile__ ("fdiv\ts0, %s0, %s0" \ diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index b1a3f673f0..b5ab7d51fe 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -87,7 +87,7 @@ init_cpu_features (struct cpu_features *cpu_features) cpu_features->midr_el1 = midr; /* Check if ZVA is enabled. */ - unsigned dczid; + uint64_t dczid; asm volatile ("mrs %0, dczid_el0" : "=r"(dczid)); if ((dczid & DCZID_DZP_MASK) == 0) diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c index 6c8216e95a..657df5d845 100644 --- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c +++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c @@ -27,7 +27,7 @@ static long int linux_sysconf (int name); long int __sysconf (int name) { - unsigned ctr; + unsigned long int ctr; /* Unfortunately, the registers that contain the actual cache info (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux