From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12198 invoked by alias); 28 May 2011 01:08:03 -0000 Received: (qmail 12178 invoked by uid 22791); 28 May 2011 01:08:02 -0000 X-SWARE-Spam-Status: No, hits=-1.3 required=5.0 tests=AWL,BAYES_00,NO_DNS_FOR_FROM,TW_GC,TW_HG,TW_PX,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 28 May 2011 01:07:48 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 27 May 2011 18:07:47 -0700 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by orsmga001.jf.intel.com with ESMTP; 27 May 2011 18:07:47 -0700 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id D2967180D86; Fri, 27 May 2011 18:07:46 -0700 (PDT) Date: Sat, 28 May 2011 01:08:00 -0000 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org, java-patches@gcc.gnu.org Subject: PATCH: PR libgcj/49193: __sync_xxxx builtins aren't used in sysdep/*/locks.h Message-ID: <20110528010746.GA13079@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact java-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: java-patches-owner@gcc.gnu.org X-SW-Source: 2011-q2/txt/msg00061.txt.bz2 Hi, This patch uses __sync_bool_compare_and_swap and removes sysdep/x86-64/locks.h. OK for trunk if there is no regression? Thanks. H.J. --- 2011-05-27 H.J. Lu PR libgcj/49193 * configure.host (sysdeps_dir): Set to i386 for x86_64. * sysdep/i386/locks.h (compare_and_swap): Call __sync_bool_compare_and_swap. (release_set): Call write_barrier (). * sysdep/x86-64/locks.h: Removed. diff --git a/libjava/configure.host b/libjava/configure.host index 5b88478..9d4f2b6 100644 --- a/libjava/configure.host +++ b/libjava/configure.host @@ -132,7 +132,7 @@ case "${host}" in slow_pthread_self=yes ;; x86_64-*) - sysdeps_dir=x86-64 + sysdeps_dir=i386 # For 64-bit we always use SSE registers for arithmetic, # which doesn't have the extra precision problems of the fpu. # But be careful about 32-bit multilibs. @@ -279,7 +279,7 @@ EOF slow_pthread_self= ;; i[34567]86-*-solaris2.1[0-9]* ) - sysdeps_dir=x86-64 + sysdeps_dir=i386 DIVIDESPEC=-f%{m32:no-}%{!m32:%{!m64:no-}}%{m64:}use-divide-subroutine ;; mips-sgi-irix6* ) diff --git a/libjava/sysdep/i386/locks.h b/libjava/sysdep/i386/locks.h index 9d130b0..7b99f0b 100644 --- a/libjava/sysdep/i386/locks.h +++ b/libjava/sysdep/i386/locks.h @@ -1,6 +1,6 @@ /* locks.h - Thread synchronization primitives. X86/x86-64 implementation. - Copyright (C) 2002 Free Software Foundation + Copyright (C) 2002, 2011 Free Software Foundation This file is part of libgcj. @@ -23,19 +23,25 @@ compare_and_swap(volatile obj_addr_t *addr, obj_addr_t old, obj_addr_t new_val) { - char result; -#ifdef __x86_64__ - __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1" - : "=m"(*(addr)), "=q"(result) - : "r" (new_val), "a"(old), "m"(*addr) - : "memory"); -#else - __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1" - : "=m"(*addr), "=q"(result) - : "r" (new_val), "a"(old), "m"(*addr) - : "memory"); -#endif - return (bool) result; + return __sync_bool_compare_and_swap (addr, old, new_val); +} + +// Ensure that subsequent instructions do not execute on stale +// data that was loaded from memory before the barrier. +// On X86/x86-64, the hardware ensures that reads are properly ordered. +inline static void +read_barrier() +{ +} + +// Ensure that prior stores to memory are completed with respect to other +// processors. +inline static void +write_barrier() +{ + /* x86-64/X86 does not reorder writes. We just need to ensure that + gcc also doesn't. */ + __asm__ __volatile__(" " : : : "memory"); } // Set *addr to new_val with release semantics, i.e. making sure @@ -46,7 +52,7 @@ compare_and_swap(volatile obj_addr_t *addr, inline static void release_set(volatile obj_addr_t *addr, obj_addr_t new_val) { - __asm__ __volatile__(" " : : : "memory"); + write_barrier (); *(addr) = new_val; } @@ -60,22 +66,4 @@ compare_and_swap_release(volatile obj_addr_t *addr, { return compare_and_swap(addr, old, new_val); } - -// Ensure that subsequent instructions do not execute on stale -// data that was loaded from memory before the barrier. -// On X86/x86-64, the hardware ensures that reads are properly ordered. -inline static void -read_barrier() -{ -} - -// Ensure that prior stores to memory are completed with respect to other -// processors. -inline static void -write_barrier() -{ - /* x86-64/X86 does not reorder writes. We just need to ensure that - gcc also doesn't. */ - __asm__ __volatile__(" " : : : "memory"); -} #endif diff --git a/libjava/sysdep/x86-64/locks.h b/libjava/sysdep/x86-64/locks.h deleted file mode 100644 index fdc0a3e..0000000 --- a/libjava/sysdep/x86-64/locks.h +++ /dev/null @@ -1,83 +0,0 @@ -/* locks.h - Thread synchronization primitives. X86/x86-64 implementation. - - Copyright (C) 2002 Free Software Foundation - - Contributed by Bo Thorsen . - - This file is part of libgcj. - -This software is copyrighted work licensed under the terms of the -Libgcj License. Please consult the file "LIBGCJ_LICENSE" for -details. */ - -#ifndef __SYSDEP_LOCKS_H__ -#define __SYSDEP_LOCKS_H__ - -typedef size_t obj_addr_t; /* Integer type big enough for object */ - /* address. */ - -// Atomically replace *addr by new_val if it was initially equal to old. -// Return true if the comparison succeeded. -// Assumed to have acquire semantics, i.e. later memory operations -// cannot execute before the compare_and_swap finishes. -inline static bool -compare_and_swap(volatile obj_addr_t *addr, - obj_addr_t old, - obj_addr_t new_val) -{ - char result; -#ifdef __x86_64__ - __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1" - : "=m"(*(addr)), "=q"(result) - : "r" (new_val), "a"(old), "m"(*addr) - : "memory"); -#else - __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1" - : "=m"(*addr), "=q"(result) - : "r" (new_val), "a"(old), "m"(*addr) - : "memory"); -#endif - return (bool) result; -} - -// Set *addr to new_val with release semantics, i.e. making sure -// that prior loads and stores complete before this -// assignment. -// On X86/x86-64, the hardware shouldn't reorder reads and writes, -// so we just have to convince gcc not to do it either. -inline static void -release_set(volatile obj_addr_t *addr, obj_addr_t new_val) -{ - __asm__ __volatile__(" " : : : "memory"); - *(addr) = new_val; -} - -// Compare_and_swap with release semantics instead of acquire semantics. -// On many architecture, the operation makes both guarantees, so the -// implementation can be the same. -inline static bool -compare_and_swap_release(volatile obj_addr_t *addr, - obj_addr_t old, - obj_addr_t new_val) -{ - return compare_and_swap(addr, old, new_val); -} - -// Ensure that subsequent instructions do not execute on stale -// data that was loaded from memory before the barrier. -// On X86/x86-64, the hardware ensures that reads are properly ordered. -inline static void -read_barrier() -{ -} - -// Ensure that prior stores to memory are completed with respect to other -// processors. -inline static void -write_barrier() -{ - /* x86-64/X86 does not reorder writes. We just need to ensure that - gcc also doesn't. */ - __asm__ __volatile__(" " : : : "memory"); -} -#endif