From: Richard Henderson <rth@redhat.com>
To: Jeff Sturm <jsturm@one-point.com>
Cc: Bryce McKinlay <bryce@waitaki.otago.ac.nz>,
tromey@redhat.com, Dan Nicolaescu <dann@godzilla.ics.uci.edu>,
java@gcc.gnu.org, gcc@gcc.gnu.org
Subject: Re: java aliasing rules
Date: Sat, 30 Mar 2002 13:55:00 -0000 [thread overview]
Message-ID: <20020330135503.A20655@redhat.com> (raw)
In-Reply-To: <Pine.LNX.4.10.10203300926250.5677-100000@mars.deadcafe.org>; from jsturm@one-point.com on Sat, Mar 30, 2002 at 09:35:54AM -0500
On Sat, Mar 30, 2002 at 09:35:54AM -0500, Jeff Sturm wrote:
> Wouldn't accessing r9 immediately after the load cause a pipeline stall?
Yes.
> Come to think of it, what happens on an out-of-order processor (e.g.
> Alpha EV6) when an instruction traps? Are preceding instructions
> guaranteed to have completed? I'm curious.
Yes. All the instructions before hand are committed, and all
of the in-flight instruction after are aborted.
r~
next prev parent reply other threads:[~2002-03-30 21:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-03-27 11:43 Dan Nicolaescu
2002-03-27 13:53 ` Tom Tromey
2002-03-27 16:03 ` Dan Nicolaescu
2002-03-27 16:47 ` Tom Tromey
2002-03-27 20:00 ` Dan Nicolaescu
2002-03-27 15:54 ` Bryce McKinlay
2002-03-27 16:45 ` Tom Tromey
2002-03-28 22:02 ` Bryce McKinlay
2002-03-28 22:13 ` Richard Henderson
2002-03-28 22:15 ` Tom Tromey
2002-03-29 15:22 ` Bryce McKinlay
2002-03-29 16:26 ` Richard Henderson
2002-03-30 6:37 ` Jeff Sturm
2002-03-30 13:55 ` Richard Henderson [this message]
2002-03-30 15:04 ` Bryce McKinlay
2002-04-04 10:57 ` Jeff Sturm
2002-04-04 12:57 ` Andrew Haley
2002-04-04 14:20 ` Jeff Sturm
2002-04-04 17:04 ` Bryce McKinlay
2002-04-04 20:39 ` Jeff Sturm
2002-04-05 1:07 ` Bryce McKinlay
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