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Content-Transfer-Encoding: quoted-printable In-Reply-To: Cc: Mime-Version: 1.0 References: <20231225103548.1615-2-zhujunxian@oss.cipunited.com> <20231225103548.1615-4-zhujunxian@oss.cipunited.com> X-Lms-Return-Path: From: "Junxian Zhu" Date: Tue, 2 Jan 2024 17:51:24 +0800 User-Agent: Mozilla Thunderbird Received: from [192.168.8.110] ([171.15.158.108]) by smtp.feishu.cn with ESMTPS; Tue, 02 Jan 2024 17:51:25 +0800 Subject: Re: [PATCH 2/2] MIPS: Hard-float rounding instructions support Message-Id: <00bdff38-7446-4815-bc90-96203e4a473a@oss.cipunited.com> X-Original-From: Junxian Zhu Content-Type: text/plain; charset=UTF-8 To: "YunQiang Su" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_SHORT,NO_DNS_FOR_FROM,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: =E5=9C=A8 2023/12/25 20:36, YunQiang Su =E5=86=99=E9=81=93: > > Junxian Zhu =E4=BA=8E 2023=E5=B9=B412=E6= =9C=8825=E6=97=A5=E5=91=A8=E4=B8=80=20 > 18:38=E5=86=99=E9=81=93=EF=BC=9A > > From: Junxian Zhu > > Use hardware floating-point rounding instructions to implement > roundeven, trunc, ceil and floor. > > * sysdeps/mips/mips32/Implies: Add source path. > * sysdeps/mips/mips64/Implies: Likewise. > * sysdeps/mips/fpu/Makefile: Newfile. > * sysdeps/mips/fpu/s_ceil.c: Likewise. > * sysdeps/mips/fpu/s_ceil_fpu.S: Likewise. > * sysdeps/mips/fpu/s_ceilf.c: Likewise. > * sysdeps/mips/fpu/s_ceilf_fpu.S: Likewise. > * sysdeps/mips/fpu/s_floor.c: Likewise. > * sysdeps/mips/fpu/s_floor_fpu.S: Likewise. > * sysdeps/mips/fpu/s_floorf.c: Likewise. > * sysdeps/mips/fpu/s_floorf_fpu.S: Likewise. > * sysdeps/mips/fpu/s_roundeven.c: Likewise. > * sysdeps/mips/fpu/s_roundeven_fpu.S: Likewise. > * sysdeps/mips/fpu/s_roundevenf.c: Likewise. > * sysdeps/mips/fpu/s_roundevenf_fpu.S: Likewise. > * sysdeps/mips/fpu/s_trunc.c: Likewise. > * sysdeps/mips/fpu/s_trunc_fpu.S: Likewise. > * sysdeps/mips/fpu/s_truncf.c: Likewise. > * sysdeps/mips/fpu/s_truncf_fpu.S: Likewise. > > Signed-off-by: Rong Zhang > Signed-off-by: Junxian Zhu > --- > =C2=A0sysdeps/mips/fpu/Makefile=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0| 12 ++++ > =C2=A0sysdeps/mips/fpu/s_ceil.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0| 30 ++++++++++ > =C2=A0sysdeps/mips/fpu/s_ceil_fpu.S=C2=A0 =C2=A0 =C2=A0 =C2=A0| 90 > +++++++++++++++++++++++++++++ > =C2=A0sysdeps/mips/fpu/s_ceilf.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | = 30 ++++++++++ > =C2=A0sysdeps/mips/fpu/s_ceilf_fpu.S=C2=A0 =C2=A0 =C2=A0 | 82 +++++++= +++++++++++++++++++ > =C2=A0sysdeps/mips/fpu/s_floor.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | = 24 ++++++++ > =C2=A0sysdeps/mips/fpu/s_floor_fpu.S=C2=A0 =C2=A0 =C2=A0 | 88 +++++++= +++++++++++++++++++++ > =C2=A0sysdeps/mips/fpu/s_floorf.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| = 24 ++++++++ > =C2=A0sysdeps/mips/fpu/s_floorf_fpu.S=C2=A0 =C2=A0 =C2=A0| 80 +++++++= ++++++++++++++++++ > =C2=A0sysdeps/mips/fpu/s_roundeven.c=C2=A0 =C2=A0 =C2=A0 | 24 +++++++= + > =C2=A0sysdeps/mips/fpu/s_roundeven_fpu.S=C2=A0 | 87 +++++++++++++++++= +++++++++++ > =C2=A0sysdeps/mips/fpu/s_roundevenf.c=C2=A0 =C2=A0 =C2=A0| 24 +++++++= + > =C2=A0sysdeps/mips/fpu/s_roundevenf_fpu.S | 79 ++++++++++++++++++++++= +++ > =C2=A0sysdeps/mips/fpu/s_trunc.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | = 24 ++++++++ > =C2=A0sysdeps/mips/fpu/s_trunc_fpu.S=C2=A0 =C2=A0 =C2=A0 | 84 +++++++= ++++++++++++++++++++ > =C2=A0sysdeps/mips/fpu/s_truncf.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| = 24 ++++++++ > =C2=A0sysdeps/mips/fpu/s_truncf_fpu.S=C2=A0 =C2=A0 =C2=A0| 76 +++++++= +++++++++++++++++ > =C2=A0sysdeps/mips/mips32/Implies=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 1 + > =C2=A0sysdeps/mips/mips64/Implies=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 1 + > =C2=A019 files changed, 884 insertions(+) > =C2=A0create mode 100644 sysdeps/mips/fpu/Makefile > =C2=A0create mode 100644 sysdeps/mips/fpu/s_ceil.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_ceil_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_ceilf.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_ceilf_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_floor.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_floor_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_floorf.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_floorf_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_roundeven.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_roundeven_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_roundevenf.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_roundevenf_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_trunc.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_trunc_fpu.S > =C2=A0create mode 100644 sysdeps/mips/fpu/s_truncf.c > =C2=A0create mode 100644 sysdeps/mips/fpu/s_truncf_fpu.S > > diff --git a/sysdeps/mips/fpu/Makefile b/sysdeps/mips/fpu/Makefile > new file mode 100644 > index 0000000000..ad537d6bf1 > --- /dev/null > +++ b/sysdeps/mips/fpu/Makefile > @@ -0,0 +1,12 @@ > +ifeq ($(subdir),math) > +sysdep_routines +=3D s_floor_fpu s_floorf_fpu \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s_ceil_fpu s_ceilf_fpu \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s_trunc_fpu s_truncf_fpu \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s_roundeven_fpu s_roundevenf_fpu > + > +libm-sysdep_routines +=3D s_floor_fpu s_floorf_fpu \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s_ceil_fpu s_ceilf_fpu \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s_trunc_fpu s_truncf_fpu \ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0s_roundeven_fpu s_roundevenf_fpu > + > +endif > diff --git a/sysdeps/mips/fpu/s_ceil.c b/sysdeps/mips/fpu/s_ceil.c > new file mode 100644 > index 0000000000..91a90a70c5 > --- /dev/null > +++ b/sysdeps/mips/fpu/s_ceil.c > @@ -0,0 +1,30 @@ > +/* Copyright (C) 2023 Free Software Foundation, Inc. > +=C2=A0 =C2=A0This file is part of the GNU C Library. > + > +=C2=A0 =C2=A0The GNU C Library is free software; you can redistribut= e it and/or > +=C2=A0 =C2=A0modify it under the terms of the GNU Lesser General Pub= lic > +=C2=A0 =C2=A0License as published by the Free Software Foundation; e= ither > +=C2=A0 =C2=A0version 2.1 of the License, or (at your option) any lat= er version. > + > +=C2=A0 =C2=A0The GNU C Library is distributed in the hope that it wi= ll be > useful, > +=C2=A0 =C2=A0but WITHOUT ANY WARRANTY; without even the implied warr= anty of > +=C2=A0 =C2=A0MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Se= e the GNU > +=C2=A0 =C2=A0Lesser General Public License for more details. > + > +=C2=A0 =C2=A0You should have received a copy of the GNU Lesser Gener= al Public > +=C2=A0 =C2=A0License along with the GNU C Library.=C2=A0 If not, see > +=C2=A0 =C2=A0. */ > + > +/* > + * ceil(x) > + * Return x rounded toward -inf to integral value > + * Method: > + *=C2=A0 =C2=A0 =C2=A0Bit twiddling. > + */ > + > +#if !((__mips_fpr =3D=3D 64) && (__mips_hard_float =3D=3D 1)=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \ > +=C2=A0 =C2=A0 =C2=A0 && ((__mips =3D=3D 32 && __mips_isa_rev > 1) ||= __mips =3D=3D 64)) > + > > > __mips_fpr =3D=3D 64 > this condition should not be here. > it means fp64. > In fact your code should also support fp32 and fpxx. > The MIPS instruction=C2=A0documentation has=C2=A0specifies restrictions for= the=20 ceil, round, floor and trunc. "The result of this instruction is=20 UNPREDICTABLE if the processor is executing in the FR=3D0 32-bit FPU=20 register model; it is predictable if executing on a 64-bit FPU in the=20 FR=3D1 mode, but not with FR=3D0, and not on a 32-bit FPU." And fp64 ABI is the only=C2=A0configuration that restricts FPU work in FR= =3D1=20 mode.