From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTP id DD9283858D37 for ; Sun, 12 Feb 2023 06:30:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD9283858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=isrc.iscas.ac.cn Received: from [192.168.223.33] (unknown [101.6.102.102]) by APP-05 (Coremail) with SMTP id zQCowAA3PfVvh+hjGXPNBA--.24809S2; Sun, 12 Feb 2023 14:30:07 +0800 (CST) Message-ID: <0e733efc-2f2a-bfb6-44e3-c053f2d41f34@isrc.iscas.ac.cn> Date: Sun, 12 Feb 2023 14:29:57 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH] riscv: Add macros for FPUCW in fpu_control.h To: Andreas Schwab Cc: libc-alpha@sourceware.org References: <20230211174916.1455-1-shiqi@isrc.iscas.ac.cn> <87357cvtpo.fsf@igel.home> From: Shiqi Zhang In-Reply-To: <87357cvtpo.fsf@igel.home> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CM-TRANSID:zQCowAA3PfVvh+hjGXPNBA--.24809S2 X-Coremail-Antispam: 1UD129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73 VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUUYn7k0a2IF6w4kM7kC6x804xWl14x267AK xVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWUuVWrJwAFIxvE14AKwVWUJVWUGw A2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r1j 6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr 0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv 0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z2 80aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcVAKI48JMxk0xIA0c2IE e2xFo4CEbIxvr21l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxV Aqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1Y 6r17MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6x kF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvj xUgmFCUUUUU X-Originating-IP: [101.6.102.102] X-CM-SenderInfo: 5vkl1xw6lv2u4olvutnvoduhdfq/ X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,FORGED_SPF_HELO,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: >> +# define _FPU_RM_DYN (7 << 5) > That is only valid in an insn encoding, not in the fcsr register. Thank you very much for the tip! >> +/* FPU accrued exception flags */ >> +# define _FPU_EXCEPT_NV (1 << 0) >> +# define _FPU_EXCEPT_NZ (1 << 1) >> +# define _FPU_EXCEPT_OF (1 << 2) >> +# define _FPU_EXCEPT_UF (1 << 3) >> +# define _FPU_EXCEPT_NX (1 << 4) > You got them backwards. Sorry for my carelessness. I mistakenly assumed that flags in table 11.2 was listed from lower to higher bits. Will send a v2 soon.