From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23955 invoked by alias); 9 Nov 2016 17:08:22 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 23945 invoked by uid 89); 9 Nov 2016 17:08:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.8 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=HTo:U*davem, weekend, sparcv8, LEON X-HELO: mx1.redhat.com Message-ID: <1478711295.7146.969.camel@localhost.localdomain> Subject: Re: Remove sparcv8 support From: Torvald Riegel To: David Miller Cc: carlos@redhat.com, adhemerval.zanella@linaro.org, andreas@gaisler.com, libc-alpha@sourceware.org, software@gaisler.com Date: Wed, 09 Nov 2016 17:08:00 -0000 In-Reply-To: <20161107.113825.631166023186879199.davem@davemloft.net> References: <20161026.144741.1659367414224835783.davem@davemloft.net> <1477565575.7146.199.camel@localhost.localdomain> <502720f6-3057-41f5-7832-4b219f5f729f@redhat.com> <20161107.113825.631166023186879199.davem@davemloft.net> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SW-Source: 2016-11/txt/msg00346.txt.bz2 On Mon, 2016-11-07 at 11:38 -0500, David Miller wrote: > > So the following attached is what I started playing around with this > weekend. > > It implements software trap "0x23" to perform a CAS operations, the > operands are expected in registers %o0, %o1, and %o2. > > Since it was easiest to test I implemented this first on sparc64 which > just executes the CAS instruction directly. I'll start working on the > 32-bit part in the background. > > The capability will be advertised via the mask returned by the "get > kernel features" system call. We could check this early in the > crt'ish code and cache the value in a variable which the atomics can > check. > > Another kernel side change I have to do is advertise the LEON CAS > availability in the _dl_hwcaps so that we can use the LEON CAS in > glibc when available. > > The first patch is the kernel side, and the second is the glibc side. > The whole NPTL testsuite passes for the plain 32-bit sparc target with > these changes. What approach are you going to use in the kernel to emulate the CAS if the hardware doesn't offer one? If you are not stopping all threads, then there could be concurrent stores to the same memory location targeted by the CAS; to make such stores atomic wrt. the CAS, you would need to implement atomic stores in glibc to also use the kernel (eg, to do a CAS). I didn't see this in the glibc patch you sent, so I thought I'd ask.