From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ZXSHCAS1.zhaoxin.com (unknown [203.148.12.81]) by sourceware.org (Postfix) with ESMTPS id 07911385B835 for ; Mon, 30 Mar 2020 05:33:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 07911385B835 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=MayShao@zhaoxin.com Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 30 Mar 2020 13:33:53 +0800 Received: from dmdba-HX001EM2.zhaoxin.com (10.29.8.4) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 30 Mar 2020 13:33:52 +0800 From: MayShao To: CC: , , , , Subject: [PATCH v2 2/3] x86: Add cache information support for Zhaoxin processors Date: Mon, 30 Mar 2020 13:33:49 +0800 Message-ID: <1585546430-6167-3-git-send-email-MayShao@zhaoxin.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585546430-6167-1-git-send-email-MayShao@zhaoxin.com> References: <1585546430-6167-1-git-send-email-MayShao@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Originating-IP: [10.29.8.4] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To zxbjmbx1.zhaoxin.com (10.29.252.163) Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-22.3 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Mar 2020 05:34:01 -0000 To obtain Zhaoxin CPU cache information, add a new function handle_zhaoxin(). Add Zhaoxin branch in init_cacheinfo() for initializing variables, such as __x86_shared_cache_size. --- sysdeps/x86/cacheinfo.c | 185 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 185 insertions(+) diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index e3e8ef2..e5a3284 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -436,6 +436,57 @@ handle_amd (int name) } +static long int __attribute__ ((noinline)) +handle_zhaoxin (int name) +{ + unsigned int eax; + unsigned int ebx; + unsigned int ecx; + unsigned int edx; + + int folded_rel_name =3D (M(name) / 3) * 3; + + unsigned int round =3D 0; + while (1) + { + __cpuid_count (4, round, eax, ebx, ecx, edx); + + enum { null =3D 0, data =3D 1, inst =3D 2, uni =3D 3 } type =3D eax = & 0x1f; + if (type =3D=3D null) + break; + + unsigned int level =3D (eax >> 5) & 0x7; + + if ((level =3D=3D 1 && type =3D=3D data + && folded_rel_name =3D=3D M(_SC_LEVEL1_DCACHE_SIZE)) + || (level =3D=3D 1 && type =3D=3D inst + && folded_rel_name =3D=3D M(_SC_LEVEL1_ICACHE_SIZE)) + || (level =3D=3D 2 && folded_rel_name =3D=3D M(_SC_LEVEL2_CACHE_SI= ZE)) + || (level =3D=3D 3 && folded_rel_name =3D=3D M(_SC_LEVEL3_CACHE_SI= ZE))) + { + unsigned int offset =3D M(name) - folded_rel_name; + + if (offset =3D=3D 0) + /* Cache size. */ + return (((ebx >> 22) + 1) + * (((ebx >> 12) & 0x3ff) + 1) + * ((ebx & 0xfff) + 1) + * (ecx + 1)); + if (offset =3D=3D 1) + return (ebx >> 22) + 1; + + assert (offset =3D=3D 2); + return (ebx & 0xfff) + 1; + } + + ++round; + } + + /* Nothing found. */ + return 0; +} + + /* Get the value of the system variable NAME. */ long int attribute_hidden @@ -449,6 +500,9 @@ __cache_sysconf (int name) if (cpu_features->basic.kind =3D=3D arch_kind_amd) return handle_amd (name); + if (cpu_features->basic.kind =3D=3D arch_kind_zhaoxin) + return handle_zhaoxin (name); + // XXX Fill in more vendors. /* CPU not known, we have no information. */ @@ -751,6 +805,137 @@ intel_bug_no_cache_info: } #endif } + else if (cpu_features->basic.kind =3D=3D arch_kind_zhaoxin) + { + data =3D handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); + long int core =3D handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); + shared =3D handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); + + /* Number of logical processors sharing L2 cache. */ + int threads_l2; + + /* Number of logical processors sharing L3 cache. */ + int threads_l3; + + if (shared <=3D 0) + { + /* No shared L3 cache. All we have is the L2 cache. */ + level =3D 2; + shared =3D core; + threads_l2 =3D 0; + threads_l3 =3D -1; + } + else + { + level =3D 3; + threads_l2 =3D 0; + threads_l3 =3D 0; + } + + int i =3D 0; + + /* Query until cache level 2 and 3 are enumerated. */ + int check =3D 0x1 | (threads_l3 =3D=3D 0) << 1; + do + { + __cpuid_count (4, i++, eax, ebx, ecx, edx); + + switch ((eax >> 5) & 0x7) + { + default: + break; + case 2: + if ((check & 0x1)) + { + /* Get maximum number of logical processors + sharing L2 cache. */ + threads_l2 =3D (eax >> 14) & 0x3ff; + check &=3D ~0x1; + } + break; + case 3: + if ((check & (0x1 << 1))) + { + /* Get maximum number of logical processors + sharing L3 cache. */ + threads_l3 =3D (eax >> 14) & 0x3ff; + check &=3D ~(0x1 << 1); + } + break; + } + } + while (check); + + /* If max_cpuid >=3D 11, THREADS_L2/THREADS_L3 are the maximum + numbers of addressable IDs for logical processors sharing + the cache, instead of the maximum number of threads + sharing the cache. */ + if (max_cpuid >=3D 11) + { + /* Find the number of logical processors shipped in + one core and apply count mask. */ + i =3D 0; + + /* Count SMT only if there is L3 cache. Always count + core if there is no L3 cache. */ + int count =3D ((threads_l2 > 0 && level =3D=3D 3) + | ((threads_l3 > 0 + || (threads_l2 > 0 && level =3D=3D 2)) << 1)); + + while (count) + { + __cpuid_count (11, i++, eax, ebx, ecx, edx); + + int shipped =3D ebx & 0xff; + int type =3D ecx & 0xff00; + if (shipped =3D=3D 0 || type =3D=3D 0) + break; + else if (type =3D=3D 0x100) + { + /* Count SMT. */ + if ((count & 0x1)) + { + int count_mask; + + /* Compute count mask. */ + asm ("bsr %1, %0" + : "=3Dr" (count_mask) : "g" (threads_l2)); + count_mask =3D ~(-1 << (count_mask + 1)); + threads_l2 =3D (shipped - 1) & count_mask; + count &=3D ~0x1; + } + } + else if (type =3D=3D 0x200) + { + /* Count core. */ + if ((count & (0x1 << 1))) + { + int count_mask; + int threads_core + =3D (level =3D=3D 2 ? threads_l2 : threads_l3); + + /* Compute count mask. */ + asm ("bsr %1, %0" + : "=3Dr" (count_mask) : "g" (threads_core)); + count_mask =3D ~(-1 << (count_mask + 1)); + threads_core =3D (shipped - 1) & count_mask; + if (level =3D=3D 2) + threads_l2 =3D threads_core; + else + threads_l3 =3D threads_core; + count &=3D ~(0x1 << 1); + } + } + } + } + if (level =3D=3D 2 && threads_l2 > 0) + threads =3D threads_l2 + 1; + if (level =3D=3D 3 && threads_l3 > 0) + threads =3D threads_l3 + 1; + + if (shared > 0 && threads > 0) + shared /=3D threads; + } if (cpu_features->data_cache_size !=3D 0) data =3D cpu_features->data_cache_size; -- 2.7.4 =E4=BF=9D=E5=AF=86=E5=A3=B0=E6=98=8E=EF=BC=9A =E6=9C=AC=E9=82=AE=E4=BB=B6=E5=90=AB=E6=9C=89=E4=BF=9D=E5=AF=86=E6=88=96=E4= =B8=93=E6=9C=89=E4=BF=A1=E6=81=AF=EF=BC=8C=E4=BB=85=E4=BE=9B=E6=8C=87=E5=AE= =9A=E6=94=B6=E4=BB=B6=E4=BA=BA=E4=BD=BF=E7=94=A8=E3=80=82=E4=B8=A5=E7=A6=81= =E5=AF=B9=E6=9C=AC=E9=82=AE=E4=BB=B6=E6=88=96=E5=85=B6=E5=86=85=E5=AE=B9=E5= =81=9A=E4=BB=BB=E4=BD=95=E6=9C=AA=E7=BB=8F=E6=8E=88=E6=9D=83=E7=9A=84=E6=9F= =A5=E9=98=85=E3=80=81=E4=BD=BF=E7=94=A8=E3=80=81=E5=A4=8D=E5=88=B6=E6=88=96= =E8=BD=AC=E5=8F=91=E3=80=82 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is f= or the sole use of its intended recipient. Any unauthorized review, use, co= pying or forwarding of this email or the content of this email is strictly = prohibited.