From: mayshao-oc <mayshao-oc@zhaoxin.com>
To: <libc-alpha@sourceware.org>
Cc: <hjl.tools@gmail.com>, <carlos@redhat.com>, <fw@deneb.enyo.de>,
<QiyuanWang@zhaoxin.com>, <HerryYang@zhaoxin.com>,
<RickyLi@zhaoxin.com>, mayshao <mayshao-oc@zhaoxin.com>
Subject: [PATCH v3 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors
Date: Fri, 24 Apr 2020 20:29:30 +0800 [thread overview]
Message-ID: <1587731372-9324-2-git-send-email-mayshao-oc@zhaoxin.com> (raw)
In-Reply-To: <1587731372-9324-1-git-send-email-mayshao-oc@zhaoxin.com>
From: mayshao <mayshao-oc@zhaoxin.com>
To recognize Zhaoxin CPU Vendor ID, add a new architecture type
arch_kind_zhaoxin for Vendor Zhaoxin detection.
---
sysdeps/x86/cpu-features.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++
sysdeps/x86/cpu-features.h | 1 +
2 files changed, 55 insertions(+)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 81a170a..bfb415f 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -466,6 +466,60 @@ init_cpu_features (struct cpu_features *cpu_features)
}
}
}
+ /* This spells out "CentaurHauls" or " Shanghai ". */
+ else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561)
+ || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61))
+ {
+ unsigned int extended_model, stepping;
+
+ kind = arch_kind_zhaoxin;
+
+ get_common_indices (cpu_features, &family, &model, &extended_model,
+ &stepping);
+
+ get_extended_indices (cpu_features);
+
+ model += extended_model;
+ if (family == 0x6)
+ {
+ if (model == 0xf || model == 0x19)
+ {
+ cpu_features->feature[index_arch_AVX_Usable]
+ &= (~bit_arch_AVX_Usable
+ & ~bit_arch_AVX2_Usable);
+
+ cpu_features->feature[index_arch_Slow_SSE4_2]
+ |= (bit_arch_Slow_SSE4_2);
+
+ cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+ &= ~bit_arch_AVX_Fast_Unaligned_Load;
+ }
+ }
+ else if (family == 0x7)
+ {
+ if (model == 0x1b)
+ {
+ cpu_features->feature[index_arch_AVX_Usable]
+ &= (~bit_arch_AVX_Usable
+ & ~bit_arch_AVX2_Usable);
+
+ cpu_features->feature[index_arch_Slow_SSE4_2]
+ |= bit_arch_Slow_SSE4_2;
+
+ cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+ &= ~bit_arch_AVX_Fast_Unaligned_Load;
+ }
+ else if (model == 0x3b)
+ {
+ cpu_features->feature[index_arch_AVX_Usable]
+ &= (~bit_arch_AVX_Usable
+ & ~bit_arch_AVX2_Usable);
+
+ cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+ &= ~bit_arch_AVX_Fast_Unaligned_Load;
+ }
+ }
+ }
else
{
kind = arch_kind_other;
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index aea83e6..f05d5ce 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -53,6 +53,7 @@ enum cpu_features_kind
arch_kind_unknown = 0,
arch_kind_intel,
arch_kind_amd,
+ arch_kind_zhaoxin,
arch_kind_other
};
--
2.7.4
next prev parent reply other threads:[~2020-04-24 12:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 12:29 [PATCH v3 0/3] x86: Add " mayshao-oc
2020-04-24 12:29 ` mayshao-oc [this message]
2020-04-24 12:53 ` [PATCH v3 1/3] x86: Add CPU Vendor ID detection " H.J. Lu
2020-04-24 12:29 ` [PATCH v3 2/3] x86: Add cache information " mayshao-oc
2020-04-24 12:53 ` H.J. Lu
2020-04-26 5:54 ` Mayshao-oc
2020-04-26 12:07 ` H.J. Lu
2020-04-30 5:09 ` Mayshao-oc
2020-04-30 5:15 ` H.J. Lu
2020-04-30 6:04 ` Mayshao-oc
2020-04-30 12:52 ` H.J. Lu
2020-04-30 13:22 ` Mayshao-oc
2020-04-30 13:55 ` H.J. Lu
2020-04-30 14:39 ` Mayshao-oc
2020-04-30 19:10 ` Joseph Myers
2020-04-30 19:16 ` Florian Weimer
2020-04-30 19:21 ` H.J. Lu
2020-04-30 20:04 ` Florian Weimer
2020-04-24 12:29 ` [PATCH v3 3/3] x86: Add the test case of __get_cpu_features " mayshao-oc
2020-04-24 12:54 ` H.J. Lu
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