From: Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>
To: Noah Goldstein <goldstein.w.n@gmail.com>
Cc: libc-alpha@sourceware.org, "H . J . Lu" <hjl.tools@gmail.com>,
Sajan Karumanchi <sajan.karumanchi@gmail.com>,
bmerry@sarao.ac.za, pmallapp@amd.com
Subject: Re: [PATCH v2 2/3] x86: Do not prefer ERMS for memset on Zen3+
Date: Wed, 7 Feb 2024 09:14:37 -0300 [thread overview]
Message-ID: <15a52132-bfc7-43c6-bea3-f5467c2a7a65@linaro.org> (raw)
In-Reply-To: <CAFUsyf+3GuDvFXnjECh9_paQ8opxPv+OHPmqp54KX=+t1BEiGg@mail.gmail.com>
On 06/02/24 16:01, Noah Goldstein wrote:
> On Tue, Feb 6, 2024 at 5:43 PM Adhemerval Zanella
> <adhemerval.zanella@linaro.org> wrote:
>>
>> For AMD Zen3+ architecture, the performance of the vectorized loop is
>> slightly better than ERMS.
>>
>> Checked on x86_64-linux-gnu on Zen3.
>> ---
>> sysdeps/x86/dl-cacheinfo.h | 16 +++++++++++-----
>> 1 file changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
>> index 74b804c5e6..f2cd6f179d 100644
>> --- a/sysdeps/x86/dl-cacheinfo.h
>> +++ b/sysdeps/x86/dl-cacheinfo.h
>> @@ -1010,11 +1010,17 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
>> if (tunable_size > minimum_rep_movsb_threshold)
>> rep_movsb_threshold = tunable_size;
>>
>> - /* NB: The default value of the x86_rep_stosb_threshold tunable is the
>> - same as the default value of __x86_rep_stosb_threshold and the
>> - minimum value is fixed. */
>> - rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold,
>> - long int, NULL);
>> + /* For AMD Zen3+ architecture, the performance of the vectorized loop is
>> + slightly better than ERMS. */
>> + if (cpu_features->basic.kind == arch_kind_amd)
>> + rep_stosb_threshold = SIZE_MAX;
>> +
>> + if (TUNABLE_IS_INITIALIZED (x86_rep_stosb_threshold))
>> + /* NB: The default value of the x86_rep_stosb_threshold tunable is the
>> + same as the default value of __x86_rep_stosb_threshold and the
>> + minimum value is fixed. */
>> + rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold,
>> + long int, NULL);
> Can we keep the unconditional
> rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold,
> long int, NULL);
> for targets other than AMD?
> Its easier to control the defaults that way.
Alright, I will change to
/* NB: The default value of the x86_rep_stosb_threshold tunable is the
same as the default value of __x86_rep_stosb_threshold and the
minimum value is fixed. */
rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold,
long int, NULL);
if (cpu_features->basic.kind == arch_kind_amd
&& !TUNABLE_IS_INITIALIZED (x86_rep_stosb_threshold))
/* For AMD Zen3+ architecture, the performance of the vectorized loop is
slightly better than ERMS. */
rep_stosb_threshold = SIZE_MAX;
next prev parent reply other threads:[~2024-02-07 12:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-06 17:43 [PATCH v2 0/3] x86: Improve ERMS usage " Adhemerval Zanella
2024-02-06 17:43 ` [PATCH v2 1/3] x86: Fix Zen3/Zen4 ERMS selection (BZ 30994) Adhemerval Zanella
2024-02-06 18:36 ` Noah Goldstein
2024-02-07 12:10 ` Adhemerval Zanella Netto
2024-02-07 17:39 ` Noah Goldstein
2024-02-07 18:06 ` Adhemerval Zanella Netto
2024-02-07 18:10 ` Adhemerval Zanella Netto
2024-02-07 22:07 ` Noah Goldstein
2024-02-09 10:59 ` Karumanchi, Sajan
2024-02-06 17:43 ` [PATCH v2 2/3] x86: Do not prefer ERMS for memset on Zen3+ Adhemerval Zanella
2024-02-06 19:01 ` Noah Goldstein
2024-02-07 12:14 ` Adhemerval Zanella Netto [this message]
2024-02-06 17:43 ` [PATCH v2 3/3] x86: Expand the comment on when REP STOSB is used on memset Adhemerval Zanella
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