From: Adhemerval Zanella <adhemerval.zanella@linaro.org>
To: libc-alpha@sourceware.org
Subject: Re: [PATCH] AArch64: Improve backwards memmove performance
Date: Tue, 25 Aug 2020 09:15:38 -0300 [thread overview]
Message-ID: <16d04393-df89-cfb2-a97c-91a44fa4888c@linaro.org> (raw)
In-Reply-To: <DB8PR08MB503633698FAA56D1D8E3AF35835A0@DB8PR08MB5036.eurprd08.prod.outlook.com>
On 20/08/2020 08:46, Wilco Dijkstra wrote:
> On some microarchitectures performance of the backwards memmove improves if
> the stores use STR with decreasing addresses. So change the memmove loop
> in memcpy_advsimd.S to use 2x STR rather than STP.
>
> Passes GLIBC regression test, OK for commit?
LGTM, thanks. Does it make any difference to use the same strategy on the
last iteration at L(copy64_from_start) as well?
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
>
> ---
> diff --git a/sysdeps/aarch64/multiarch/memcpy_advsimd.S b/sysdeps/aarch64/multiarch/memcpy_advsimd.S
> index d4ba74777744c8bb5a83e43ab2d63ad8dab35203..48bb6d7ca425197907eaef2307fb3939e69baa15 100644
> --- a/sysdeps/aarch64/multiarch/memcpy_advsimd.S
> +++ b/sysdeps/aarch64/multiarch/memcpy_advsimd.S
> @@ -223,12 +223,13 @@ L(copy_long_backwards):
> b.ls L(copy64_from_start)
>
> L(loop64_backwards):
> - stp A_q, B_q, [dstend, -32]
> + str B_q, [dstend, -16]
> + str A_q, [dstend, -32]
> ldp A_q, B_q, [srcend, -96]
> - stp C_q, D_q, [dstend, -64]
> + str D_q, [dstend, -48]
> + str C_q, [dstend, -64]!
> ldp C_q, D_q, [srcend, -128]
> sub srcend, srcend, 64
> - sub dstend, dstend, 64
> subs count, count, 64
> b.hi L(loop64_backwards)
>
>
prev parent reply other threads:[~2020-08-25 12:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-20 11:46 Wilco Dijkstra
2020-08-25 12:15 ` Adhemerval Zanella [this message]
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