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([2804:1b3:a7c1:e3c5:d5b:1509:7f55:16c2]) by smtp.gmail.com with ESMTPSA id t23-20020a656097000000b005fd08bcee06sm14978674pgu.2.2024.04.30.11.34.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Apr 2024 11:34:44 -0700 (PDT) Message-ID: <17f748c4-399e-4f8a-9a62-a9b86f7a0aae@linaro.org> Date: Tue, 30 Apr 2024 15:34:41 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] powerpc: Fix __fesetround_inline_nocheck on POWER9+ (BZ 31682) To: Paul E Murphy , libc-alpha@sourceware.org Cc: Manjunath S Matti , Peter Bergner References: <20240430124011.12408-1-adhemerval.zanella@linaro.org> Content-Language: en-US From: Adhemerval Zanella Netto Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 30/04/24 15:13, Paul E Murphy wrote: > > > On 4/30/24 7:40 AM, Adhemerval Zanella wrote: >> The e68b1151f7460d5fa88c3a567c13f66052da79a7 commit changed the >> __fesetround_inline_nocheck implementation to use mffscrni >> (through __fe_mffscrn) instead of mtfsfi.  For generic powerpc >> ceil/floor/trunc, the function is supposed to not change the >> Floating-Point Inexact Exception Enable bit, however mffscrni >> clear bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), different than mtfsfi. > > I don't think that explanation is correct. mffscrni should not alter the exception enable bits. It copies them into FRT, but does not clear them. Yeah, I forgot to add that mffscrni in this context clears because there is no easy way to mask out the current bits 56:63 since only the rounding bit is provided. So maybe: The e68b1151f7460d5fa88c3a567c13f66052da79a7 commit changed the __fesetround_inline_nocheck implementation to use mffscrni (through __fe_mffscrn) instead of mtfsfi. For generic powerpc ceil/floor/trunc, the function is supposed to not change the Floating-Point Inexact Exception Enable bit, however mffscrni usage always clear the the bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), since only the rounding mode is provided. > > From ISA 3.1 description of mffscrni: > > The contents of the control bits in the FPSCR, that is, > bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), > are placed into the corresponding bits in register FRT. All > other bits in register FRT are set to 0. > > The contents of bits 62:63 of the FPSCR (RN) are set to > the value of RM.