From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id 40F04385B50C for ; Mon, 13 Feb 2023 18:17:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 40F04385B50C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-pj1-x102c.google.com with SMTP id bx22so12732935pjb.3 for ; Mon, 13 Feb 2023 10:17:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=jg+1WF/VSrL1Hm2WLxIINZJkMKxKh4uCUNX6G7obnso=; b=AZSrX5svn3qKR6mUOzQywQfFmBramg43r5PgGxgENxxxbCrBRtxPYXuZYN4LRCDThj gc0vlDF37RwlM/Lw+JqnXY95cJvuICvmbCiaHYy14FSADOZhJ8NGP/MPNYYSqDrZN+pI k6sQ1eynXvsblDYAJaLFWMff2NslwFocSz6Sl+oyLPfh8WS580zI+EfbWsZ+leuIpN11 R+PFJANE8lCWZA1z5ES8ODJzhgyjIwxRUkESXPRHGMva8ICResG0CSa4RDg7clYTT7Cb ec+earJphfjXES3S6xhHfeu9wEdA0eWSJ3OLEPEEizv46WewLYO8S0VELBI++vaJojye SSjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jg+1WF/VSrL1Hm2WLxIINZJkMKxKh4uCUNX6G7obnso=; b=EfNhq2SH3I/wHeuHCrChoOadQ+4IHs2koygBBfdJ6aYs0UHT3Jx2lCeVoqq/0n5m07 HCe5KaK/E08vJntdrDosO4aE7tptqKgtj4Yt1Lnp4Xz3jAFUOBiKhYSszk1NM/RjJJe1 u7Ms6AMhp12dtrEuxhjsnscJgn9r5pPov1YudUjc/lZIENslC8ByiEkGj8ek0FPVo1Fj pESe1bQwUDrzOO6zBc9SHHQu67yp0XirRYJbuisrETK2MTIKksWIysU0hrQADTFteDIR 4GEm7OcYc2QtqaO98gMEaLX9jSCTrNOebq6z8HOFjP6Xt5oJPqYMf8KKes/cd/GB1yur ZjFA== X-Gm-Message-State: AO0yUKWz3+O3WZwxu/pWpNWupM8qNfURbmQzCRh0xXpsjDyMmsEj0qAN p43/FzS2FtQ06MQaTbHgZ2NCa4QC32h2zo1HWO4= X-Google-Smtp-Source: AK7set9A8UD4WWmxg4aAeQK+IRt1ftgOYxFCDPPB1Eqjs+Ks9/fnpwvKgtppyrqT5Q4mNK3dDK3CWw== X-Received: by 2002:a17:902:ecc2:b0:19a:968d:2713 with SMTP id a2-20020a170902ecc200b0019a968d2713mr6631320plh.48.1676312237633; Mon, 13 Feb 2023 10:17:17 -0800 (PST) Received: from [192.168.145.227] (rrcs-74-87-59-234.west.biz.rr.com. [74.87.59.234]) by smtp.gmail.com with ESMTPSA id p14-20020a170902c58e00b00198e6257921sm3859314plx.269.2023.02.13.10.17.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Feb 2023 10:17:17 -0800 (PST) Message-ID: <191630a8-913e-74bd-2052-8199290ee0df@linaro.org> Date: Mon, 13 Feb 2023 08:17:13 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v2] riscv: Add macros for FPUCW/fcsr in fpu_control.h Content-Language: en-US To: Shiqi Zhang , libc-alpha@sourceware.org Cc: schwab@linux-m68k.org References: <20230212065214.2399-1-shiqi@isrc.iscas.ac.cn> <68996dd3-9fbe-b6ed-0642-0e1c860c3c78@isrc.iscas.ac.cn> From: Richard Henderson In-Reply-To: <68996dd3-9fbe-b6ed-0642-0e1c860c3c78@isrc.iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2/12/23 20:16, Shiqi Zhang wrote: > >> Honestly, no one should be using at all.  It was >> originally an x86 specific thing.  The only reason to fill in this >> header at all is to match the original x86 API.  Therefore the symbol >> names should match ./sysdeps/x86/fpu_control.h. > > > Actually other architectures also defines these arch-specific macros in > ./sysdeps/***/fpu_control.h. And the symbol names doesn't match x86, > too. For example I checked the macro _FPU_FPCR_MASK_OFE in > ./sysdeps/aarch64/fpu/fpu_control.h, nothing in glibc referenced it so I > think it can only be for the users to control FPU in an arch-specific > manner. Oh the other hand, note the number of targets that use _FPU_RC_NEAREST, _FPU_RC_DOWN, _FPU_RC_UP, _FPU_RC_ZERO x86, alpha, csky, loongarch, m68k, mips, ppc, sparc, sh (nearest, zero). Indeed, arm and aarch64 seem to be the outliers in being completely different. r~