From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from black.elm.relay.mailchannels.net (black.elm.relay.mailchannels.net [23.83.212.19]) by sourceware.org (Postfix) with ESMTPS id A9B69388A40A for ; Wed, 25 Nov 2020 15:34:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org A9B69388A40A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=gotplt.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=siddhesh@gotplt.org X-Sender-Id: dreamhost|x-authsender|siddhesh@gotplt.org Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id DF1F040205A; Wed, 25 Nov 2020 15:34:39 +0000 (UTC) Received: from pdx1-sub0-mail-a90.g.dreamhost.com (100-96-12-120.trex.outbound.svc.cluster.local [100.96.12.120]) (Authenticated sender: dreamhost) by relay.mailchannels.net (Postfix) with ESMTPA id 5472C401EF0; Wed, 25 Nov 2020 15:34:38 +0000 (UTC) X-Sender-Id: dreamhost|x-authsender|siddhesh@gotplt.org Received: from pdx1-sub0-mail-a90.g.dreamhost.com (pop.dreamhost.com [64.90.62.162]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.18.10); Wed, 25 Nov 2020 15:34:39 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: dreamhost|x-authsender|siddhesh@gotplt.org X-MailChannels-Auth-Id: dreamhost X-Chief-Hysterical: 7d88b3b8309870c1_1606318478755_4268905570 X-MC-Loop-Signature: 1606318478751:2204928724 X-MC-Ingress-Time: 1606318478750 Received: from pdx1-sub0-mail-a90.g.dreamhost.com (localhost [127.0.0.1]) by pdx1-sub0-mail-a90.g.dreamhost.com (Postfix) with ESMTP id 856837F5E1; Wed, 25 Nov 2020 07:34:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gotplt.org; h=subject:to :references:from:message-id:date:mime-version:in-reply-to :content-type:content-transfer-encoding; s=gotplt.org; bh=+Gy1tz Y7n+jRULfjZY7ricDMZ+k=; b=uwjvNUsL5hG+fdhJHLWdqUVVZ7Z+FWc9Bo0V/5 h03lmXS5MShviVcQleEHoGreRwzElWuPv6eaEYjGVKcNOMIFfyS8Bn/W/zeh2atx cX/SbWrvLpM13XzYBQ1C5QZ3dXqPNoSz3z3+Bm7t7dvRG5TZdEWlelmjkve2eI4r 2HlXE= Received: from [192.168.1.111] (unknown [1.186.101.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: siddhesh@gotplt.org) by pdx1-sub0-mail-a90.g.dreamhost.com (Postfix) with ESMTPSA id 3EB2F7F25D; Wed, 25 Nov 2020 07:34:35 -0800 (PST) Subject: Re: [PATCH v3 7/8] aarch64: Add sysv specific enabling code for memory tagging To: Richard Earnshaw , libc-alpha@sourceware.org References: <20201123154236.25809-1-rearnsha@arm.com> <20201123154236.25809-8-rearnsha@arm.com> X-DH-BACKEND: pdx1-sub0-mail-a90 From: Siddhesh Poyarekar Message-ID: <1b6cd0c1-e9d2-820d-325b-40b65d65d870@gotplt.org> Date: Wed, 25 Nov 2020 21:04:30 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201123154236.25809-8-rearnsha@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Nov 2020 15:34:44 -0000 On 11/23/20 9:12 PM, Richard Earnshaw via Libc-alpha wrote: > > Add various defines and stubs for enabling MTE on AArch64 sysv-like > systems such as Linux. The HWCAP feature bit is copied over in the > same way as other feature bits. Similarly we add a new wrapper header > for mman.h to define the PROT_MTE flag that can be used with mmap and > related functions. > > We add a new field to struct cpu_features that can be used, for > example, to check whether or not certain ifunc'd routines should be > bound to MTE-safe versions. > > Finally, if we detect that MTE should be enabled (ie via the glibc > tunable); we enable MTE during startup as required. > --- > sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 1 + > sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 7 +++++ > .../unix/sysv/linux/aarch64/cpu-features.c | 28 +++++++++++++++++++ > .../unix/sysv/linux/aarch64/cpu-features.h | 1 + > 4 files changed, 37 insertions(+) > > diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h > index af90d8a626..389852f1d9 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h > +++ b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h > @@ -73,3 +73,4 @@ > #define HWCAP2_DGH (1 << 15) > #define HWCAP2_RNG (1 << 16) > #define HWCAP2_BTI (1 << 17) > +#define HWCAP2_MTE (1 << 18) > diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h > index ecae046344..3658b958b5 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h > +++ b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h > @@ -1,4 +1,5 @@ > /* Definitions for POSIX memory map interface. Linux/AArch64 version. > + Unnecessary newline. I spotted a couple in 3/8 as well. > Copyright (C) 2020 Free Software Foundation, Inc. > This file is part of the GNU C Library. > > @@ -25,6 +26,12 @@ > > #define PROT_BTI 0x10 > > +/* The following definitions basically come from the kernel headers. > + But the kernel header is not namespace clean. */ > + > +/* Other flags. */ > +#define PROT_MTE 0x20 /* Normal Tagged mapping. */ > + > #include > > /* Include generic Linux declarations. */ > diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > index b9ab827aca..aa4a82c6e8 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > > #define DCZID_DZP_MASK (1 << 4) > #define DCZID_BS_MASK (0xf) > @@ -86,4 +87,31 @@ init_cpu_features (struct cpu_features *cpu_features) > > /* Check if BTI is supported. */ > cpu_features->bti = GLRO (dl_hwcap2) & HWCAP2_BTI; > + > + /* Setup memory tagging support if the HW and kernel support it, and if > + the user has requested it. */ > + cpu_features->mte_state = 0; > + > +#ifdef _LIBC_MTAG > +# if HAVE_TUNABLES > + int mte_state = TUNABLE_GET (glibc, memtag, enable, unsigned, 0); > + cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0; > + /* If we lack the MTE feature, disable the tunable, since it will > + otherwise cause instructions that won't run on this CPU to be used. */ > + TUNABLE_SET (glibc, memtag, enable, unsigned, cpu_features->mte_state); > +# endif > + > + /* For now, disallow tag 0, so that we can clearly see when tagged > + addresses are being allocated. */ > + if (cpu_features->mte_state & 2) > + __prctl (PR_SET_TAGGED_ADDR_CTRL, > + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC > + | (0xfffe << PR_MTE_TAG_SHIFT)), Couldn't this magic number also become a macro too? > + 0, 0, 0); > + else if (cpu_features->mte_state) > + __prctl (PR_SET_TAGGED_ADDR_CTRL, > + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC > + | (0xfffe << PR_MTE_TAG_SHIFT)), Likewise. > + 0, 0, 0); > +#endif > } > diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h > index 00a4d0c8e7..838d5c9aba 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h > +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h > @@ -70,6 +70,7 @@ struct cpu_features > uint64_t midr_el1; > unsigned zva_size; > bool bti; > + unsigned mte_state; This could be just a byte unless you foresee expanding the MTE flags beyond the 8 bits you've specified in the tunables. > }; > > #endif /* _CPU_FEATURES_AARCH64_H */