From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 59621 invoked by alias); 7 Nov 2016 21:21:07 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 59605 invoked by uid 89); 7 Nov 2016 21:21:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_NONE autolearn=no version=3.3.2 spammy=Sam, firstly, playing, HTo:U*davem X-HELO: asavdk4.altibox.net Date: Mon, 07 Nov 2016 21:21:00 -0000 From: Sam Ravnborg To: David Miller Cc: carlos@redhat.com, triegel@redhat.com, adhemerval.zanella@linaro.org, andreas@gaisler.com, libc-alpha@sourceware.org, software@gaisler.com Subject: Re: Remove sparcv8 support Message-ID: <20161107212050.GA27481@ravnborg.org> References: <20161026.144741.1659367414224835783.davem@davemloft.net> <1477565575.7146.199.camel@localhost.localdomain> <502720f6-3057-41f5-7832-4b219f5f729f@redhat.com> <20161107.113825.631166023186879199.davem@davemloft.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161107.113825.631166023186879199.davem@davemloft.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-CMAE-Score: 0 X-CMAE-Analysis: v=2.2 cv=eqGd9chX c=1 sm=1 tr=0 a=Ij76tQDYWdb01v2+RnYW5w==:117 a=Ij76tQDYWdb01v2+RnYW5w==:17 a=kj9zAlcOel0A:10 a=J1Y8HTJGAAAA:8 a=Dk9V0s3UyH1J1Avdk_YA:9 a=CjuIK1q_8ugA:10 a=y1Q9-5lHfBjTkpIzbSAN:22 X-SW-Source: 2016-11/txt/msg00253.txt.bz2 On Mon, Nov 07, 2016 at 11:38:25AM -0500, David Miller wrote: > > So the following attached is what I started playing around with this > weekend. > > It implements software trap "0x23" to perform a CAS operations, the > operands are expected in registers %o0, %o1, and %o2. > > Since it was easiest to test I implemented this first on sparc64 which > just executes the CAS instruction directly. I'll start working on the > 32-bit part in the background. > > The capability will be advertised via the mask returned by the "get > kernel features" system call. We could check this early in the > crt'ish code and cache the value in a variable which the atomics can > check. > > Another kernel side change I have to do is advertise the LEON CAS > availability in the _dl_hwcaps so that we can use the LEON CAS in > glibc when available. > > The first patch is the kernel side, and the second is the glibc side. > The whole NPTL testsuite passes for the plain 32-bit sparc target with > these changes. Glad that you found some time to look into this! > >From fa1cad39df7318cdb46baea5774c340322cd74f2 Mon Sep 17 00:00:00 2001 > From: "David S. Miller" > Date: Mon, 7 Nov 2016 08:27:05 -0800 > Subject: [PATCH] sparc64: Add CAS emulation trap. > > Older 32-bit sparc cpus (other than LEON) lack a CAS instruction, so > we need to provide some kind of helper infrastructure in the kernel > to emulate it. > > This is the first part which firstly defines the basic infrastructure > and the simplest implementation, which is to just directly execute the > instruction on sparc64. > > We make use of the window fill/spill fault unwind facilities to make > this as simple as possible. When we take a full TSB miss, we check if > the trap level is greater than one, and if so unwind the trap to one > of the final 3 instructions of the interrupted trap handler's block. > Which of the three to use is based upon whether this is a real fault, > an unaligned access, or a data access exception (ie. bus error). > > Signed-off-by: David S. Miller > --- > arch/sparc/include/uapi/asm/unistd.h | 1 + > arch/sparc/kernel/Makefile | 1 + > arch/sparc/kernel/sys_sparc_64.c | 2 +- > arch/sparc/kernel/ttable_64.S | 3 ++- > 4 files changed, 5 insertions(+), 2 deletions(-) casemul.S is missing. So all the fun kernel stuf was not included in the patch... Sam