From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 130926 invoked by alias); 22 Aug 2017 11:17:15 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 130901 invoked by uid 89); 22 Aug 2017 11:17:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=terminology X-Spam-User: qpsmtpd, 2 recipients X-HELO: foss.arm.com Date: Tue, 22 Aug 2017 11:17:00 -0000 From: Dave Martin To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel , Szabolcs Nagy , gdb@sourceware.org, Yao Qi , Alan Hayward , Will Deacon , Richard Sandiford , Catalin Marinas , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition Message-ID: <20170822111705.GT6321@e103592.cambridge.arm.com> References: <1502280338-23002-1-git-send-email-Dave.Martin@arm.com> <1502280338-23002-10-git-send-email-Dave.Martin@arm.com> <87y3qb52ez.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87y3qb52ez.fsf@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-SW-Source: 2017-08/txt/msg01043.txt.bz2 On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > This patch defines the representation that will be used for the SVE > > register state in the signal frame, and implements support for > > saving and restoring the SVE registers around signals. > > > > The same layout will also be used for the in-kernel task state. > > > > Due to the variability of the SVE vector length, it is not possible > > to define a fixed C struct to describe all the registers. Instead, > > Macros are defined in sigcontext.h to facilitate access to the > > parts of the structure. > > > > Signed-off-by: Dave Martin > > --- > > arch/arm64/include/uapi/asm/sigcontext.h | 113 ++++++++++++++++++++++++++++++- > > 1 file changed, 112 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h > > index f0a76b9..0533bdf 100644 > > --- a/arch/arm64/include/uapi/asm/sigcontext.h > > +++ b/arch/arm64/include/uapi/asm/sigcontext.h > > @@ -16,6 +16,8 @@ > > #ifndef _UAPI__ASM_SIGCONTEXT_H > > #define _UAPI__ASM_SIGCONTEXT_H > > > > +#ifndef __ASSEMBLY__ > > + > > #include > > > > /* > > @@ -41,10 +43,11 @@ struct sigcontext { > > * > > * 0x210 fpsimd_context > > * 0x10 esr_context > > + * 0x8a0 sve_context (vl <= 64) (optional) > > * 0x20 extra_context (optional) > > * 0x10 terminator (null _aarch64_ctx) > > * > > - * 0xdb0 (reserved for future allocation) > > + * 0x510 (reserved for future allocation) > > * > > * New records that can exceed this space need to be opt-in for userspace, so > > * that an expanded signal frame is not generated unexpectedly. The mechanism > > @@ -116,4 +119,112 @@ struct extra_context { > > __u32 __reserved[3]; > > }; > > > > +#define SVE_MAGIC 0x53564501 > > + > > +struct sve_context { > > + struct _aarch64_ctx head; > > + __u16 vl; > > + __u16 __reserved[3]; > > +}; > > + > > +#endif /* !__ASSEMBLY__ */ > > + > > +/* > > + * The SVE architecture leaves space for future expansion of the > > + * vector length beyond its initial architectural limit of 2048 bits > > + * (16 quadwords). > > + */ > > +#define SVE_VQ_MIN 1 > > +#define SVE_VQ_MAX 0x200 > > + > > +#define SVE_VL_MIN (SVE_VQ_MIN * 0x10) > > +#define SVE_VL_MAX (SVE_VQ_MAX * 0x10) > > + > > +#define SVE_NUM_ZREGS 32 > > +#define SVE_NUM_PREGS 16 > > + > > +#define sve_vl_valid(vl) \ > > + ((vl) % 0x10 == 0 && (vl) >= SVE_VL_MIN && (vl) <= SVE_VL_MAX) > > +#define sve_vq_from_vl(vl) ((vl) / 0x10) > > +#define sve_vl_from_vq(vq) ((vq) * 0x10) > > I got a little confused first time through over what VQ and VL where. > Maybe it would make sense to expand a little more from first principles? > > /* > * The SVE architecture defines vector registers as a multiple of 128 > * bit quadwords. The current architectural limit is 2048 bits (16 > * quadwords) but there is room for future expansion beyond that. > */ This comes up in several places and so I didn't want to comment it repeatedly everywhere. Instead, I wrote up something in section 2 (Vector length terminology) of Documentation/arm64/sve.txt -- see patch 25. Can you take a look and see whether that's adequate? [...] Cheers ---Dave