From: Palmer Dabbelt <palmer@dabbelt.com>
To: libc-alpha@sourceware.org
Cc: Andrew Waterman <andrew@sifive.com>,
Darius Rad <darius@bluespec.com>,
dj@redhat.com, Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v2 06/15] RISC-V: Generic <math.h> and soft-fp Routines
Date: Wed, 20 Dec 2017 07:24:00 -0000 [thread overview]
Message-ID: <20171220072022.26909-7-palmer@dabbelt.com> (raw)
In-Reply-To: <20171220072022.26909-1-palmer@dabbelt.com>
This patch contains the miscellaneous math routines and headers we have
implemented for RISC-V. This includes things from <math.h> that aren't
completely ISA-generic, floating-point bit manipulation, and soft-fp
hooks.
---
sysdeps/riscv/bits/fenv.h | 74 +++++++++++++++++++++++++++++
sysdeps/riscv/fpu_control.h | 74 +++++++++++++++++++++++++++++
sysdeps/riscv/sfp-machine.h | 112 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 260 insertions(+)
create mode 100644 sysdeps/riscv/bits/fenv.h
create mode 100644 sysdeps/riscv/fpu_control.h
create mode 100644 sysdeps/riscv/sfp-machine.h
diff --git a/sysdeps/riscv/bits/fenv.h b/sysdeps/riscv/bits/fenv.h
new file mode 100644
index 000000000000..13569f6d2ca6
--- /dev/null
+++ b/sysdeps/riscv/bits/fenv.h
@@ -0,0 +1,74 @@
+/* Floating point environment, RISC-V version.
+ Copyright (C) 1998-2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _FENV_H
+# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
+#endif
+
+enum
+ {
+ FE_INEXACT =
+#define FE_INEXACT (0x01)
+ FE_INEXACT,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW (0x02)
+ FE_UNDERFLOW,
+ FE_OVERFLOW =
+#define FE_OVERFLOW (0x04)
+ FE_OVERFLOW,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO (0x08)
+ FE_DIVBYZERO,
+ FE_INVALID =
+#define FE_INVALID (0x10)
+ FE_INVALID,
+ };
+
+#define FE_ALL_EXCEPT \
+ (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
+
+enum
+ {
+ FE_TONEAREST =
+#define FE_TONEAREST (0x0)
+ FE_TONEAREST,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO (0x1)
+ FE_TOWARDZERO,
+ FE_DOWNWARD =
+#define FE_DOWNWARD (0x2)
+ FE_DOWNWARD,
+ FE_UPWARD =
+#define FE_UPWARD (0x3)
+ FE_UPWARD,
+ };
+
+
+typedef unsigned int fexcept_t;
+typedef unsigned int fenv_t;
+
+/* If the default argument is used we use this value. */
+#define FE_DFL_ENV ((__const fenv_t *) -1)
+
+#if __GLIBC_USE (IEC_60559_BFP_EXT)
+/* Type representing floating-point control modes. */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes. */
+# define FE_DFL_MODE ((const femode_t *) -1L)
+#endif
diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h
new file mode 100644
index 000000000000..f2c59845f8f7
--- /dev/null
+++ b/sysdeps/riscv/fpu_control.h
@@ -0,0 +1,74 @@
+/* FPU control word bits. RISC-V version.
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _FPU_CONTROL_H
+#define _FPU_CONTROL_H
+
+#include <features.h>
+
+#ifndef __riscv_flen
+
+#define _FPU_RESERVED 0xffffffff
+#define _FPU_DEFAULT 0x00000000
+typedef unsigned int fpu_control_t;
+#define _FPU_GETCW(cw) (cw) = 0
+#define _FPU_SETCW(cw) do { } while (0)
+extern fpu_control_t __fpu_control;
+
+#else /* __riscv_flen */
+
+#define _FPU_RESERVED 0
+#define _FPU_DEFAULT 0
+#define _FPU_IEEE _FPU_DEFAULT
+
+/* Type of the control word. */
+typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
+
+/* Macros for accessing the hardware control word. */
+#define _FPU_GETCW(cw) __asm__ volatile ("frsr %0" : "=r" (cw))
+#define _FPU_SETCW(cw) __asm__ volatile ("fssr %z0" : : "rJ" (cw))
+
+/* Default control word set at startup. */
+extern fpu_control_t __fpu_control;
+
+#define _FCLASS(x) ({ int res; \
+ if (sizeof (x) * 8 > __riscv_flen) __builtin_trap (); \
+ if (sizeof (x) == 4) asm ("fclass.s %0, %1" : "=r" (res) : "f" (x)); \
+ else if (sizeof (x) == 8) asm ("fclass.d %0, %1" : "=r" (res) : "f" (x)); \
+ else __builtin_trap (); \
+ res; })
+
+#define _FCLASS_MINF (1<<0)
+#define _FCLASS_MNORM (1<<1)
+#define _FCLASS_MSUBNORM (1<<2)
+#define _FCLASS_MZERO (1<<3)
+#define _FCLASS_PZERO (1<<4)
+#define _FCLASS_PSUBNORM (1<<5)
+#define _FCLASS_PNORM (1<<6)
+#define _FCLASS_PINF (1<<7)
+#define _FCLASS_SNAN (1<<8)
+#define _FCLASS_QNAN (1<<9)
+#define _FCLASS_ZERO (_FCLASS_MZERO | _FCLASS_PZERO)
+#define _FCLASS_SUBNORM (_FCLASS_MSUBNORM | _FCLASS_PSUBNORM)
+#define _FCLASS_NORM (_FCLASS_MNORM | _FCLASS_PNORM)
+#define _FCLASS_INF (_FCLASS_MINF | _FCLASS_PINF)
+#define _FCLASS_NAN (_FCLASS_SNAN | _FCLASS_QNAN)
+
+#endif /* __riscv_flen */
+
+#endif /* fpu_control.h */
diff --git a/sysdeps/riscv/sfp-machine.h b/sysdeps/riscv/sfp-machine.h
new file mode 100644
index 000000000000..55949e58b349
--- /dev/null
+++ b/sysdeps/riscv/sfp-machine.h
@@ -0,0 +1,112 @@
+/* RISC-V softfloat definitions
+ Copyright (C) 2017 Free Software Foundation, Inc.
+
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <fenv.h>
+#include <fpu_control.h>
+
+#if __riscv_xlen == 32
+
+#define _FP_W_TYPE_SIZE 32
+#define _FP_W_TYPE unsigned long
+#define _FP_WS_TYPE signed long
+#define _FP_I_TYPE long
+
+#define _FP_MUL_MEAT_S(R,X,Y) \
+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y) \
+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S _FP_QNANBIT_S
+#define _FP_NANFRAC_D _FP_QNANBIT_D, 0
+#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
+
+#else
+
+#define _FP_W_TYPE_SIZE 64
+#define _FP_W_TYPE unsigned long long
+#define _FP_WS_TYPE signed long long
+#define _FP_I_TYPE long long
+
+#define _FP_MUL_MEAT_S(R,X,Y) \
+ _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
+#define _FP_MUL_MEAT_D(R,X,Y) \
+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S _FP_QNANBIT_S
+#define _FP_NANFRAC_D _FP_QNANBIT_D
+#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0
+
+#endif
+
+#define _FP_NANSIGN_S 0
+#define _FP_NANSIGN_D 0
+#define _FP_NANSIGN_Q 0
+
+#define _FP_KEEPNANFRACP 0
+#define _FP_QNANNEGATEDP 0
+
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
+ do { \
+ R##_s = _FP_NANSIGN_##fs; \
+ _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \
+ R##_c = FP_CLS_NAN; \
+ } while (0)
+
+#define _FP_DECL_EX int _frm __attribute__ ((unused));
+#define FP_ROUNDMODE _frm
+
+#define FP_RND_NEAREST FE_TONEAREST
+#define FP_RND_ZERO FE_TOWARDZERO
+#define FP_RND_PINF FE_UPWARD
+#define FP_RND_MINF FE_DOWNWARD
+
+#define FP_EX_INVALID FE_INVALID
+#define FP_EX_OVERFLOW FE_OVERFLOW
+#define FP_EX_UNDERFLOW FE_UNDERFLOW
+#define FP_EX_DIVZERO FE_DIVBYZERO
+#define FP_EX_INEXACT FE_INEXACT
+
+#define _FP_TININESS_AFTER_ROUNDING 1
+
+#ifdef __riscv_flen
+#define FP_INIT_ROUNDMODE \
+do { \
+ __asm__ volatile ("frrm %0" : "=r" (_frm)); \
+} while (0)
+
+#define FP_HANDLE_EXCEPTIONS \
+do { \
+ if (__builtin_expect (_fex, 0)) \
+ __asm__ volatile ("csrs fflags, %0" : : "rK" (_fex)); \
+} while (0)
+#else
+#define FP_INIT_ROUNDMODE _frm = FP_RND_NEAREST
+#endif
--
2.13.6
next prev parent reply other threads:[~2017-12-20 7:23 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-20 7:23 RISC-V glibc port v2 Palmer Dabbelt
2017-12-20 7:23 ` [PATCH v2 05/15] RISC-V: Generic <string.h> Routines Palmer Dabbelt
2017-12-20 16:48 ` Joseph Myers
2017-12-23 22:01 ` Palmer Dabbelt
2018-01-01 0:52 ` Joseph Myers
2018-01-03 15:46 ` Adhemerval Zanella
2018-01-03 16:03 ` Joseph Myers
2018-01-03 16:08 ` Adhemerval Zanella
2017-12-20 7:23 ` [PATCH v2 03/15] RISC-V: Startup and Dynamic Loading Code Palmer Dabbelt
2017-12-20 16:38 ` Joseph Myers
2017-12-23 3:25 ` Palmer Dabbelt
2017-12-23 3:33 ` DJ Delorie
2017-12-23 12:52 ` Joseph Myers
2017-12-20 7:23 ` [PATCH v2 04/15] RISC-V: Thread-Local Storage Support Palmer Dabbelt
2017-12-20 16:45 ` Joseph Myers
2017-12-23 19:10 ` Palmer Dabbelt
2017-12-20 7:23 ` [PATCH v2 02/15] RISC-V: ABI Implementation Palmer Dabbelt
2017-12-20 16:31 ` Joseph Myers
2017-12-23 3:25 ` Palmer Dabbelt
2017-12-23 3:30 ` DJ Delorie
2017-12-20 7:23 ` [PATCH v2 01/15] RISC-V: Build Infastructure Palmer Dabbelt
2017-12-20 14:05 ` Dmitry V. Levin
2017-12-20 20:25 ` Palmer Dabbelt
2017-12-20 16:22 ` Joseph Myers
2017-12-20 16:49 ` Adhemerval Zanella
2017-12-23 2:22 ` Palmer Dabbelt
2017-12-23 12:44 ` Joseph Myers
2017-12-25 20:58 ` Palmer Dabbelt
2018-01-01 1:21 ` Joseph Myers
2017-12-20 16:43 ` Joseph Myers
2017-12-23 3:41 ` Palmer Dabbelt
2017-12-23 12:53 ` Joseph Myers
2017-12-20 7:24 ` [PATCH v2 11/15] RISC-V: Linux ABI Palmer Dabbelt
2017-12-20 17:33 ` Joseph Myers
2017-12-25 19:47 ` Palmer Dabbelt
2018-01-01 1:04 ` Joseph Myers
2018-01-02 20:59 ` Joseph Myers
2017-12-20 7:24 ` Palmer Dabbelt [this message]
2017-12-20 16:50 ` [PATCH v2 06/15] RISC-V: Generic <math.h> and soft-fp Routines Joseph Myers
2017-12-24 0:24 ` Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 08/15] RISC-V: RV32D, RV64F, and RV64D Support Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 09/15] RISC-V: Atomic and Locking Routines Palmer Dabbelt
2017-12-20 17:08 ` Joseph Myers
2017-12-24 1:26 ` Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 13/15] Add RISC-V dynamic relocations to elf.h Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 14/15] Add linux-4.15 VDSO hash for RISC-V Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 07/15] RISC-V: RV32F Support Palmer Dabbelt
2017-12-20 17:01 ` Joseph Myers
2017-12-20 17:04 ` Joseph Myers
2017-12-24 1:26 ` Palmer Dabbelt
2017-12-24 0:37 ` Palmer Dabbelt
2018-01-01 0:57 ` Joseph Myers
2017-12-20 7:24 ` [PATCH v2 10/15] RISC-V: Linux Syscall Interface Palmer Dabbelt
2017-12-20 16:57 ` Adhemerval Zanella
2017-12-24 0:24 ` Palmer Dabbelt
2018-01-01 0:56 ` Joseph Myers
2018-01-03 13:43 ` Christoph Hellwig
2018-01-03 15:56 ` Adhemerval Zanella
2018-01-09 1:30 ` Palmer Dabbelt
2018-01-09 11:16 ` Adhemerval Zanella
2017-12-20 17:24 ` Joseph Myers
2017-12-25 19:47 ` Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 12/15] RISC-V: Linux Startup and Dynamic Loading Code Palmer Dabbelt
2017-12-20 7:24 ` [PATCH v2 15/15] Add RISC-V to build-many-glibcs.py Palmer Dabbelt
2017-12-20 16:04 ` RISC-V glibc port v2 Joseph Myers
2017-12-20 20:25 ` Palmer Dabbelt
2017-12-20 20:42 ` Joseph Myers
2017-12-20 17:40 ` Joseph Myers
2017-12-25 20:20 ` Palmer Dabbelt
2018-01-01 1:20 ` Joseph Myers
2018-01-03 13:37 ` Christoph Hellwig
2018-01-03 13:42 ` Joseph Myers
2017-12-20 21:11 ` Joseph Myers
2017-12-20 21:45 ` Palmer Dabbelt
2017-12-25 12:57 ` Adhemerval Zanella
2018-01-01 0:58 ` Joseph Myers
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