From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 90029 invoked by alias); 3 Jan 2018 13:37:19 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 89234 invoked by uid 89); 3 Jan 2018 13:37:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy= X-HELO: newverein.lst.de Date: Wed, 03 Jan 2018 13:37:00 -0000 From: Christoph Hellwig To: Joseph Myers Cc: Palmer Dabbelt , libc-alpha@sourceware.org, Andrew Waterman , Darius Rad , dj@redhat.com Subject: Re: RISC-V glibc port v2 Message-ID: <20180103133714.GA14077@lst.de> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) X-SW-Source: 2018-01/txt/msg00097.txt.bz2 On Mon, Jan 01, 2018 at 01:19:48AM +0000, Joseph Myers wrote: > Do I understand correctly from this that RV64I processors cannot execute > RV32I code (unlike e.g. x86_64 where execution of 32-bit code is always > supported by the processor, or AArch64 where processors may or may not > support execution of AArch32 code)? If so, then indeed > bits/environments.h is not relevant at present. RV64I processors might be able to execute RV32I code (that support is optional in the architecture by writing to the sstatus register). But the Linux port currently does not support that (yet).