From: Palmer Dabbelt <palmer@dabbelt.com>
To: libc-alpha@sourceware.org, joseph@codesourcery.com
Cc: patches@groups.riscv.org, Andrew Waterman <andrew@sifive.com>,
dj@redhat.com, Darius Rad <darius@bluespec.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v6 04/16] Add documentation for __riscv_flush_icache
Date: Fri, 26 Jan 2018 05:45:00 -0000 [thread overview]
Message-ID: <20180126054443.22702-5-palmer@dabbelt.com> (raw)
In-Reply-To: <20180126054443.22702-1-palmer@dabbelt.com>
This function is used by GCC to enforce ordering between data writes and
instruction fetches, and while we'd prefer that users rely on the GCC
intrinsic when possible this is user visible in case that's not
possible.
2018-01-13 Palmer Dabbelt <palmer@sifive.com>
* manual/platform.texi: Add RISC-V documenation for
__riscv_flush_icache.
---
manual/platform.texi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/manual/platform.texi b/manual/platform.texi
index cb166641fb71..b8721a071272 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -6,6 +6,7 @@
@menu
* PowerPC:: Facilities Specific to the PowerPC Architecture
+* RISC-V:: Facilities Specific to the RISC-V Architecture
@end menu
@node PowerPC
@@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time
interval expires or if an attempt is made to set the priority to medium high
when it is not allowed, the priority is set to medium.
@end deftypefun
+
+@node RISC-V
+@appendixsec RISC-V-specific Facilities
+
+Cache management facilities specific to RISC-V systems that implement the Linux
+ABI are declared in @file{sys/cachectl.h}.
+
+@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags})
+@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
+Enforce ordering between stores and instruction cache fetches. The range of
+addresses over which ordering is enforced is specified by @var{start} and
+@var{end}. The @var{flags} argument controls the extent of this ordering, with
+the default behavior (a @var{flags} value of 0) being to enforce the fence on
+all threads in the current process. Setting the
+@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
+ordering on only the current thread is necessary. All other flag bits are
+reserved.
+@end deftypefun
--
2.13.6
next prev parent reply other threads:[~2018-01-26 5:45 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-26 5:44 RISC-V glibc port, v6 Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 08/16] RISC-V: Generic <math.h> and soft-fp Routines Palmer Dabbelt
2018-01-26 13:10 ` Joseph Myers
2018-01-26 18:03 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 14/16] RISC-V: Add ABI Lists Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 09/16] RISC-V: Hard Float Support Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 07/16] RISC-V: Thread-Local Storage Support Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 13/16] RISC-V: Linux Startup and Dynamic Loading Code Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 01/16] sysdeps/init_array: Add PREINIT_FUNCTION to crti.S Palmer Dabbelt
2018-01-26 12:56 ` Joseph Myers
2018-01-26 17:54 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 10/16] RISC-V: Atomic and Locking Routines Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 12/16] RISC-V: Linux ABI Palmer Dabbelt
2018-01-26 13:12 ` Joseph Myers
2018-01-26 18:05 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 16/16] Add RISC-V to build-many-glibcs.py Palmer Dabbelt
2018-01-26 5:45 ` Palmer Dabbelt [this message]
2018-01-26 5:45 ` [PATCH v6 15/16] RISC-V: Build Infastructure Palmer Dabbelt
2018-01-26 13:15 ` Joseph Myers
2018-01-26 18:00 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 02/16] Skeleton documentation for the RISC-V port Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 06/16] RISC-V: Startup and Dynamic Loading Code Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 05/16] RISC-V: ABI Implementation Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 11/16] RISC-V: Linux Syscall Interface Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 03/16] Add RISC-V entries to config.h.in Palmer Dabbelt
2018-01-26 12:49 ` RISC-V glibc port, v6 Joseph Myers
2018-01-26 17:51 ` Palmer Dabbelt
2018-01-26 15:05 ` Joseph Myers
2018-01-26 18:18 ` Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180126054443.22702-5-palmer@dabbelt.com \
--to=palmer@dabbelt.com \
--cc=andrew@sifive.com \
--cc=darius@bluespec.com \
--cc=dj@redhat.com \
--cc=joseph@codesourcery.com \
--cc=libc-alpha@sourceware.org \
--cc=patches@groups.riscv.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).