From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 45198 invoked by alias); 10 Dec 2018 17:37:16 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 45172 invoked by uid 89); 10 Dec 2018 17:37:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_NONE autolearn=no version=3.3.2 spammy=power6, kindly, H*F:D*br X-HELO: mo19.mail-out.ovh.net Date: Mon, 10 Dec 2018 18:08:00 -0000 From: "Gabriel F. T. Gomes" To: Rogerio Alves CC: Florian Weimer , Subject: Re: [PATCH] power: Fix VSCR position on ucontext Message-ID: <20181210153658.32b0e266@tereshkova> In-Reply-To: <20181207162959.5e5d8933@tereshkova> References: <8a619ad1-b7f2-04f8-f9a7-0a19cbf98f4c@linux.ibm.com> <87lg5va6a6.fsf@oldenburg.str.redhat.com> <20181116111825.43b60283@tereshkova.br.ibm.com> <5e1d1cab-7c91-90f8-82d2-fd38f8676f30@linux.ibm.com> <20181207162959.5e5d8933@tereshkova> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 11837148671460167360 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeghedguddtfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-SW-Source: 2018-12/txt/msg00324.txt.bz2 On Fri, 07 Dec 2018, Gabriel F. T. Gomes wrote: >On Fri, 07 Dec 2018, Rogerio Alves wrote: > >>+/* This test is supported only on POWER 5 or higher. */ >>+#define PPC_CPU_SUPPORTED (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS = | \ >>+ PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06= | \ >>+ PPC_FEATURE2_ARCH_2_07)=20=20 > >Is this actually needed? Glibc has code to fill all the bits for older >architectures in sysdeps/powerpc/hwcapinfo.c [1]. So, as far as I can >see, you only need to test for AT_HWCAP & PPC_FEATURE_POWER5. > >[1] https://sourceware.org/git/?p=3Dglibc.git;a=3Dblob;f=3Dsysdeps/powerpc= /hwcapinfo.c;h=3Da09b18309324423d0cdf04e88367899a4396bab7;hb=3DHEAD#l47 Hrm, that's only true for the hwcap info that is copied into the TCB, not when accessing it with getauxval, so my comment is wrong (as Rogerio kindly pointed out to me in a private message... thanks). So, nevermind this comment. On the other hand, on powerpc64 builds configured with --with-cpu set to power4, power5, and power6, (but not to power8 or power7), I got the following error message: ../sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c: In function =E2=80= =98do_test=E2=80=99: ../sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c:51:3: error: inconsi= stent operand constraints in an =E2=80=98asm=E2=80=99 asm volatile ("vspltisb %0,0\n" ^~~ I guess we didn't get this error message before, because of the `#ifdef ARCH_PWR8' statement. So, unless you know a better way to fix this, you should reintroduce the `#ifdef' statement (now, you could use ARCH_PWR7).