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CAT:NONE; SFS:(4636009)(346002)(396003)(376002)(39860400002)(136003)(46966005)(8676002)(55016002)(1076003)(16526019)(82310400003)(36906005)(7696005)(316002)(26005)(2906002)(6862004)(186003)(47076004)(82740400003)(478600001)(336012)(81166007)(44832011)(5660300002)(83380400001)(4326008)(70586007)(356005)(8936002)(8886007)(36756003)(86362001)(2616005)(70206006)(33656002)(956004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2020 13:18:23.6284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 754b5829-46b3-4997-0d70-08d85fc32638 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT064.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3366 X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, KAM_NUMSUBJECT, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Sep 2020 13:18:27 -0000 The 09/23/2020 14:56, Florian Weimer wrote: > * Szabolcs Nagy: > > The 09/23/2020 14:22, Florian Weimer via Libc-alpha wrote: > >> * Ben Woodard via Libc-alpha: > >> > >> > To fix this > >> > * The La_aarch64_regs structure was expanded to include x8 and the full > >> > sized NEON V registers that are required to be preserved by the ABI. > >> > >> Off-list, you said that the audit interface was completely broken on > >> AArch64. But it seems to be working enough for sotruss. So I do wonder > >> if we have to do a proper ABI transition here after all (bumping > >> LAV_CURRENT and all the consequences of that). > > > > i think plt hooks currently don't work for functions > > that take neon vector arguments because the save/restore > > logic clobbers the top bits (but such extern calls are > > not common since they need to use non-portable types) > > > > but i agree if it's not too intrusive to bump the audit > > abi then we should do so and then the incompatibility > > can be detected at least. > > The other question I had if we can do this once and make sure that the > CPU state is represented in such a way that we can efficiently save and > load it for later SVE support, so that we do not have to create two > copies (the architecture state and the audit representation), or bump > LAV_CURRENT for a new CPU. > > (I'm aware that AArch64 would be pioneering audit support for vector > calling conventions.) we don't have a way to do this in the architecture (i.e. reg state save/restore operations) we can have something in the kernel (which needs to know about the supported registers) but i assume using a syscall for this is too much overhead. (maybe in vdso? sounds ugly if we need it before vdso is set up) (i can tell the architects about this requirement in case they invent new register state.)