* [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041
@ 2020-10-08 16:12 H.J. Lu
2020-10-08 16:12 ` [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support H.J. Lu
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-08 16:12 UTC (permalink / raw)
To: libc-alpha
Update CPUID support in <sys/platform/x86.h> for Intel Architecture
Instruction Set Extensions and Future Features Programming Reference
revision 041:
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
for Intel UINTR, AVX512_FP16, AVX-VNNI, Intel HRESET, Fast Short REP CMP
and SCA (FSRCS), Fast Short REP STO (FSRS) and Fast Zero-Length REP MOV
(FZLRM).
H.J. Lu (5):
<sys/platform/x86.h>: Add Intel UINTR support
<sys/platform/x86.h>: Add AVX512_FP16 support
<sys/platform/x86.h>: Add AVX-VNNI support
<sys/platform/x86.h>: Add Intel HRESET support
<sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support
manual/platform.texi | 21 +++++++++++++++++++++
sysdeps/x86/cpu-features.c | 7 +++++++
sysdeps/x86/sys/platform/x86.h | 27 +++++++++++++++++++++------
sysdeps/x86/tst-get-cpu-features.c | 12 ++++++++++++
4 files changed, 61 insertions(+), 6 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
@ 2020-10-08 16:12 ` H.J. Lu
2020-10-08 16:12 ` [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support H.J. Lu
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-08 16:12 UTC (permalink / raw)
To: libc-alpha
Add Intel UINTR support to <sys/platform/x86.h>.
---
manual/platform.texi | 3 +++
sysdeps/x86/sys/platform/x86.h | 6 +++---
sysdeps/x86/tst-get-cpu-features.c | 1 +
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/manual/platform.texi b/manual/platform.texi
index 95b0ed0642..0dd12a4353 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -583,6 +583,9 @@ using a TSC deadline value.
@item
@code{TSXLDTRK} -- TSXLDTRK instructions.
+@item
+@code{UINTR} -- User interrupts.
+
@item
@code{UMIP} -- User-mode instruction prevention.
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 2ba6d3c4f2..22bb28449d 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -241,7 +241,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define bit_cpu_AVX512_4VNNIW (1u << 2)
#define bit_cpu_AVX512_4FMAPS (1u << 3)
#define bit_cpu_FSRM (1u << 4)
-#define bit_cpu_INDEX_7_EDX_5 (1u << 5)
+#define bit_cpu_UINTR (1u << 5)
#define bit_cpu_INDEX_7_EDX_6 (1u << 6)
#define bit_cpu_INDEX_7_EDX_7 (1u << 7)
#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
@@ -460,7 +460,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define index_cpu_AVX512_4VNNIW COMMON_CPUID_INDEX_7
#define index_cpu_AVX512_4FMAPS COMMON_CPUID_INDEX_7
#define index_cpu_FSRM COMMON_CPUID_INDEX_7
-#define index_cpu_INDEX_7_EDX_5 COMMON_CPUID_INDEX_7
+#define index_cpu_UINTR COMMON_CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_6 COMMON_CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_7 COMMON_CPUID_INDEX_7
#define index_cpu_AVX512_VP2INTERSECT COMMON_CPUID_INDEX_7
@@ -679,7 +679,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define reg_AVX512_4VNNIW edx
#define reg_AVX512_4FMAPS edx
#define reg_FSRM edx
-#define reg_INDEX_7_EDX_5 edx
+#define reg_UINTR edx
#define reg_INDEX_7_EDX_6 edx
#define reg_INDEX_7_EDX_7 edx
#define reg_AVX512_VP2INTERSECT edx
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index d11eac9853..d160f7c7a1 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -182,6 +182,7 @@ do_test (void)
CHECK_CPU_FEATURE (AVX512_4VNNIW);
CHECK_CPU_FEATURE (AVX512_4FMAPS);
CHECK_CPU_FEATURE (FSRM);
+ CHECK_CPU_FEATURE (UINTR);
CHECK_CPU_FEATURE (AVX512_VP2INTERSECT);
CHECK_CPU_FEATURE (MD_CLEAR);
CHECK_CPU_FEATURE (SERIALIZE);
--
2.26.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
2020-10-08 16:12 ` [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support H.J. Lu
@ 2020-10-08 16:12 ` H.J. Lu
2020-10-08 16:12 ` [PATCH 3/5] <sys/platform/x86.h>: Add AVX-VNNI support H.J. Lu
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-08 16:12 UTC (permalink / raw)
To: libc-alpha
Add AVX512_FP16 support to <sys/platform/x86.h>.
---
manual/platform.texi | 3 +++
sysdeps/x86/cpu-features.c | 2 ++
sysdeps/x86/sys/platform/x86.h | 6 +++---
sysdeps/x86/tst-get-cpu-features.c | 2 ++
4 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/manual/platform.texi b/manual/platform.texi
index 0dd12a4353..4f5fdff9d9 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -210,6 +210,9 @@ The supported processor features are:
@item
@code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
+@item
+@code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
+
@item
@code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 6551df19c0..4ecb8cee2c 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -175,6 +175,8 @@ update_usable (struct cpu_features *cpu_features)
AVX512_VP2INTERSECT);
/* Determine if AVX512_BF16 is usable. */
CPU_FEATURE_SET_USABLE (cpu_features, AVX512_BF16);
+ /* Determine if AVX512_FP16 is usable. */
+ CPU_FEATURE_SET_USABLE (cpu_features, AVX512_FP16);
}
}
}
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 22bb28449d..00cd151199 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -259,7 +259,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define bit_cpu_IBT (1u << 20)
#define bit_cpu_INDEX_7_EDX_21 (1u << 21)
#define bit_cpu_AMX_BF16 (1u << 22)
-#define bit_cpu_INDEX_7_EDX_23 (1u << 23)
+#define bit_cpu_AVX512_FP16 (1u << 23)
#define bit_cpu_AMX_TILE (1u << 24)
#define bit_cpu_AMX_INT8 (1u << 25)
#define bit_cpu_IBRS_IBPB (1u << 26)
@@ -478,7 +478,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define index_cpu_IBT COMMON_CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_21 COMMON_CPUID_INDEX_7
#define index_cpu_AMX_BF16 COMMON_CPUID_INDEX_7
-#define index_cpu_INDEX_7_EDX_23 COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_FP16 COMMON_CPUID_INDEX_7
#define index_cpu_AMX_TILE COMMON_CPUID_INDEX_7
#define index_cpu_AMX_INT8 COMMON_CPUID_INDEX_7
#define index_cpu_IBRS_IBPB COMMON_CPUID_INDEX_7
@@ -697,7 +697,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define reg_IBT edx
#define reg_INDEX_7_EDX_21 edx
#define reg_AMX_BF16 edx
-#define reg_INDEX_7_EDX_23 edx
+#define reg_AVX512_FP16 edx
#define reg_AMX_TILE edx
#define reg_AMX_INT8 edx
#define reg_IBRS_IBPB edx
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index d160f7c7a1..7262c3a3fa 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -191,6 +191,7 @@ do_test (void)
CHECK_CPU_FEATURE (PCONFIG);
CHECK_CPU_FEATURE (IBT);
CHECK_CPU_FEATURE (AMX_BF16);
+ CHECK_CPU_FEATURE (AVX512_FP16);
CHECK_CPU_FEATURE (AMX_TILE);
CHECK_CPU_FEATURE (AMX_INT8);
CHECK_CPU_FEATURE (IBRS_IBPB);
@@ -345,6 +346,7 @@ do_test (void)
CHECK_CPU_FEATURE_USABLE (TSXLDTRK);
CHECK_CPU_FEATURE_USABLE (PCONFIG);
CHECK_CPU_FEATURE_USABLE (AMX_BF16);
+ CHECK_CPU_FEATURE_USABLE (AVX512_FP16);
CHECK_CPU_FEATURE_USABLE (AMX_TILE);
CHECK_CPU_FEATURE_USABLE (AMX_INT8);
CHECK_CPU_FEATURE_USABLE (IBRS_IBPB);
--
2.26.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/5] <sys/platform/x86.h>: Add AVX-VNNI support
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
2020-10-08 16:12 ` [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support H.J. Lu
2020-10-08 16:12 ` [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support H.J. Lu
@ 2020-10-08 16:12 ` H.J. Lu
2020-10-08 16:12 ` [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support H.J. Lu
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-08 16:12 UTC (permalink / raw)
To: libc-alpha
Add AVX-VNNI support to <sys/platform/x86.h>.
---
manual/platform.texi | 3 +++
sysdeps/x86/cpu-features.c | 2 ++
sysdeps/x86/sys/platform/x86.h | 3 +++
sysdeps/x86/tst-get-cpu-features.c | 2 ++
4 files changed, 10 insertions(+)
diff --git a/manual/platform.texi b/manual/platform.texi
index 4f5fdff9d9..283f255679 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -198,6 +198,9 @@ The supported processor features are:
@item
@code{AVX2} -- The AVX2 instruction extensions.
+@item
+@code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
+
@item
@code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 4ecb8cee2c..b0fac22c27 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -119,6 +119,8 @@ update_usable (struct cpu_features *cpu_features)
cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
|= bit_arch_AVX_Fast_Unaligned_Load;
}
+ /* Determine if AVX-VNNI is usable. */
+ CPU_FEATURE_SET_USABLE (cpu_features, AVX_VNNI);
/* Determine if FMA is usable. */
CPU_FEATURE_SET_USABLE (cpu_features, FMA);
/* Determine if VAES is usable. */
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 00cd151199..276de1eb6b 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -311,6 +311,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* COMMON_CPUID_INDEX_7_ECX_1. */
/* EAX. */
+#define bit_cpu_AVX_VNNI (1u << 4)
#define bit_cpu_AVX512_BF16 (1u << 5)
/* COMMON_CPUID_INDEX_19. */
@@ -530,6 +531,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* COMMON_CPUID_INDEX_7_ECX_1. */
/* EAX. */
+#define index_cpu_AVX_VNNI COMMON_CPUID_INDEX_7_ECX_1
#define index_cpu_AVX512_BF16 COMMON_CPUID_INDEX_7_ECX_1
/* COMMON_CPUID_INDEX_19. */
@@ -749,6 +751,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* COMMON_CPUID_INDEX_7_ECX_1. */
/* EAX. */
+#define reg_AVX_VNNI eax
#define reg_AVX512_BF16 eax
/* COMMON_CPUID_INDEX_19. */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 7262c3a3fa..e87158d45b 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -221,6 +221,7 @@ do_test (void)
CHECK_CPU_FEATURE (XFD);
CHECK_CPU_FEATURE (INVARIANT_TSC);
CHECK_CPU_FEATURE (WBNOINVD);
+ CHECK_CPU_FEATURE (AVX_VNNI);
CHECK_CPU_FEATURE (AVX512_BF16);
CHECK_CPU_FEATURE (AESKLE);
CHECK_CPU_FEATURE (WIDE_KL);
@@ -376,6 +377,7 @@ do_test (void)
CHECK_CPU_FEATURE_USABLE (XFD);
CHECK_CPU_FEATURE_USABLE (INVARIANT_TSC);
CHECK_CPU_FEATURE_USABLE (WBNOINVD);
+ CHECK_CPU_FEATURE_USABLE (AVX_VNNI);
CHECK_CPU_FEATURE_USABLE (AVX512_BF16);
CHECK_CPU_FEATURE_USABLE (AESKLE);
CHECK_CPU_FEATURE_USABLE (WIDE_KL);
--
2.26.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
` (2 preceding siblings ...)
2020-10-08 16:12 ` [PATCH 3/5] <sys/platform/x86.h>: Add AVX-VNNI support H.J. Lu
@ 2020-10-08 16:12 ` H.J. Lu
2020-10-08 16:12 ` [PATCH 5/5] <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support H.J. Lu
2020-10-09 16:49 ` [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
5 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-08 16:12 UTC (permalink / raw)
To: libc-alpha
Add Intel HRESET support to <sys/platform/x86.h>.
---
manual/platform.texi | 3 +++
sysdeps/x86/sys/platform/x86.h | 3 +++
sysdeps/x86/tst-get-cpu-features.c | 1 +
3 files changed, 7 insertions(+)
diff --git a/manual/platform.texi b/manual/platform.texi
index 283f255679..1e44525552 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -346,6 +346,9 @@ extensions.
@item
@code{HTT} -- Max APIC IDs reserved field is Valid.
+@item
+@code{HRESET} -- History reset.
+
@item
@code{HYBRID} -- Hybrid processor.
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 276de1eb6b..394f1c41a6 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -313,6 +313,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define bit_cpu_AVX_VNNI (1u << 4)
#define bit_cpu_AVX512_BF16 (1u << 5)
+#define bit_cpu_HRESET (1u << 22)
/* COMMON_CPUID_INDEX_19. */
@@ -533,6 +534,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define index_cpu_AVX_VNNI COMMON_CPUID_INDEX_7_ECX_1
#define index_cpu_AVX512_BF16 COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_HRESET COMMON_CPUID_INDEX_7_ECX_1
/* COMMON_CPUID_INDEX_19. */
@@ -753,6 +755,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define reg_AVX_VNNI eax
#define reg_AVX512_BF16 eax
+#define reg_HRESET eax
/* COMMON_CPUID_INDEX_19. */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index e87158d45b..aacaa49045 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -223,6 +223,7 @@ do_test (void)
CHECK_CPU_FEATURE (WBNOINVD);
CHECK_CPU_FEATURE (AVX_VNNI);
CHECK_CPU_FEATURE (AVX512_BF16);
+ CHECK_CPU_FEATURE (HRESET);
CHECK_CPU_FEATURE (AESKLE);
CHECK_CPU_FEATURE (WIDE_KL);
--
2.26.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 5/5] <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
` (3 preceding siblings ...)
2020-10-08 16:12 ` [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support H.J. Lu
@ 2020-10-08 16:12 ` H.J. Lu
2020-10-09 16:49 ` [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
5 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-08 16:12 UTC (permalink / raw)
To: libc-alpha
Add Fast Short REP CMP and SCA (FSRCS), Fast Short REP STO (FSRS) and
Fast Zero-Length REP MOV (FZLRM) support to <sys/platform/x86.h>.
---
manual/platform.texi | 9 +++++++++
sysdeps/x86/cpu-features.c | 3 +++
sysdeps/x86/sys/platform/x86.h | 9 +++++++++
sysdeps/x86/tst-get-cpu-features.c | 6 ++++++
4 files changed, 27 insertions(+)
diff --git a/manual/platform.texi b/manual/platform.texi
index 1e44525552..217a5c99ad 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -331,9 +331,18 @@ extensions.
@item
@code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
+@item
+@code{FSRCS} -- Fast Short REP CMP and SCA.
+
@item
@code{FSRM} -- Fast Short REP MOV.
+@item
+@code{FSRS} -- Fast Short REP STO.
+
+@item
+@code{FZLRM} -- Fast Zero-Length REP MOV.
+
@item
@code{FXSR} -- FXSAVE and FXRSTOR instructions.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index b0fac22c27..286ff96771 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -93,6 +93,9 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, TBM);
CPU_FEATURE_SET_USABLE (cpu_features, RDTSCP);
CPU_FEATURE_SET_USABLE (cpu_features, WBNOINVD);
+ CPU_FEATURE_SET_USABLE (cpu_features, FZLRM);
+ CPU_FEATURE_SET_USABLE (cpu_features, FSRS);
+ CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
/* Can we call xgetbv? */
if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE))
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 394f1c41a6..3ef92b04e8 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -313,6 +313,9 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define bit_cpu_AVX_VNNI (1u << 4)
#define bit_cpu_AVX512_BF16 (1u << 5)
+#define bit_cpu_FZLRM (1u << 10)
+#define bit_cpu_FSRS (1u << 11)
+#define bit_cpu_FSRCS (1u << 12)
#define bit_cpu_HRESET (1u << 22)
/* COMMON_CPUID_INDEX_19. */
@@ -534,6 +537,9 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define index_cpu_AVX_VNNI COMMON_CPUID_INDEX_7_ECX_1
#define index_cpu_AVX512_BF16 COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_FZLRM COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_FSRS COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_FSRCS COMMON_CPUID_INDEX_7_ECX_1
#define index_cpu_HRESET COMMON_CPUID_INDEX_7_ECX_1
/* COMMON_CPUID_INDEX_19. */
@@ -755,6 +761,9 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define reg_AVX_VNNI eax
#define reg_AVX512_BF16 eax
+#define reg_FZLRM eax
+#define reg_FSRS eax
+#define reg_FSRCS eax
#define reg_HRESET eax
/* COMMON_CPUID_INDEX_19. */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index aacaa49045..667aa27117 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -223,6 +223,9 @@ do_test (void)
CHECK_CPU_FEATURE (WBNOINVD);
CHECK_CPU_FEATURE (AVX_VNNI);
CHECK_CPU_FEATURE (AVX512_BF16);
+ CHECK_CPU_FEATURE (FZLRM);
+ CHECK_CPU_FEATURE (FSRS);
+ CHECK_CPU_FEATURE (FSRCS);
CHECK_CPU_FEATURE (HRESET);
CHECK_CPU_FEATURE (AESKLE);
CHECK_CPU_FEATURE (WIDE_KL);
@@ -380,6 +383,9 @@ do_test (void)
CHECK_CPU_FEATURE_USABLE (WBNOINVD);
CHECK_CPU_FEATURE_USABLE (AVX_VNNI);
CHECK_CPU_FEATURE_USABLE (AVX512_BF16);
+ CHECK_CPU_FEATURE_USABLE (FZLRM);
+ CHECK_CPU_FEATURE_USABLE (FSRS);
+ CHECK_CPU_FEATURE_USABLE (FSRCS);
CHECK_CPU_FEATURE_USABLE (AESKLE);
CHECK_CPU_FEATURE_USABLE (WIDE_KL);
--
2.26.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
` (4 preceding siblings ...)
2020-10-08 16:12 ` [PATCH 5/5] <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support H.J. Lu
@ 2020-10-09 16:49 ` H.J. Lu
5 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2020-10-09 16:49 UTC (permalink / raw)
To: GNU C Library
On Thu, Oct 8, 2020 at 9:12 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> Update CPUID support in <sys/platform/x86.h> for Intel Architecture
> Instruction Set Extensions and Future Features Programming Reference
> revision 041:
>
> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
>
> for Intel UINTR, AVX512_FP16, AVX-VNNI, Intel HRESET, Fast Short REP CMP
> and SCA (FSRCS), Fast Short REP STO (FSRS) and Fast Zero-Length REP MOV
> (FZLRM).
>
> H.J. Lu (5):
> <sys/platform/x86.h>: Add Intel UINTR support
> <sys/platform/x86.h>: Add AVX512_FP16 support
> <sys/platform/x86.h>: Add AVX-VNNI support
> <sys/platform/x86.h>: Add Intel HRESET support
> <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support
>
> manual/platform.texi | 21 +++++++++++++++++++++
> sysdeps/x86/cpu-features.c | 7 +++++++
> sysdeps/x86/sys/platform/x86.h | 27 +++++++++++++++++++++------
> sysdeps/x86/tst-get-cpu-features.c | 12 ++++++++++++
> 4 files changed, 61 insertions(+), 6 deletions(-)
>
I am checking them in.
--
H.J.
^ permalink raw reply [flat|nested] 7+ messages in thread
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2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
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2020-10-08 16:12 ` [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support H.J. Lu
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2020-10-08 16:12 ` [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support H.J. Lu
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2020-10-09 16:49 ` [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu
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