* V4 [PATCH 0/2] ld.so: Add --list-tunables to print tunable values @ 2020-10-31 15:44 H.J. Lu 2020-10-31 15:44 ` V4 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features H.J. Lu 2020-10-31 15:44 ` V4 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values H.J. Lu 0 siblings, 2 replies; 12+ messages in thread From: H.J. Lu @ 2020-10-31 15:44 UTC (permalink / raw) To: libc-alpha; +Cc: Florian Weimer, Carlos O'Donell Tunable values and their minimum/maximum values are invisible to users. This patch set adds --list-tunables to ld.so to print tunable values with their minimum and maximum values. --list-tunables works on i686 and x86-64. Please test --list-tunables on your native processors. users/hjl/tunable/master branch at: https://gitlab.com/x86-glibc/glibc/-/commits/users/hjl/tunable/master contains the same set of patches. On x86, to make cache info accessible to --list-tunables, they are moved to cpu_features in ld.so and TUNABLE_SET_WITH_BOUNDS is used to update tunable bounds. Rebased on top of commit cb3a749a22a55645dc6a52659eea765300623f98 Author: Florian Weimer <fweimer@redhat.com> Date: Wed Oct 28 15:53:26 2020 +0100 x86: Restore processing of cache size tunables in init_cacheinfo H.J. Lu (2): x86: Move x86 processor cache info to cpu_features ld.so: Add --list-tunables to print tunable values NEWS | 2 + elf/Makefile | 8 + elf/dl-main.h | 2 +- elf/dl-tunables.c | 36 +++ elf/dl-tunables.h | 2 + elf/dl-usage.c | 7 +- elf/rtld.c | 23 ++ manual/tunables.texi | 37 +++ sysdeps/x86/cacheinfo.c | 46 ++- sysdeps/x86/cacheinfo.h | 400 ++----------------------- sysdeps/x86/cpu-features.c | 35 +-- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++++++++++ sysdeps/x86/include/cpu-features.h | 22 ++ 13 files changed, 666 insertions(+), 414 deletions(-) -- 2.28.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* V4 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features 2020-10-31 15:44 V4 [PATCH 0/2] ld.so: Add --list-tunables to print tunable values H.J. Lu @ 2020-10-31 15:44 ` H.J. Lu 2021-01-14 14:13 ` Adhemerval Zanella 2020-10-31 15:44 ` V4 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values H.J. Lu 1 sibling, 1 reply; 12+ messages in thread From: H.J. Lu @ 2020-10-31 15:44 UTC (permalink / raw) To: libc-alpha; +Cc: Florian Weimer, Carlos O'Donell 1. Move x86 processor cache info to _dl_x86_cpu_features in ld.so. 2. Update tunable bounds with TUNABLE_SET_WITH_BOUNDS. 3. Move x86 cache info initialization to dl-cacheinfo.h and initialize x86 cache info in init_cpu_features (). 4. Put x86 cache info for libc in cacheinfo.h, which is included in libc-start.c in libc.a and is included in cacheinfo.c in libc.so. --- sysdeps/x86/cacheinfo.c | 46 ++- sysdeps/x86/cacheinfo.h | 400 ++----------------------- sysdeps/x86/cpu-features.c | 35 +-- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++++++++++ sysdeps/x86/include/cpu-features.h | 22 ++ 5 files changed, 551 insertions(+), 412 deletions(-) diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 0d2fe3a2fa..e1ea4d5228 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -18,11 +18,8 @@ #if IS_IN (libc) -#include <assert.h> #include <unistd.h> -#include <cpuid.h> #include <ldsodefs.h> -#include <dl-cacheinfo.h> /* Get the value of the system variable NAME. */ long int @@ -30,20 +27,45 @@ attribute_hidden __cache_sysconf (int name) { const struct cpu_features *cpu_features = __get_cpu_features (); + switch (name) + { + case _SC_LEVEL1_ICACHE_SIZE: + return cpu_features->level1_icache_size; - if (cpu_features->basic.kind == arch_kind_intel) - return handle_intel (name, cpu_features); + case _SC_LEVEL1_DCACHE_SIZE: + return cpu_features->level1_dcache_size; - if (cpu_features->basic.kind == arch_kind_amd) - return handle_amd (name); + case _SC_LEVEL1_DCACHE_ASSOC: + return cpu_features->level1_dcache_assoc; - if (cpu_features->basic.kind == arch_kind_zhaoxin) - return handle_zhaoxin (name); + case _SC_LEVEL1_DCACHE_LINESIZE: + return cpu_features->level1_dcache_linesize; - // XXX Fill in more vendors. + case _SC_LEVEL2_CACHE_SIZE: + return cpu_features->level2_cache_size; - /* CPU not known, we have no information. */ - return 0; + case _SC_LEVEL2_CACHE_ASSOC: + return cpu_features->level2_cache_assoc; + + case _SC_LEVEL2_CACHE_LINESIZE: + return cpu_features->level2_cache_linesize; + + case _SC_LEVEL3_CACHE_SIZE: + return cpu_features->level3_cache_size; + + case _SC_LEVEL3_CACHE_ASSOC: + return cpu_features->level3_cache_assoc; + + case _SC_LEVEL3_CACHE_LINESIZE: + return cpu_features->level3_cache_linesize; + + case _SC_LEVEL4_CACHE_SIZE: + return cpu_features->level4_cache_size; + + default: + break; + } + return -1; } # ifdef SHARED diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h index 0aec0e2875..5aa40b45b5 100644 --- a/sysdeps/x86/cacheinfo.h +++ b/sysdeps/x86/cacheinfo.h @@ -18,7 +18,16 @@ #include <assert.h> #include <unistd.h> +#include <cpuid.h> +#include <cpu-features.h> +#if HAVE_TUNABLES +# define TUNABLE_NAMESPACE cpu +# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ +# include <elf/dl-tunables.h> +#endif + +#if IS_IN (libc) /* Data cache size for use in memory and string routines, typically L1 size, rounded to multiple of 256 bytes. */ long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2; @@ -45,385 +54,30 @@ long int __x86_rep_movsb_threshold attribute_hidden = 2048; /* Threshold to use Enhanced REP STOSB. */ long int __x86_rep_stosb_threshold attribute_hidden = 2048; -static void -get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, - long int core) -{ - unsigned int eax; - unsigned int ebx; - unsigned int ecx; - unsigned int edx; - - /* Number of logical processors sharing L2 cache. */ - int threads_l2; - - /* Number of logical processors sharing L3 cache. */ - int threads_l3; - - const struct cpu_features *cpu_features = __get_cpu_features (); - int max_cpuid = cpu_features->basic.max_cpuid; - unsigned int family = cpu_features->basic.family; - unsigned int model = cpu_features->basic.model; - long int shared = *shared_ptr; - unsigned int threads = *threads_ptr; - bool inclusive_cache = true; - bool support_count_mask = true; - - /* Try L3 first. */ - unsigned int level = 3; - - if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) - support_count_mask = false; - - if (shared <= 0) - { - /* Try L2 otherwise. */ - level = 2; - shared = core; - threads_l2 = 0; - threads_l3 = -1; - } - else - { - threads_l2 = 0; - threads_l3 = 0; - } - - /* A value of 0 for the HTT bit indicates there is only a single - logical processor. */ - if (HAS_CPU_FEATURE (HTT)) - { - /* Figure out the number of logical threads that share the - highest cache level. */ - if (max_cpuid >= 4) - { - int i = 0; - - /* Query until cache level 2 and 3 are enumerated. */ - int check = 0x1 | (threads_l3 == 0) << 1; - do - { - __cpuid_count (4, i++, eax, ebx, ecx, edx); - - /* There seems to be a bug in at least some Pentium Ds - which sometimes fail to iterate all cache parameters. - Do not loop indefinitely here, stop in this case and - assume there is no such information. */ - if (cpu_features->basic.kind == arch_kind_intel - && (eax & 0x1f) == 0 ) - goto intel_bug_no_cache_info; - - switch ((eax >> 5) & 0x7) - { - default: - break; - case 2: - if ((check & 0x1)) - { - /* Get maximum number of logical processors - sharing L2 cache. */ - threads_l2 = (eax >> 14) & 0x3ff; - check &= ~0x1; - } - break; - case 3: - if ((check & (0x1 << 1))) - { - /* Get maximum number of logical processors - sharing L3 cache. */ - threads_l3 = (eax >> 14) & 0x3ff; - - /* Check if L2 and L3 caches are inclusive. */ - inclusive_cache = (edx & 0x2) != 0; - check &= ~(0x1 << 1); - } - break; - } - } - while (check); - - /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum - numbers of addressable IDs for logical processors sharing - the cache, instead of the maximum number of threads - sharing the cache. */ - if (max_cpuid >= 11 && support_count_mask) - { - /* Find the number of logical processors shipped in - one core and apply count mask. */ - i = 0; - - /* Count SMT only if there is L3 cache. Always count - core if there is no L3 cache. */ - int count = ((threads_l2 > 0 && level == 3) - | ((threads_l3 > 0 - || (threads_l2 > 0 && level == 2)) << 1)); - - while (count) - { - __cpuid_count (11, i++, eax, ebx, ecx, edx); - - int shipped = ebx & 0xff; - int type = ecx & 0xff00; - if (shipped == 0 || type == 0) - break; - else if (type == 0x100) - { - /* Count SMT. */ - if ((count & 0x1)) - { - int count_mask; - - /* Compute count mask. */ - asm ("bsr %1, %0" - : "=r" (count_mask) : "g" (threads_l2)); - count_mask = ~(-1 << (count_mask + 1)); - threads_l2 = (shipped - 1) & count_mask; - count &= ~0x1; - } - } - else if (type == 0x200) - { - /* Count core. */ - if ((count & (0x1 << 1))) - { - int count_mask; - int threads_core - = (level == 2 ? threads_l2 : threads_l3); - - /* Compute count mask. */ - asm ("bsr %1, %0" - : "=r" (count_mask) : "g" (threads_core)); - count_mask = ~(-1 << (count_mask + 1)); - threads_core = (shipped - 1) & count_mask; - if (level == 2) - threads_l2 = threads_core; - else - threads_l3 = threads_core; - count &= ~(0x1 << 1); - } - } - } - } - if (threads_l2 > 0) - threads_l2 += 1; - if (threads_l3 > 0) - threads_l3 += 1; - if (level == 2) - { - if (threads_l2) - { - threads = threads_l2; - if (cpu_features->basic.kind == arch_kind_intel - && threads > 2 - && family == 6) - switch (model) - { - case 0x37: - case 0x4a: - case 0x4d: - case 0x5a: - case 0x5d: - /* Silvermont has L2 cache shared by 2 cores. */ - threads = 2; - break; - default: - break; - } - } - } - else if (threads_l3) - threads = threads_l3; - } - else - { -intel_bug_no_cache_info: - /* Assume that all logical threads share the highest cache - level. */ - threads - = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx - >> 16) & 0xff); - } - - /* Cap usage of highest cache level to the number of supported - threads. */ - if (shared > 0 && threads > 0) - shared /= threads; - } - - /* Account for non-inclusive L2 and L3 caches. */ - if (!inclusive_cache) - { - if (threads_l2 > 0) - core /= threads_l2; - shared += core; - } - - *shared_ptr = shared; - *threads_ptr = threads; -} - static void init_cacheinfo (void) { - /* Find out what brand of processor. */ - unsigned int ebx; - unsigned int ecx; - unsigned int edx; - int max_cpuid_ex; - long int data = -1; - long int shared = -1; - long int core; - unsigned int threads = 0; const struct cpu_features *cpu_features = __get_cpu_features (); + long int data = cpu_features->data_cache_size; + __x86_raw_data_cache_size_half = data / 2; + __x86_raw_data_cache_size = data; + /* Round data cache size to multiple of 256 bytes. */ + data = data & ~255L; + __x86_data_cache_size_half = data / 2; + __x86_data_cache_size = data; + + long int shared = cpu_features->shared_cache_size; + __x86_raw_shared_cache_size_half = shared / 2; + __x86_raw_shared_cache_size = shared; + /* Round shared cache size to multiple of 256 bytes. */ + shared = shared & ~255L; + __x86_shared_cache_size_half = shared / 2; + __x86_shared_cache_size = shared; - /* NB: In libc.so, cpu_features is defined in ld.so and is initialized - by DL_PLATFORM_INIT or IFUNC relocation before init_cacheinfo is - called by IFUNC relocation. In libc.a, init_cacheinfo is called - from init_cpu_features by ARCH_INIT_CPU_FEATURES. */ - assert (cpu_features->basic.kind != arch_kind_unknown); - - if (cpu_features->basic.kind == arch_kind_intel) - { - data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); - core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); - shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); - - get_common_cache_info (&shared, &threads, core); - } - else if (cpu_features->basic.kind == arch_kind_zhaoxin) - { - data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); - core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); - shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); - - get_common_cache_info (&shared, &threads, core); - } - else if (cpu_features->basic.kind == arch_kind_amd) - { - data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); - long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE); - shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); - - /* Get maximum extended function. */ - __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); - - if (shared <= 0) - /* No shared L3 cache. All we have is the L2 cache. */ - shared = core; - else - { - /* Figure out the number of logical threads that share L3. */ - if (max_cpuid_ex >= 0x80000008) - { - /* Get width of APIC ID. */ - __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); - threads = 1 << ((ecx >> 12) & 0x0f); - } - - if (threads == 0 || cpu_features->basic.family >= 0x17) - { - /* If APIC ID width is not available, use logical - processor count. */ - __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); - - if ((edx & (1 << 28)) != 0) - threads = (ebx >> 16) & 0xff; - } - - /* Cap usage of highest cache level to the number of - supported threads. */ - if (threads > 0) - shared /= threads; - - /* Get shared cache per ccx for Zen architectures. */ - if (cpu_features->basic.family >= 0x17) - { - unsigned int eax; - - /* Get number of threads share the L3 cache in CCX. */ - __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); - - unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; - shared *= threads_per_ccx; - } - else - { - /* Account for exclusive L2 and L3 caches. */ - shared += core; - } - } - } - - /* Prefer cache size configure via tuning. */ - if (cpu_features->data_cache_size != 0) - data = cpu_features->data_cache_size; - - if (data > 0) - { - __x86_raw_data_cache_size_half = data / 2; - __x86_raw_data_cache_size = data; - /* Round data cache size to multiple of 256 bytes. */ - data = data & ~255L; - __x86_data_cache_size_half = data / 2; - __x86_data_cache_size = data; - } - - /* Prefer cache size configure via tuning. */ - if (cpu_features->shared_cache_size != 0) - shared = cpu_features->shared_cache_size; - - if (shared > 0) - { - __x86_raw_shared_cache_size_half = shared / 2; - __x86_raw_shared_cache_size = shared; - /* Round shared cache size to multiple of 256 bytes. */ - shared = shared & ~255L; - __x86_shared_cache_size_half = shared / 2; - __x86_shared_cache_size = shared; - } - - /* The default setting for the non_temporal threshold is 3/4 of one - thread's share of the chip's cache. For most Intel and AMD processors - with an initial release date between 2017 and 2020, a thread's typical - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 - threshold leaves 125 KBytes to 500 KBytes of the thread's data - in cache after a maximum temporal copy, which will maintain - in cache a reasonable portion of the thread's stack and other - active data. If the threshold is set higher than one thread's - share of the cache, it has a substantial risk of negatively - impacting the performance of other threads running on the chip. */ __x86_shared_non_temporal_threshold - = (cpu_features->non_temporal_threshold != 0 - ? cpu_features->non_temporal_threshold - : __x86_shared_cache_size * 3 / 4); - - /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ - unsigned int minimum_rep_movsb_threshold; - /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ - unsigned int rep_movsb_threshold; - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) - && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) - { - rep_movsb_threshold = 2048 * (64 / 16); - minimum_rep_movsb_threshold = 64 * 8; - } - else if (CPU_FEATURE_PREFERRED_P (cpu_features, - AVX_Fast_Unaligned_Load)) - { - rep_movsb_threshold = 2048 * (32 / 16); - minimum_rep_movsb_threshold = 32 * 8; - } - else - { - rep_movsb_threshold = 2048 * (16 / 16); - minimum_rep_movsb_threshold = 16 * 8; - } - if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold) - __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; - else - __x86_rep_movsb_threshold = rep_movsb_threshold; + = cpu_features->non_temporal_threshold; -# if HAVE_TUNABLES + __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; -# endif } +#endif diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index f26deba38d..51c12d89ca 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -16,21 +16,12 @@ License along with the GNU C Library; if not, see <https://www.gnu.org/licenses/>. */ -#include <cpuid.h> #include <dl-hwcap.h> #include <libc-pointer-arith.h> -#if IS_IN (libc) && !defined SHARED -# include <assert.h> -# include <unistd.h> -# include <dl-cacheinfo.h> -# include <cacheinfo.h> -#endif +#include <cacheinfo.h> +#include <dl-cacheinfo.h> #if HAVE_TUNABLES -# define TUNABLE_NAMESPACE cpu -# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ -# include <elf/dl-tunables.h> - extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *) attribute_hidden; @@ -642,24 +633,14 @@ no_cpuid: cpu_features->basic.model = model; cpu_features->basic.stepping = stepping; + dl_init_cacheinfo (cpu_features); + #if HAVE_TUNABLES TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps)); - cpu_features->non_temporal_threshold - = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); - cpu_features->rep_movsb_threshold - = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); - cpu_features->rep_stosb_threshold - = TUNABLE_GET (x86_rep_stosb_threshold, long int, NULL); - cpu_features->data_cache_size - = TUNABLE_GET (x86_data_cache_size, long int, NULL); - cpu_features->shared_cache_size - = TUNABLE_GET (x86_shared_cache_size, long int, NULL); -#endif - - /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */ -#if !HAVE_TUNABLES && defined SHARED - /* The glibc.cpu.hwcap_mask tunable is initialized already, so no need to do - this. */ +#elif defined SHARED + /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. The + glibc.cpu.hwcap_mask tunable is initialized already, so no + need to do this. */ GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT; #endif diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index b2b90074b0..9632ee7818 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -476,3 +476,463 @@ handle_zhaoxin (int name) /* Nothing found. */ return 0; } + +static void +get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, + long int core) +{ + unsigned int eax; + unsigned int ebx; + unsigned int ecx; + unsigned int edx; + + /* Number of logical processors sharing L2 cache. */ + int threads_l2; + + /* Number of logical processors sharing L3 cache. */ + int threads_l3; + + const struct cpu_features *cpu_features = __get_cpu_features (); + int max_cpuid = cpu_features->basic.max_cpuid; + unsigned int family = cpu_features->basic.family; + unsigned int model = cpu_features->basic.model; + long int shared = *shared_ptr; + unsigned int threads = *threads_ptr; + bool inclusive_cache = true; + bool support_count_mask = true; + + /* Try L3 first. */ + unsigned int level = 3; + + if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) + support_count_mask = false; + + if (shared <= 0) + { + /* Try L2 otherwise. */ + level = 2; + shared = core; + threads_l2 = 0; + threads_l3 = -1; + } + else + { + threads_l2 = 0; + threads_l3 = 0; + } + + /* A value of 0 for the HTT bit indicates there is only a single + logical processor. */ + if (HAS_CPU_FEATURE (HTT)) + { + /* Figure out the number of logical threads that share the + highest cache level. */ + if (max_cpuid >= 4) + { + int i = 0; + + /* Query until cache level 2 and 3 are enumerated. */ + int check = 0x1 | (threads_l3 == 0) << 1; + do + { + __cpuid_count (4, i++, eax, ebx, ecx, edx); + + /* There seems to be a bug in at least some Pentium Ds + which sometimes fail to iterate all cache parameters. + Do not loop indefinitely here, stop in this case and + assume there is no such information. */ + if (cpu_features->basic.kind == arch_kind_intel + && (eax & 0x1f) == 0 ) + goto intel_bug_no_cache_info; + + switch ((eax >> 5) & 0x7) + { + default: + break; + case 2: + if ((check & 0x1)) + { + /* Get maximum number of logical processors + sharing L2 cache. */ + threads_l2 = (eax >> 14) & 0x3ff; + check &= ~0x1; + } + break; + case 3: + if ((check & (0x1 << 1))) + { + /* Get maximum number of logical processors + sharing L3 cache. */ + threads_l3 = (eax >> 14) & 0x3ff; + + /* Check if L2 and L3 caches are inclusive. */ + inclusive_cache = (edx & 0x2) != 0; + check &= ~(0x1 << 1); + } + break; + } + } + while (check); + + /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum + numbers of addressable IDs for logical processors sharing + the cache, instead of the maximum number of threads + sharing the cache. */ + if (max_cpuid >= 11 && support_count_mask) + { + /* Find the number of logical processors shipped in + one core and apply count mask. */ + i = 0; + + /* Count SMT only if there is L3 cache. Always count + core if there is no L3 cache. */ + int count = ((threads_l2 > 0 && level == 3) + | ((threads_l3 > 0 + || (threads_l2 > 0 && level == 2)) << 1)); + + while (count) + { + __cpuid_count (11, i++, eax, ebx, ecx, edx); + + int shipped = ebx & 0xff; + int type = ecx & 0xff00; + if (shipped == 0 || type == 0) + break; + else if (type == 0x100) + { + /* Count SMT. */ + if ((count & 0x1)) + { + int count_mask; + + /* Compute count mask. */ + asm ("bsr %1, %0" + : "=r" (count_mask) : "g" (threads_l2)); + count_mask = ~(-1 << (count_mask + 1)); + threads_l2 = (shipped - 1) & count_mask; + count &= ~0x1; + } + } + else if (type == 0x200) + { + /* Count core. */ + if ((count & (0x1 << 1))) + { + int count_mask; + int threads_core + = (level == 2 ? threads_l2 : threads_l3); + + /* Compute count mask. */ + asm ("bsr %1, %0" + : "=r" (count_mask) : "g" (threads_core)); + count_mask = ~(-1 << (count_mask + 1)); + threads_core = (shipped - 1) & count_mask; + if (level == 2) + threads_l2 = threads_core; + else + threads_l3 = threads_core; + count &= ~(0x1 << 1); + } + } + } + } + if (threads_l2 > 0) + threads_l2 += 1; + if (threads_l3 > 0) + threads_l3 += 1; + if (level == 2) + { + if (threads_l2) + { + threads = threads_l2; + if (cpu_features->basic.kind == arch_kind_intel + && threads > 2 + && family == 6) + switch (model) + { + case 0x37: + case 0x4a: + case 0x4d: + case 0x5a: + case 0x5d: + /* Silvermont has L2 cache shared by 2 cores. */ + threads = 2; + break; + default: + break; + } + } + } + else if (threads_l3) + threads = threads_l3; + } + else + { +intel_bug_no_cache_info: + /* Assume that all logical threads share the highest cache + level. */ + threads + = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx + >> 16) & 0xff); + } + + /* Cap usage of highest cache level to the number of supported + threads. */ + if (shared > 0 && threads > 0) + shared /= threads; + } + + /* Account for non-inclusive L2 and L3 caches. */ + if (!inclusive_cache) + { + if (threads_l2 > 0) + core /= threads_l2; + shared += core; + } + + *shared_ptr = shared; + *threads_ptr = threads; +} + +static void +dl_init_cacheinfo (struct cpu_features *cpu_features) +{ + /* Find out what brand of processor. */ + unsigned int ebx; + unsigned int ecx; + unsigned int edx; + int max_cpuid_ex; + long int data = -1; + long int shared = -1; + long int core; + unsigned int threads = 0; + unsigned long int level1_icache_size = -1; + unsigned long int level1_dcache_size = -1; + unsigned long int level1_dcache_assoc = -1; + unsigned long int level1_dcache_linesize = -1; + unsigned long int level2_cache_size = -1; + unsigned long int level2_cache_assoc = -1; + unsigned long int level2_cache_linesize = -1; + unsigned long int level3_cache_size = -1; + unsigned long int level3_cache_assoc = -1; + unsigned long int level3_cache_linesize = -1; + unsigned long int level4_cache_size = -1; + + if (cpu_features->basic.kind == arch_kind_intel) + { + data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); + core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); + shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); + + level1_icache_size + = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); + level1_dcache_size = data; + level1_dcache_assoc + = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); + level1_dcache_linesize + = handle_intel (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features); + level2_cache_size = core; + level2_cache_assoc + = handle_intel (_SC_LEVEL2_CACHE_ASSOC, cpu_features); + level2_cache_linesize + = handle_intel (_SC_LEVEL2_CACHE_LINESIZE, cpu_features); + level3_cache_size = shared; + level3_cache_assoc + = handle_intel (_SC_LEVEL3_CACHE_ASSOC, cpu_features); + level3_cache_linesize + = handle_intel (_SC_LEVEL3_CACHE_LINESIZE, cpu_features); + level4_cache_size + = handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features); + + get_common_cache_info (&shared, &threads, core); + } + else if (cpu_features->basic.kind == arch_kind_zhaoxin) + { + data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); + core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); + shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); + + level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); + level1_dcache_size = data; + level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); + level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE); + level2_cache_size = core; + level2_cache_assoc = handle_zhaoxin (_SC_LEVEL2_CACHE_ASSOC); + level2_cache_linesize = handle_zhaoxin (_SC_LEVEL2_CACHE_LINESIZE); + level3_cache_size = shared; + level3_cache_assoc = handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC); + level3_cache_linesize = handle_zhaoxin (_SC_LEVEL3_CACHE_LINESIZE); + + get_common_cache_info (&shared, &threads, core); + } + else if (cpu_features->basic.kind == arch_kind_amd) + { + data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); + core = handle_amd (_SC_LEVEL2_CACHE_SIZE); + shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); + + level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); + level1_dcache_size = data; + level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); + level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); + level2_cache_size = core; + level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC); + level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE); + level3_cache_size = shared; + level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC); + level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE); + + /* Get maximum extended function. */ + __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); + + if (shared <= 0) + /* No shared L3 cache. All we have is the L2 cache. */ + shared = core; + else + { + /* Figure out the number of logical threads that share L3. */ + if (max_cpuid_ex >= 0x80000008) + { + /* Get width of APIC ID. */ + __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); + threads = 1 << ((ecx >> 12) & 0x0f); + } + + if (threads == 0 || cpu_features->basic.family >= 0x17) + { + /* If APIC ID width is not available, use logical + processor count. */ + __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); + + if ((edx & (1 << 28)) != 0) + threads = (ebx >> 16) & 0xff; + } + + /* Cap usage of highest cache level to the number of + supported threads. */ + if (threads > 0) + shared /= threads; + + /* Get shared cache per ccx for Zen architectures. */ + if (cpu_features->basic.family >= 0x17) + { + unsigned int eax; + + /* Get number of threads share the L3 cache in CCX. */ + __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); + + unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; + shared *= threads_per_ccx; + } + else + { + /* Account for exclusive L2 and L3 caches. */ + shared += core; + } + } + } + + cpu_features->level1_icache_size = level1_icache_size; + cpu_features->level1_dcache_size = level1_dcache_size; + cpu_features->level1_dcache_assoc = level1_dcache_assoc; + cpu_features->level1_dcache_linesize = level1_dcache_linesize; + cpu_features->level2_cache_size = level2_cache_size; + cpu_features->level2_cache_assoc = level2_cache_assoc; + cpu_features->level2_cache_linesize = level2_cache_linesize; + cpu_features->level3_cache_size = level3_cache_size; + cpu_features->level3_cache_assoc = level3_cache_assoc; + cpu_features->level3_cache_linesize = level3_cache_linesize; + cpu_features->level4_cache_size = level4_cache_size; + + /* The default setting for the non_temporal threshold is 3/4 of one + thread's share of the chip's cache. For most Intel and AMD processors + with an initial release date between 2017 and 2020, a thread's typical + share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 + threshold leaves 125 KBytes to 500 KBytes of the thread's data + in cache after a maximum temporal copy, which will maintain + in cache a reasonable portion of the thread's stack and other + active data. If the threshold is set higher than one thread's + share of the cache, it has a substantial risk of negatively + impacting the performance of other threads running on the chip. */ + unsigned long int non_temporal_threshold = shared * 3 / 4; + +#if HAVE_TUNABLES + /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ + unsigned int minimum_rep_movsb_threshold; +#endif + /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ + unsigned int rep_movsb_threshold; + if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) + && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) + { + rep_movsb_threshold = 2048 * (64 / 16); +#if HAVE_TUNABLES + minimum_rep_movsb_threshold = 64 * 8; +#endif + } + else if (CPU_FEATURE_PREFERRED_P (cpu_features, + AVX_Fast_Unaligned_Load)) + { + rep_movsb_threshold = 2048 * (32 / 16); +#if HAVE_TUNABLES + minimum_rep_movsb_threshold = 32 * 8; +#endif + } + else + { + rep_movsb_threshold = 2048 * (16 / 16); +#if HAVE_TUNABLES + minimum_rep_movsb_threshold = 16 * 8; +#endif + } + + /* The default threshold to use Enhanced REP STOSB. */ + unsigned long int rep_stosb_threshold = 2048; + +#if HAVE_TUNABLES + long int tunable_size; + + tunable_size = TUNABLE_GET (x86_data_cache_size, long int, NULL); + /* NB: Ignore the default value 0. */ + if (tunable_size) + data = tunable_size; + + tunable_size = TUNABLE_GET (x86_shared_cache_size, long int, NULL); + /* NB: Ignore the default value 0. */ + if (tunable_size) + shared = tunable_size; + + tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); + /* NB: Ignore the default value 0. */ + if (tunable_size) + non_temporal_threshold = tunable_size; + + tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); + if (tunable_size > minimum_rep_movsb_threshold) + rep_movsb_threshold = tunable_size; + + /* NB: The default value of the x86_rep_stosb_threshold tunable is the + same as the default value of __x86_rep_stosb_threshold and the + minimum value is fixed. */ + rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold, + long int, NULL); + + TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, long int, data, + 0, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, long int, shared, + 0, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, long int, + non_temporal_threshold, 0, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, long int, + rep_movsb_threshold, + minimum_rep_movsb_threshold, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, long int, + rep_stosb_threshold, 1, (long int) -1); +#endif + + cpu_features->data_cache_size = data; + cpu_features->shared_cache_size = shared; + cpu_features->non_temporal_threshold = non_temporal_threshold; + cpu_features->rep_movsb_threshold = rep_movsb_threshold; + cpu_features->rep_stosb_threshold = rep_stosb_threshold; +} diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index f62be0b9b3..3f3bd93320 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -153,6 +153,28 @@ struct cpu_features unsigned long int rep_movsb_threshold; /* Threshold to use "rep stosb". */ unsigned long int rep_stosb_threshold; + /* _SC_LEVEL1_ICACHE_SIZE. */ + unsigned long int level1_icache_size; + /* _SC_LEVEL1_DCACHE_SIZE. */ + unsigned long int level1_dcache_size; + /* _SC_LEVEL1_DCACHE_ASSOC. */ + unsigned long int level1_dcache_assoc; + /* _SC_LEVEL1_DCACHE_LINESIZE. */ + unsigned long int level1_dcache_linesize; + /* _SC_LEVEL2_CACHE_ASSOC. */ + unsigned long int level2_cache_size; + /* _SC_LEVEL2_DCACHE_ASSOC. */ + unsigned long int level2_cache_assoc; + /* _SC_LEVEL2_CACHE_LINESIZE. */ + unsigned long int level2_cache_linesize; + /* /_SC_LEVEL3_CACHE_SIZE. */ + unsigned long int level3_cache_size; + /* _SC_LEVEL3_CACHE_ASSOC. */ + unsigned long int level3_cache_assoc; + /* _SC_LEVEL3_CACHE_LINESIZE. */ + unsigned long int level3_cache_linesize; + /* /_SC_LEVEL4_CACHE_SIZE. */ + unsigned long int level4_cache_size; }; # if defined (_LIBC) && !IS_IN (nonlib) -- 2.28.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: V4 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features 2020-10-31 15:44 ` V4 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features H.J. Lu @ 2021-01-14 14:13 ` Adhemerval Zanella 2021-01-14 19:28 ` V5 " H.J. Lu 0 siblings, 1 reply; 12+ messages in thread From: Adhemerval Zanella @ 2021-01-14 14:13 UTC (permalink / raw) To: H.J. Lu, libc-alpha; +Cc: Florian Weimer On 31/10/2020 12:44, H.J. Lu via Libc-alpha wrote: > 1. Move x86 processor cache info to _dl_x86_cpu_features in ld.so. > 2. Update tunable bounds with TUNABLE_SET_WITH_BOUNDS. > 3. Move x86 cache info initialization to dl-cacheinfo.h and initialize > x86 cache info in init_cpu_features (). > 4. Put x86 cache info for libc in cacheinfo.h, which is included in > libc-start.c in libc.a and is included in cacheinfo.c in libc.so. Patch looks ok for 2.33 with a small nit below regarding an implicit check. I have checked with some build variations (default and static-pie) and it shows no regression. I saw that --enable-tunables=no is not building anymore, but it is due another patch. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> > --- > sysdeps/x86/cacheinfo.c | 46 ++- > sysdeps/x86/cacheinfo.h | 400 ++----------------------- > sysdeps/x86/cpu-features.c | 35 +-- > sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++++++++++ > sysdeps/x86/include/cpu-features.h | 22 ++ > 5 files changed, 551 insertions(+), 412 deletions(-) > > diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c > index 0d2fe3a2fa..e1ea4d5228 100644 > --- a/sysdeps/x86/cacheinfo.c > +++ b/sysdeps/x86/cacheinfo.c > @@ -18,11 +18,8 @@ > > #if IS_IN (libc) > > -#include <assert.h> > #include <unistd.h> > -#include <cpuid.h> > #include <ldsodefs.h> > -#include <dl-cacheinfo.h> > > /* Get the value of the system variable NAME. */ > long int > @@ -30,20 +27,45 @@ attribute_hidden > __cache_sysconf (int name) > { > const struct cpu_features *cpu_features = __get_cpu_features (); > + switch (name) > + { > + case _SC_LEVEL1_ICACHE_SIZE: > + return cpu_features->level1_icache_size; > > - if (cpu_features->basic.kind == arch_kind_intel) > - return handle_intel (name, cpu_features); > + case _SC_LEVEL1_DCACHE_SIZE: > + return cpu_features->level1_dcache_size; > > - if (cpu_features->basic.kind == arch_kind_amd) > - return handle_amd (name); > + case _SC_LEVEL1_DCACHE_ASSOC: > + return cpu_features->level1_dcache_assoc; > > - if (cpu_features->basic.kind == arch_kind_zhaoxin) > - return handle_zhaoxin (name); > + case _SC_LEVEL1_DCACHE_LINESIZE: > + return cpu_features->level1_dcache_linesize; > > - // XXX Fill in more vendors. > + case _SC_LEVEL2_CACHE_SIZE: > + return cpu_features->level2_cache_size; > > - /* CPU not known, we have no information. */ > - return 0; > + case _SC_LEVEL2_CACHE_ASSOC: > + return cpu_features->level2_cache_assoc; > + > + case _SC_LEVEL2_CACHE_LINESIZE: > + return cpu_features->level2_cache_linesize; > + > + case _SC_LEVEL3_CACHE_SIZE: > + return cpu_features->level3_cache_size; > + > + case _SC_LEVEL3_CACHE_ASSOC: > + return cpu_features->level3_cache_assoc; > + > + case _SC_LEVEL3_CACHE_LINESIZE: > + return cpu_features->level3_cache_linesize; > + > + case _SC_LEVEL4_CACHE_SIZE: > + return cpu_features->level4_cache_size; > + > + default: > + break; > + } > + return -1; > } > > # ifdef SHARED Ok, so now it handles _SC_LEVEL1_ICACHE_SIZE <= name < _SC_LEVEL4_CACHE_LINESIZE and returns -1 otherwise. It align with sysconf interface. > diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h > index 0aec0e2875..5aa40b45b5 100644 > --- a/sysdeps/x86/cacheinfo.h > +++ b/sysdeps/x86/cacheinfo.h > @@ -18,7 +18,16 @@ > > #include <assert.h> > #include <unistd.h> > +#include <cpuid.h> > +#include <cpu-features.h> > > +#if HAVE_TUNABLES > +# define TUNABLE_NAMESPACE cpu > +# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ > +# include <elf/dl-tunables.h> > +#endif > + > +#if IS_IN (libc) > /* Data cache size for use in memory and string routines, typically > L1 size, rounded to multiple of 256 bytes. */ > long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2; Ok. > @@ -45,385 +54,30 @@ long int __x86_rep_movsb_threshold attribute_hidden = 2048; > /* Threshold to use Enhanced REP STOSB. */ > long int __x86_rep_stosb_threshold attribute_hidden = 2048; > > -static void > -get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, > - long int core) > -{ > - unsigned int eax; > - unsigned int ebx; > - unsigned int ecx; > - unsigned int edx; > - > - /* Number of logical processors sharing L2 cache. */ > - int threads_l2; > - > - /* Number of logical processors sharing L3 cache. */ > - int threads_l3; > - > - const struct cpu_features *cpu_features = __get_cpu_features (); > - int max_cpuid = cpu_features->basic.max_cpuid; > - unsigned int family = cpu_features->basic.family; > - unsigned int model = cpu_features->basic.model; > - long int shared = *shared_ptr; > - unsigned int threads = *threads_ptr; > - bool inclusive_cache = true; > - bool support_count_mask = true; > - > - /* Try L3 first. */ > - unsigned int level = 3; > - > - if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) > - support_count_mask = false; > - > - if (shared <= 0) > - { > - /* Try L2 otherwise. */ > - level = 2; > - shared = core; > - threads_l2 = 0; > - threads_l3 = -1; > - } > - else > - { > - threads_l2 = 0; > - threads_l3 = 0; > - } > - > - /* A value of 0 for the HTT bit indicates there is only a single > - logical processor. */ > - if (HAS_CPU_FEATURE (HTT)) > - { > - /* Figure out the number of logical threads that share the > - highest cache level. */ > - if (max_cpuid >= 4) > - { > - int i = 0; > - > - /* Query until cache level 2 and 3 are enumerated. */ > - int check = 0x1 | (threads_l3 == 0) << 1; > - do > - { > - __cpuid_count (4, i++, eax, ebx, ecx, edx); > - > - /* There seems to be a bug in at least some Pentium Ds > - which sometimes fail to iterate all cache parameters. > - Do not loop indefinitely here, stop in this case and > - assume there is no such information. */ > - if (cpu_features->basic.kind == arch_kind_intel > - && (eax & 0x1f) == 0 ) > - goto intel_bug_no_cache_info; > - > - switch ((eax >> 5) & 0x7) > - { > - default: > - break; > - case 2: > - if ((check & 0x1)) > - { > - /* Get maximum number of logical processors > - sharing L2 cache. */ > - threads_l2 = (eax >> 14) & 0x3ff; > - check &= ~0x1; > - } > - break; > - case 3: > - if ((check & (0x1 << 1))) > - { > - /* Get maximum number of logical processors > - sharing L3 cache. */ > - threads_l3 = (eax >> 14) & 0x3ff; > - > - /* Check if L2 and L3 caches are inclusive. */ > - inclusive_cache = (edx & 0x2) != 0; > - check &= ~(0x1 << 1); > - } > - break; > - } > - } > - while (check); > - > - /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum > - numbers of addressable IDs for logical processors sharing > - the cache, instead of the maximum number of threads > - sharing the cache. */ > - if (max_cpuid >= 11 && support_count_mask) > - { > - /* Find the number of logical processors shipped in > - one core and apply count mask. */ > - i = 0; > - > - /* Count SMT only if there is L3 cache. Always count > - core if there is no L3 cache. */ > - int count = ((threads_l2 > 0 && level == 3) > - | ((threads_l3 > 0 > - || (threads_l2 > 0 && level == 2)) << 1)); > - > - while (count) > - { > - __cpuid_count (11, i++, eax, ebx, ecx, edx); > - > - int shipped = ebx & 0xff; > - int type = ecx & 0xff00; > - if (shipped == 0 || type == 0) > - break; > - else if (type == 0x100) > - { > - /* Count SMT. */ > - if ((count & 0x1)) > - { > - int count_mask; > - > - /* Compute count mask. */ > - asm ("bsr %1, %0" > - : "=r" (count_mask) : "g" (threads_l2)); > - count_mask = ~(-1 << (count_mask + 1)); > - threads_l2 = (shipped - 1) & count_mask; > - count &= ~0x1; > - } > - } > - else if (type == 0x200) > - { > - /* Count core. */ > - if ((count & (0x1 << 1))) > - { > - int count_mask; > - int threads_core > - = (level == 2 ? threads_l2 : threads_l3); > - > - /* Compute count mask. */ > - asm ("bsr %1, %0" > - : "=r" (count_mask) : "g" (threads_core)); > - count_mask = ~(-1 << (count_mask + 1)); > - threads_core = (shipped - 1) & count_mask; > - if (level == 2) > - threads_l2 = threads_core; > - else > - threads_l3 = threads_core; > - count &= ~(0x1 << 1); > - } > - } > - } > - } > - if (threads_l2 > 0) > - threads_l2 += 1; > - if (threads_l3 > 0) > - threads_l3 += 1; > - if (level == 2) > - { > - if (threads_l2) > - { > - threads = threads_l2; > - if (cpu_features->basic.kind == arch_kind_intel > - && threads > 2 > - && family == 6) > - switch (model) > - { > - case 0x37: > - case 0x4a: > - case 0x4d: > - case 0x5a: > - case 0x5d: > - /* Silvermont has L2 cache shared by 2 cores. */ > - threads = 2; > - break; > - default: > - break; > - } > - } > - } > - else if (threads_l3) > - threads = threads_l3; > - } > - else > - { > -intel_bug_no_cache_info: > - /* Assume that all logical threads share the highest cache > - level. */ > - threads > - = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx > - >> 16) & 0xff); > - } > - > - /* Cap usage of highest cache level to the number of supported > - threads. */ > - if (shared > 0 && threads > 0) > - shared /= threads; > - } > - > - /* Account for non-inclusive L2 and L3 caches. */ > - if (!inclusive_cache) > - { > - if (threads_l2 > 0) > - core /= threads_l2; > - shared += core; > - } > - > - *shared_ptr = shared; > - *threads_ptr = threads; > -} > - > static void > init_cacheinfo (void) > { > - /* Find out what brand of processor. */ > - unsigned int ebx; > - unsigned int ecx; > - unsigned int edx; > - int max_cpuid_ex; > - long int data = -1; > - long int shared = -1; > - long int core; > - unsigned int threads = 0; > const struct cpu_features *cpu_features = __get_cpu_features (); > + long int data = cpu_features->data_cache_size; > + __x86_raw_data_cache_size_half = data / 2; > + __x86_raw_data_cache_size = data; > + /* Round data cache size to multiple of 256 bytes. */ > + data = data & ~255L; > + __x86_data_cache_size_half = data / 2; > + __x86_data_cache_size = data; > + > + long int shared = cpu_features->shared_cache_size; > + __x86_raw_shared_cache_size_half = shared / 2; > + __x86_raw_shared_cache_size = shared; > + /* Round shared cache size to multiple of 256 bytes. */ > + shared = shared & ~255L; > + __x86_shared_cache_size_half = shared / 2; > + __x86_shared_cache_size = shared; > > - /* NB: In libc.so, cpu_features is defined in ld.so and is initialized > - by DL_PLATFORM_INIT or IFUNC relocation before init_cacheinfo is > - called by IFUNC relocation. In libc.a, init_cacheinfo is called > - from init_cpu_features by ARCH_INIT_CPU_FEATURES. */ > - assert (cpu_features->basic.kind != arch_kind_unknown); > - > - if (cpu_features->basic.kind == arch_kind_intel) > - { > - data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > - core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > - shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > - > - get_common_cache_info (&shared, &threads, core); > - } > - else if (cpu_features->basic.kind == arch_kind_zhaoxin) > - { > - data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); > - core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); > - shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > - > - get_common_cache_info (&shared, &threads, core); > - } > - else if (cpu_features->basic.kind == arch_kind_amd) > - { > - data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); > - long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE); > - shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); > - > - /* Get maximum extended function. */ > - __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); > - > - if (shared <= 0) > - /* No shared L3 cache. All we have is the L2 cache. */ > - shared = core; > - else > - { > - /* Figure out the number of logical threads that share L3. */ > - if (max_cpuid_ex >= 0x80000008) > - { > - /* Get width of APIC ID. */ > - __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); > - threads = 1 << ((ecx >> 12) & 0x0f); > - } > - > - if (threads == 0 || cpu_features->basic.family >= 0x17) > - { > - /* If APIC ID width is not available, use logical > - processor count. */ > - __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); > - > - if ((edx & (1 << 28)) != 0) > - threads = (ebx >> 16) & 0xff; > - } > - > - /* Cap usage of highest cache level to the number of > - supported threads. */ > - if (threads > 0) > - shared /= threads; > - > - /* Get shared cache per ccx for Zen architectures. */ > - if (cpu_features->basic.family >= 0x17) > - { > - unsigned int eax; > - > - /* Get number of threads share the L3 cache in CCX. */ > - __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); > - > - unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; > - shared *= threads_per_ccx; > - } > - else > - { > - /* Account for exclusive L2 and L3 caches. */ > - shared += core; > - } > - } > - } > - > - /* Prefer cache size configure via tuning. */ > - if (cpu_features->data_cache_size != 0) > - data = cpu_features->data_cache_size; > - > - if (data > 0) > - { > - __x86_raw_data_cache_size_half = data / 2; > - __x86_raw_data_cache_size = data; > - /* Round data cache size to multiple of 256 bytes. */ > - data = data & ~255L; > - __x86_data_cache_size_half = data / 2; > - __x86_data_cache_size = data; > - } > - > - /* Prefer cache size configure via tuning. */ > - if (cpu_features->shared_cache_size != 0) > - shared = cpu_features->shared_cache_size; > - > - if (shared > 0) > - { > - __x86_raw_shared_cache_size_half = shared / 2; > - __x86_raw_shared_cache_size = shared; > - /* Round shared cache size to multiple of 256 bytes. */ > - shared = shared & ~255L; > - __x86_shared_cache_size_half = shared / 2; > - __x86_shared_cache_size = shared; > - } > - > - /* The default setting for the non_temporal threshold is 3/4 of one > - thread's share of the chip's cache. For most Intel and AMD processors > - with an initial release date between 2017 and 2020, a thread's typical > - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 > - threshold leaves 125 KBytes to 500 KBytes of the thread's data > - in cache after a maximum temporal copy, which will maintain > - in cache a reasonable portion of the thread's stack and other > - active data. If the threshold is set higher than one thread's > - share of the cache, it has a substantial risk of negatively > - impacting the performance of other threads running on the chip. */ > __x86_shared_non_temporal_threshold > - = (cpu_features->non_temporal_threshold != 0 > - ? cpu_features->non_temporal_threshold > - : __x86_shared_cache_size * 3 / 4); > - > - /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ > - unsigned int minimum_rep_movsb_threshold; > - /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ > - unsigned int rep_movsb_threshold; > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) > - && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) > - { > - rep_movsb_threshold = 2048 * (64 / 16); > - minimum_rep_movsb_threshold = 64 * 8; > - } > - else if (CPU_FEATURE_PREFERRED_P (cpu_features, > - AVX_Fast_Unaligned_Load)) > - { > - rep_movsb_threshold = 2048 * (32 / 16); > - minimum_rep_movsb_threshold = 32 * 8; > - } > - else > - { > - rep_movsb_threshold = 2048 * (16 / 16); > - minimum_rep_movsb_threshold = 16 * 8; > - } > - if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold) > - __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; > - else > - __x86_rep_movsb_threshold = rep_movsb_threshold; > + = cpu_features->non_temporal_threshold; > > -# if HAVE_TUNABLES > + __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; > __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; > -# endif > } > +#endif Ok, it is refactoring the code. > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > index f26deba38d..51c12d89ca 100644 > --- a/sysdeps/x86/cpu-features.c > +++ b/sysdeps/x86/cpu-features.c > @@ -16,21 +16,12 @@ > License along with the GNU C Library; if not, see > <https://www.gnu.org/licenses/>. */ > > -#include <cpuid.h> > #include <dl-hwcap.h> > #include <libc-pointer-arith.h> > -#if IS_IN (libc) && !defined SHARED > -# include <assert.h> > -# include <unistd.h> > -# include <dl-cacheinfo.h> > -# include <cacheinfo.h> > -#endif > +#include <cacheinfo.h> > +#include <dl-cacheinfo.h> > > #if HAVE_TUNABLES > -# define TUNABLE_NAMESPACE cpu > -# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ > -# include <elf/dl-tunables.h> > - > extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *) > attribute_hidden; > Ok. > @@ -642,24 +633,14 @@ no_cpuid: > cpu_features->basic.model = model; > cpu_features->basic.stepping = stepping; > > + dl_init_cacheinfo (cpu_features); > + > #if HAVE_TUNABLES > TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps)); > - cpu_features->non_temporal_threshold > - = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); > - cpu_features->rep_movsb_threshold > - = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); > - cpu_features->rep_stosb_threshold > - = TUNABLE_GET (x86_rep_stosb_threshold, long int, NULL); > - cpu_features->data_cache_size > - = TUNABLE_GET (x86_data_cache_size, long int, NULL); > - cpu_features->shared_cache_size > - = TUNABLE_GET (x86_shared_cache_size, long int, NULL); > -#endif > - > - /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */ > -#if !HAVE_TUNABLES && defined SHARED > - /* The glibc.cpu.hwcap_mask tunable is initialized already, so no need to do > - this. */ > +#elif defined SHARED > + /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. The > + glibc.cpu.hwcap_mask tunable is initialized already, so no > + need to do this. */ > GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT; > #endif > Ok. > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > index b2b90074b0..9632ee7818 100644 > --- a/sysdeps/x86/dl-cacheinfo.h > +++ b/sysdeps/x86/dl-cacheinfo.h > @@ -476,3 +476,463 @@ handle_zhaoxin (int name) > /* Nothing found. */ > return 0; > } > + > +static void > +get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, > + long int core) > +{ > + unsigned int eax; > + unsigned int ebx; > + unsigned int ecx; > + unsigned int edx; > + > + /* Number of logical processors sharing L2 cache. */ > + int threads_l2; > + > + /* Number of logical processors sharing L3 cache. */ > + int threads_l3; > + > + const struct cpu_features *cpu_features = __get_cpu_features (); > + int max_cpuid = cpu_features->basic.max_cpuid; > + unsigned int family = cpu_features->basic.family; > + unsigned int model = cpu_features->basic.model; > + long int shared = *shared_ptr; > + unsigned int threads = *threads_ptr; > + bool inclusive_cache = true; > + bool support_count_mask = true; > + > + /* Try L3 first. */ > + unsigned int level = 3; > + > + if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) > + support_count_mask = false; > + > + if (shared <= 0) > + { > + /* Try L2 otherwise. */ > + level = 2; > + shared = core; > + threads_l2 = 0; > + threads_l3 = -1; > + } > + else > + { > + threads_l2 = 0; > + threads_l3 = 0; > + } > + > + /* A value of 0 for the HTT bit indicates there is only a single > + logical processor. */ > + if (HAS_CPU_FEATURE (HTT)) > + { > + /* Figure out the number of logical threads that share the > + highest cache level. */ > + if (max_cpuid >= 4) > + { > + int i = 0; > + > + /* Query until cache level 2 and 3 are enumerated. */ > + int check = 0x1 | (threads_l3 == 0) << 1; > + do > + { > + __cpuid_count (4, i++, eax, ebx, ecx, edx); > + > + /* There seems to be a bug in at least some Pentium Ds > + which sometimes fail to iterate all cache parameters. > + Do not loop indefinitely here, stop in this case and > + assume there is no such information. */ > + if (cpu_features->basic.kind == arch_kind_intel > + && (eax & 0x1f) == 0 ) > + goto intel_bug_no_cache_info; > + > + switch ((eax >> 5) & 0x7) > + { > + default: > + break; > + case 2: > + if ((check & 0x1)) > + { > + /* Get maximum number of logical processors > + sharing L2 cache. */ > + threads_l2 = (eax >> 14) & 0x3ff; > + check &= ~0x1; > + } > + break; > + case 3: > + if ((check & (0x1 << 1))) > + { > + /* Get maximum number of logical processors > + sharing L3 cache. */ > + threads_l3 = (eax >> 14) & 0x3ff; > + > + /* Check if L2 and L3 caches are inclusive. */ > + inclusive_cache = (edx & 0x2) != 0; > + check &= ~(0x1 << 1); > + } > + break; > + } > + } > + while (check); > + > + /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum > + numbers of addressable IDs for logical processors sharing > + the cache, instead of the maximum number of threads > + sharing the cache. */ > + if (max_cpuid >= 11 && support_count_mask) > + { > + /* Find the number of logical processors shipped in > + one core and apply count mask. */ > + i = 0; > + > + /* Count SMT only if there is L3 cache. Always count > + core if there is no L3 cache. */ > + int count = ((threads_l2 > 0 && level == 3) > + | ((threads_l3 > 0 > + || (threads_l2 > 0 && level == 2)) << 1)); > + > + while (count) > + { > + __cpuid_count (11, i++, eax, ebx, ecx, edx); > + > + int shipped = ebx & 0xff; > + int type = ecx & 0xff00; > + if (shipped == 0 || type == 0) > + break; > + else if (type == 0x100) > + { > + /* Count SMT. */ > + if ((count & 0x1)) > + { > + int count_mask; > + > + /* Compute count mask. */ > + asm ("bsr %1, %0" > + : "=r" (count_mask) : "g" (threads_l2)); > + count_mask = ~(-1 << (count_mask + 1)); > + threads_l2 = (shipped - 1) & count_mask; > + count &= ~0x1; > + } > + } > + else if (type == 0x200) > + { > + /* Count core. */ > + if ((count & (0x1 << 1))) > + { > + int count_mask; > + int threads_core > + = (level == 2 ? threads_l2 : threads_l3); > + > + /* Compute count mask. */ > + asm ("bsr %1, %0" > + : "=r" (count_mask) : "g" (threads_core)); > + count_mask = ~(-1 << (count_mask + 1)); > + threads_core = (shipped - 1) & count_mask; > + if (level == 2) > + threads_l2 = threads_core; > + else > + threads_l3 = threads_core; > + count &= ~(0x1 << 1); > + } > + } > + } > + } > + if (threads_l2 > 0) > + threads_l2 += 1; > + if (threads_l3 > 0) > + threads_l3 += 1; > + if (level == 2) > + { > + if (threads_l2) > + { > + threads = threads_l2; > + if (cpu_features->basic.kind == arch_kind_intel > + && threads > 2 > + && family == 6) > + switch (model) > + { > + case 0x37: > + case 0x4a: > + case 0x4d: > + case 0x5a: > + case 0x5d: > + /* Silvermont has L2 cache shared by 2 cores. */ > + threads = 2; > + break; > + default: > + break; > + } > + } > + } > + else if (threads_l3) > + threads = threads_l3; > + } > + else > + { > +intel_bug_no_cache_info: > + /* Assume that all logical threads share the highest cache > + level. */ > + threads > + = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx > + >> 16) & 0xff); > + } > + > + /* Cap usage of highest cache level to the number of supported > + threads. */ > + if (shared > 0 && threads > 0) > + shared /= threads; > + } > + > + /* Account for non-inclusive L2 and L3 caches. */ > + if (!inclusive_cache) > + { > + if (threads_l2 > 0) > + core /= threads_l2; > + shared += core; > + } > + > + *shared_ptr = shared; > + *threads_ptr = threads; > +} > + Ok, so this is function moved from sysdeps/x86/cacheinfo.h. > +static void > +dl_init_cacheinfo (struct cpu_features *cpu_features) > +{ > + /* Find out what brand of processor. */ > + unsigned int ebx; > + unsigned int ecx; > + unsigned int edx; > + int max_cpuid_ex; > + long int data = -1; > + long int shared = -1; > + long int core; > + unsigned int threads = 0; > + unsigned long int level1_icache_size = -1; > + unsigned long int level1_dcache_size = -1; > + unsigned long int level1_dcache_assoc = -1; > + unsigned long int level1_dcache_linesize = -1; > + unsigned long int level2_cache_size = -1; > + unsigned long int level2_cache_assoc = -1; > + unsigned long int level2_cache_linesize = -1; > + unsigned long int level3_cache_size = -1; > + unsigned long int level3_cache_assoc = -1; > + unsigned long int level3_cache_linesize = -1; > + unsigned long int level4_cache_size = -1; > + > + if (cpu_features->basic.kind == arch_kind_intel) > + { > + data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > + core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > + shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > + > + level1_icache_size > + = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); > + level1_dcache_size = data; > + level1_dcache_assoc > + = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); > + level1_dcache_linesize > + = handle_intel (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features); > + level2_cache_size = core; > + level2_cache_assoc > + = handle_intel (_SC_LEVEL2_CACHE_ASSOC, cpu_features); > + level2_cache_linesize > + = handle_intel (_SC_LEVEL2_CACHE_LINESIZE, cpu_features); > + level3_cache_size = shared; > + level3_cache_assoc > + = handle_intel (_SC_LEVEL3_CACHE_ASSOC, cpu_features); > + level3_cache_linesize > + = handle_intel (_SC_LEVEL3_CACHE_LINESIZE, cpu_features); > + level4_cache_size > + = handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features); > + > + get_common_cache_info (&shared, &threads, core); > + } > + else if (cpu_features->basic.kind == arch_kind_zhaoxin) > + { > + data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); > + core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); > + shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > + > + level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); > + level1_dcache_size = data; > + level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); > + level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE); > + level2_cache_size = core; > + level2_cache_assoc = handle_zhaoxin (_SC_LEVEL2_CACHE_ASSOC); > + level2_cache_linesize = handle_zhaoxin (_SC_LEVEL2_CACHE_LINESIZE); > + level3_cache_size = shared; > + level3_cache_assoc = handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC); > + level3_cache_linesize = handle_zhaoxin (_SC_LEVEL3_CACHE_LINESIZE); > + > + get_common_cache_info (&shared, &threads, core); > + } > + else if (cpu_features->basic.kind == arch_kind_amd) > + { > + data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); > + core = handle_amd (_SC_LEVEL2_CACHE_SIZE); > + shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); > + > + level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); > + level1_dcache_size = data; > + level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); > + level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); > + level2_cache_size = core; > + level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC); > + level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE); > + level3_cache_size = shared; > + level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC); > + level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE); > + > + /* Get maximum extended function. */ > + __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); > + > + if (shared <= 0) > + /* No shared L3 cache. All we have is the L2 cache. */ > + shared = core; > + else > + { > + /* Figure out the number of logical threads that share L3. */ > + if (max_cpuid_ex >= 0x80000008) > + { > + /* Get width of APIC ID. */ > + __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); > + threads = 1 << ((ecx >> 12) & 0x0f); > + } > + > + if (threads == 0 || cpu_features->basic.family >= 0x17) > + { > + /* If APIC ID width is not available, use logical > + processor count. */ > + __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); > + > + if ((edx & (1 << 28)) != 0) > + threads = (ebx >> 16) & 0xff; > + } > + > + /* Cap usage of highest cache level to the number of > + supported threads. */ > + if (threads > 0) > + shared /= threads; > + > + /* Get shared cache per ccx for Zen architectures. */ > + if (cpu_features->basic.family >= 0x17) > + { > + unsigned int eax; > + > + /* Get number of threads share the L3 cache in CCX. */ > + __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); > + > + unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; > + shared *= threads_per_ccx; > + } > + else > + { > + /* Account for exclusive L2 and L3 caches. */ > + shared += core; > + } > + } > + } > + > + cpu_features->level1_icache_size = level1_icache_size; > + cpu_features->level1_dcache_size = level1_dcache_size; > + cpu_features->level1_dcache_assoc = level1_dcache_assoc; > + cpu_features->level1_dcache_linesize = level1_dcache_linesize; > + cpu_features->level2_cache_size = level2_cache_size; > + cpu_features->level2_cache_assoc = level2_cache_assoc; > + cpu_features->level2_cache_linesize = level2_cache_linesize; > + cpu_features->level3_cache_size = level3_cache_size; > + cpu_features->level3_cache_assoc = level3_cache_assoc; > + cpu_features->level3_cache_linesize = level3_cache_linesize; > + cpu_features->level4_cache_size = level4_cache_size; Ok, so you are expanding the definitions by family. > + > + /* The default setting for the non_temporal threshold is 3/4 of one > + thread's share of the chip's cache. For most Intel and AMD processors > + with an initial release date between 2017 and 2020, a thread's typical > + share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 > + threshold leaves 125 KBytes to 500 KBytes of the thread's data > + in cache after a maximum temporal copy, which will maintain > + in cache a reasonable portion of the thread's stack and other > + active data. If the threshold is set higher than one thread's > + share of the cache, it has a substantial risk of negatively > + impacting the performance of other threads running on the chip. */ > + unsigned long int non_temporal_threshold = shared * 3 / 4; > + > +#if HAVE_TUNABLES > + /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ > + unsigned int minimum_rep_movsb_threshold; > +#endif > + /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ > + unsigned int rep_movsb_threshold; > + if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) > + && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) > + { > + rep_movsb_threshold = 2048 * (64 / 16); > +#if HAVE_TUNABLES > + minimum_rep_movsb_threshold = 64 * 8; > +#endif > + } > + else if (CPU_FEATURE_PREFERRED_P (cpu_features, > + AVX_Fast_Unaligned_Load)) > + { > + rep_movsb_threshold = 2048 * (32 / 16); > +#if HAVE_TUNABLES > + minimum_rep_movsb_threshold = 32 * 8; > +#endif > + } > + else > + { > + rep_movsb_threshold = 2048 * (16 / 16); > +#if HAVE_TUNABLES > + minimum_rep_movsb_threshold = 16 * 8; > +#endif > + } > + > + /* The default threshold to use Enhanced REP STOSB. */ > + unsigned long int rep_stosb_threshold = 2048; > + Ok. > +#if HAVE_TUNABLES > + long int tunable_size; > + > + tunable_size = TUNABLE_GET (x86_data_cache_size, long int, NULL); > + /* NB: Ignore the default value 0. */ > + if (tunable_size) No implicit checks, same as the others below. > + data = tunable_size; > + > + tunable_size = TUNABLE_GET (x86_shared_cache_size, long int, NULL); > + /* NB: Ignore the default value 0. */ > + if (tunable_size) > + shared = tunable_size; > + > + tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); > + /* NB: Ignore the default value 0. */ > + if (tunable_size) > + non_temporal_threshold = tunable_size; > + > + tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); > + if (tunable_size > minimum_rep_movsb_threshold) > + rep_movsb_threshold = tunable_size; > + > + /* NB: The default value of the x86_rep_stosb_threshold tunable is the > + same as the default value of __x86_rep_stosb_threshold and the > + minimum value is fixed. */ > + rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold, > + long int, NULL); > + > + TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, long int, data, > + 0, (long int) -1); > + TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, long int, shared, > + 0, (long int) -1); > + TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, long int, > + non_temporal_threshold, 0, (long int) -1); > + TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, long int, > + rep_movsb_threshold, > + minimum_rep_movsb_threshold, (long int) -1); > + TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, long int, > + rep_stosb_threshold, 1, (long int) -1); > +#endif Ok. Are the bounds ok for the architecture? > + > + cpu_features->data_cache_size = data; > + cpu_features->shared_cache_size = shared; > + cpu_features->non_temporal_threshold = non_temporal_threshold; > + cpu_features->rep_movsb_threshold = rep_movsb_threshold; > + cpu_features->rep_stosb_threshold = rep_stosb_threshold; > +} Ok. > diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h > index f62be0b9b3..3f3bd93320 100644 > --- a/sysdeps/x86/include/cpu-features.h > +++ b/sysdeps/x86/include/cpu-features.h > @@ -153,6 +153,28 @@ struct cpu_features > unsigned long int rep_movsb_threshold; > /* Threshold to use "rep stosb". */ > unsigned long int rep_stosb_threshold; > + /* _SC_LEVEL1_ICACHE_SIZE. */ > + unsigned long int level1_icache_size; > + /* _SC_LEVEL1_DCACHE_SIZE. */ > + unsigned long int level1_dcache_size; > + /* _SC_LEVEL1_DCACHE_ASSOC. */ > + unsigned long int level1_dcache_assoc; > + /* _SC_LEVEL1_DCACHE_LINESIZE. */ > + unsigned long int level1_dcache_linesize; > + /* _SC_LEVEL2_CACHE_ASSOC. */ > + unsigned long int level2_cache_size; > + /* _SC_LEVEL2_DCACHE_ASSOC. */ > + unsigned long int level2_cache_assoc; > + /* _SC_LEVEL2_CACHE_LINESIZE. */ > + unsigned long int level2_cache_linesize; > + /* /_SC_LEVEL3_CACHE_SIZE. */ > + unsigned long int level3_cache_size; > + /* _SC_LEVEL3_CACHE_ASSOC. */ > + unsigned long int level3_cache_assoc; > + /* _SC_LEVEL3_CACHE_LINESIZE. */ > + unsigned long int level3_cache_linesize; > + /* /_SC_LEVEL4_CACHE_SIZE. */ > + unsigned long int level4_cache_size; > }; > > # if defined (_LIBC) && !IS_IN (nonlib) > Ok. ^ permalink raw reply [flat|nested] 12+ messages in thread
* V5 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features 2021-01-14 14:13 ` Adhemerval Zanella @ 2021-01-14 19:28 ` H.J. Lu 0 siblings, 0 replies; 12+ messages in thread From: H.J. Lu @ 2021-01-14 19:28 UTC (permalink / raw) To: Adhemerval Zanella; +Cc: GNU C Library, Florian Weimer [-- Attachment #1: Type: text/plain, Size: 43434 bytes --] On Thu, Jan 14, 2021 at 6:13 AM Adhemerval Zanella <adhemerval.zanella@linaro.org> wrote: > > > > On 31/10/2020 12:44, H.J. Lu via Libc-alpha wrote: > > 1. Move x86 processor cache info to _dl_x86_cpu_features in ld.so. > > 2. Update tunable bounds with TUNABLE_SET_WITH_BOUNDS. > > 3. Move x86 cache info initialization to dl-cacheinfo.h and initialize > > x86 cache info in init_cpu_features (). > > 4. Put x86 cache info for libc in cacheinfo.h, which is included in > > libc-start.c in libc.a and is included in cacheinfo.c in libc.so. > > Patch looks ok for 2.33 with a small nit below regarding an implicit check. > > I have checked with some build variations (default and static-pie) > and it shows no regression. I saw that --enable-tunables=no is not > building anymore, but it is due another patch. > > Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> > > > --- > > sysdeps/x86/cacheinfo.c | 46 ++- > > sysdeps/x86/cacheinfo.h | 400 ++----------------------- > > sysdeps/x86/cpu-features.c | 35 +-- > > sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++++++++++ > > sysdeps/x86/include/cpu-features.h | 22 ++ > > 5 files changed, 551 insertions(+), 412 deletions(-) > > > > diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c > > index 0d2fe3a2fa..e1ea4d5228 100644 > > --- a/sysdeps/x86/cacheinfo.c > > +++ b/sysdeps/x86/cacheinfo.c > > @@ -18,11 +18,8 @@ > > > > #if IS_IN (libc) > > > > -#include <assert.h> > > #include <unistd.h> > > -#include <cpuid.h> > > #include <ldsodefs.h> > > -#include <dl-cacheinfo.h> > > > > /* Get the value of the system variable NAME. */ > > long int > > @@ -30,20 +27,45 @@ attribute_hidden > > __cache_sysconf (int name) > > { > > const struct cpu_features *cpu_features = __get_cpu_features (); > > + switch (name) > > + { > > + case _SC_LEVEL1_ICACHE_SIZE: > > + return cpu_features->level1_icache_size; > > > > - if (cpu_features->basic.kind == arch_kind_intel) > > - return handle_intel (name, cpu_features); > > + case _SC_LEVEL1_DCACHE_SIZE: > > + return cpu_features->level1_dcache_size; > > > > - if (cpu_features->basic.kind == arch_kind_amd) > > - return handle_amd (name); > > + case _SC_LEVEL1_DCACHE_ASSOC: > > + return cpu_features->level1_dcache_assoc; > > > > - if (cpu_features->basic.kind == arch_kind_zhaoxin) > > - return handle_zhaoxin (name); > > + case _SC_LEVEL1_DCACHE_LINESIZE: > > + return cpu_features->level1_dcache_linesize; > > > > - // XXX Fill in more vendors. > > + case _SC_LEVEL2_CACHE_SIZE: > > + return cpu_features->level2_cache_size; > > > > - /* CPU not known, we have no information. */ > > - return 0; > > + case _SC_LEVEL2_CACHE_ASSOC: > > + return cpu_features->level2_cache_assoc; > > + > > + case _SC_LEVEL2_CACHE_LINESIZE: > > + return cpu_features->level2_cache_linesize; > > + > > + case _SC_LEVEL3_CACHE_SIZE: > > + return cpu_features->level3_cache_size; > > + > > + case _SC_LEVEL3_CACHE_ASSOC: > > + return cpu_features->level3_cache_assoc; > > + > > + case _SC_LEVEL3_CACHE_LINESIZE: > > + return cpu_features->level3_cache_linesize; > > + > > + case _SC_LEVEL4_CACHE_SIZE: > > + return cpu_features->level4_cache_size; > > + > > + default: > > + break; > > + } > > + return -1; > > } > > > > # ifdef SHARED > > Ok, so now it handles _SC_LEVEL1_ICACHE_SIZE <= name < _SC_LEVEL4_CACHE_LINESIZE > and returns -1 otherwise. It align with sysconf interface. > > > diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h > > index 0aec0e2875..5aa40b45b5 100644 > > --- a/sysdeps/x86/cacheinfo.h > > +++ b/sysdeps/x86/cacheinfo.h > > @@ -18,7 +18,16 @@ > > > > #include <assert.h> > > #include <unistd.h> > > +#include <cpuid.h> > > +#include <cpu-features.h> > > > > +#if HAVE_TUNABLES > > +# define TUNABLE_NAMESPACE cpu > > +# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ > > +# include <elf/dl-tunables.h> > > +#endif > > + > > +#if IS_IN (libc) > > /* Data cache size for use in memory and string routines, typically > > L1 size, rounded to multiple of 256 bytes. */ > > long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2; > > Ok. > > > @@ -45,385 +54,30 @@ long int __x86_rep_movsb_threshold attribute_hidden = 2048; > > /* Threshold to use Enhanced REP STOSB. */ > > long int __x86_rep_stosb_threshold attribute_hidden = 2048; > > > > -static void > > -get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, > > - long int core) > > -{ > > - unsigned int eax; > > - unsigned int ebx; > > - unsigned int ecx; > > - unsigned int edx; > > - > > - /* Number of logical processors sharing L2 cache. */ > > - int threads_l2; > > - > > - /* Number of logical processors sharing L3 cache. */ > > - int threads_l3; > > - > > - const struct cpu_features *cpu_features = __get_cpu_features (); > > - int max_cpuid = cpu_features->basic.max_cpuid; > > - unsigned int family = cpu_features->basic.family; > > - unsigned int model = cpu_features->basic.model; > > - long int shared = *shared_ptr; > > - unsigned int threads = *threads_ptr; > > - bool inclusive_cache = true; > > - bool support_count_mask = true; > > - > > - /* Try L3 first. */ > > - unsigned int level = 3; > > - > > - if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) > > - support_count_mask = false; > > - > > - if (shared <= 0) > > - { > > - /* Try L2 otherwise. */ > > - level = 2; > > - shared = core; > > - threads_l2 = 0; > > - threads_l3 = -1; > > - } > > - else > > - { > > - threads_l2 = 0; > > - threads_l3 = 0; > > - } > > - > > - /* A value of 0 for the HTT bit indicates there is only a single > > - logical processor. */ > > - if (HAS_CPU_FEATURE (HTT)) > > - { > > - /* Figure out the number of logical threads that share the > > - highest cache level. */ > > - if (max_cpuid >= 4) > > - { > > - int i = 0; > > - > > - /* Query until cache level 2 and 3 are enumerated. */ > > - int check = 0x1 | (threads_l3 == 0) << 1; > > - do > > - { > > - __cpuid_count (4, i++, eax, ebx, ecx, edx); > > - > > - /* There seems to be a bug in at least some Pentium Ds > > - which sometimes fail to iterate all cache parameters. > > - Do not loop indefinitely here, stop in this case and > > - assume there is no such information. */ > > - if (cpu_features->basic.kind == arch_kind_intel > > - && (eax & 0x1f) == 0 ) > > - goto intel_bug_no_cache_info; > > - > > - switch ((eax >> 5) & 0x7) > > - { > > - default: > > - break; > > - case 2: > > - if ((check & 0x1)) > > - { > > - /* Get maximum number of logical processors > > - sharing L2 cache. */ > > - threads_l2 = (eax >> 14) & 0x3ff; > > - check &= ~0x1; > > - } > > - break; > > - case 3: > > - if ((check & (0x1 << 1))) > > - { > > - /* Get maximum number of logical processors > > - sharing L3 cache. */ > > - threads_l3 = (eax >> 14) & 0x3ff; > > - > > - /* Check if L2 and L3 caches are inclusive. */ > > - inclusive_cache = (edx & 0x2) != 0; > > - check &= ~(0x1 << 1); > > - } > > - break; > > - } > > - } > > - while (check); > > - > > - /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum > > - numbers of addressable IDs for logical processors sharing > > - the cache, instead of the maximum number of threads > > - sharing the cache. */ > > - if (max_cpuid >= 11 && support_count_mask) > > - { > > - /* Find the number of logical processors shipped in > > - one core and apply count mask. */ > > - i = 0; > > - > > - /* Count SMT only if there is L3 cache. Always count > > - core if there is no L3 cache. */ > > - int count = ((threads_l2 > 0 && level == 3) > > - | ((threads_l3 > 0 > > - || (threads_l2 > 0 && level == 2)) << 1)); > > - > > - while (count) > > - { > > - __cpuid_count (11, i++, eax, ebx, ecx, edx); > > - > > - int shipped = ebx & 0xff; > > - int type = ecx & 0xff00; > > - if (shipped == 0 || type == 0) > > - break; > > - else if (type == 0x100) > > - { > > - /* Count SMT. */ > > - if ((count & 0x1)) > > - { > > - int count_mask; > > - > > - /* Compute count mask. */ > > - asm ("bsr %1, %0" > > - : "=r" (count_mask) : "g" (threads_l2)); > > - count_mask = ~(-1 << (count_mask + 1)); > > - threads_l2 = (shipped - 1) & count_mask; > > - count &= ~0x1; > > - } > > - } > > - else if (type == 0x200) > > - { > > - /* Count core. */ > > - if ((count & (0x1 << 1))) > > - { > > - int count_mask; > > - int threads_core > > - = (level == 2 ? threads_l2 : threads_l3); > > - > > - /* Compute count mask. */ > > - asm ("bsr %1, %0" > > - : "=r" (count_mask) : "g" (threads_core)); > > - count_mask = ~(-1 << (count_mask + 1)); > > - threads_core = (shipped - 1) & count_mask; > > - if (level == 2) > > - threads_l2 = threads_core; > > - else > > - threads_l3 = threads_core; > > - count &= ~(0x1 << 1); > > - } > > - } > > - } > > - } > > - if (threads_l2 > 0) > > - threads_l2 += 1; > > - if (threads_l3 > 0) > > - threads_l3 += 1; > > - if (level == 2) > > - { > > - if (threads_l2) > > - { > > - threads = threads_l2; > > - if (cpu_features->basic.kind == arch_kind_intel > > - && threads > 2 > > - && family == 6) > > - switch (model) > > - { > > - case 0x37: > > - case 0x4a: > > - case 0x4d: > > - case 0x5a: > > - case 0x5d: > > - /* Silvermont has L2 cache shared by 2 cores. */ > > - threads = 2; > > - break; > > - default: > > - break; > > - } > > - } > > - } > > - else if (threads_l3) > > - threads = threads_l3; > > - } > > - else > > - { > > -intel_bug_no_cache_info: > > - /* Assume that all logical threads share the highest cache > > - level. */ > > - threads > > - = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx > > - >> 16) & 0xff); > > - } > > - > > - /* Cap usage of highest cache level to the number of supported > > - threads. */ > > - if (shared > 0 && threads > 0) > > - shared /= threads; > > - } > > - > > - /* Account for non-inclusive L2 and L3 caches. */ > > - if (!inclusive_cache) > > - { > > - if (threads_l2 > 0) > > - core /= threads_l2; > > - shared += core; > > - } > > - > > - *shared_ptr = shared; > > - *threads_ptr = threads; > > -} > > - > > static void > > init_cacheinfo (void) > > { > > - /* Find out what brand of processor. */ > > - unsigned int ebx; > > - unsigned int ecx; > > - unsigned int edx; > > - int max_cpuid_ex; > > - long int data = -1; > > - long int shared = -1; > > - long int core; > > - unsigned int threads = 0; > > const struct cpu_features *cpu_features = __get_cpu_features (); > > + long int data = cpu_features->data_cache_size; > > + __x86_raw_data_cache_size_half = data / 2; > > + __x86_raw_data_cache_size = data; > > + /* Round data cache size to multiple of 256 bytes. */ > > + data = data & ~255L; > > + __x86_data_cache_size_half = data / 2; > > + __x86_data_cache_size = data; > > + > > + long int shared = cpu_features->shared_cache_size; > > + __x86_raw_shared_cache_size_half = shared / 2; > > + __x86_raw_shared_cache_size = shared; > > + /* Round shared cache size to multiple of 256 bytes. */ > > + shared = shared & ~255L; > > + __x86_shared_cache_size_half = shared / 2; > > + __x86_shared_cache_size = shared; > > > > - /* NB: In libc.so, cpu_features is defined in ld.so and is initialized > > - by DL_PLATFORM_INIT or IFUNC relocation before init_cacheinfo is > > - called by IFUNC relocation. In libc.a, init_cacheinfo is called > > - from init_cpu_features by ARCH_INIT_CPU_FEATURES. */ > > - assert (cpu_features->basic.kind != arch_kind_unknown); > > - > > - if (cpu_features->basic.kind == arch_kind_intel) > > - { > > - data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > > - core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > > - shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > > - > > - get_common_cache_info (&shared, &threads, core); > > - } > > - else if (cpu_features->basic.kind == arch_kind_zhaoxin) > > - { > > - data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); > > - core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); > > - shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > > - > > - get_common_cache_info (&shared, &threads, core); > > - } > > - else if (cpu_features->basic.kind == arch_kind_amd) > > - { > > - data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); > > - long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE); > > - shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); > > - > > - /* Get maximum extended function. */ > > - __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); > > - > > - if (shared <= 0) > > - /* No shared L3 cache. All we have is the L2 cache. */ > > - shared = core; > > - else > > - { > > - /* Figure out the number of logical threads that share L3. */ > > - if (max_cpuid_ex >= 0x80000008) > > - { > > - /* Get width of APIC ID. */ > > - __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); > > - threads = 1 << ((ecx >> 12) & 0x0f); > > - } > > - > > - if (threads == 0 || cpu_features->basic.family >= 0x17) > > - { > > - /* If APIC ID width is not available, use logical > > - processor count. */ > > - __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); > > - > > - if ((edx & (1 << 28)) != 0) > > - threads = (ebx >> 16) & 0xff; > > - } > > - > > - /* Cap usage of highest cache level to the number of > > - supported threads. */ > > - if (threads > 0) > > - shared /= threads; > > - > > - /* Get shared cache per ccx for Zen architectures. */ > > - if (cpu_features->basic.family >= 0x17) > > - { > > - unsigned int eax; > > - > > - /* Get number of threads share the L3 cache in CCX. */ > > - __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); > > - > > - unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; > > - shared *= threads_per_ccx; > > - } > > - else > > - { > > - /* Account for exclusive L2 and L3 caches. */ > > - shared += core; > > - } > > - } > > - } > > - > > - /* Prefer cache size configure via tuning. */ > > - if (cpu_features->data_cache_size != 0) > > - data = cpu_features->data_cache_size; > > - > > - if (data > 0) > > - { > > - __x86_raw_data_cache_size_half = data / 2; > > - __x86_raw_data_cache_size = data; > > - /* Round data cache size to multiple of 256 bytes. */ > > - data = data & ~255L; > > - __x86_data_cache_size_half = data / 2; > > - __x86_data_cache_size = data; > > - } > > - > > - /* Prefer cache size configure via tuning. */ > > - if (cpu_features->shared_cache_size != 0) > > - shared = cpu_features->shared_cache_size; > > - > > - if (shared > 0) > > - { > > - __x86_raw_shared_cache_size_half = shared / 2; > > - __x86_raw_shared_cache_size = shared; > > - /* Round shared cache size to multiple of 256 bytes. */ > > - shared = shared & ~255L; > > - __x86_shared_cache_size_half = shared / 2; > > - __x86_shared_cache_size = shared; > > - } > > - > > - /* The default setting for the non_temporal threshold is 3/4 of one > > - thread's share of the chip's cache. For most Intel and AMD processors > > - with an initial release date between 2017 and 2020, a thread's typical > > - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 > > - threshold leaves 125 KBytes to 500 KBytes of the thread's data > > - in cache after a maximum temporal copy, which will maintain > > - in cache a reasonable portion of the thread's stack and other > > - active data. If the threshold is set higher than one thread's > > - share of the cache, it has a substantial risk of negatively > > - impacting the performance of other threads running on the chip. */ > > __x86_shared_non_temporal_threshold > > - = (cpu_features->non_temporal_threshold != 0 > > - ? cpu_features->non_temporal_threshold > > - : __x86_shared_cache_size * 3 / 4); > > - > > - /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ > > - unsigned int minimum_rep_movsb_threshold; > > - /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ > > - unsigned int rep_movsb_threshold; > > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) > > - && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) > > - { > > - rep_movsb_threshold = 2048 * (64 / 16); > > - minimum_rep_movsb_threshold = 64 * 8; > > - } > > - else if (CPU_FEATURE_PREFERRED_P (cpu_features, > > - AVX_Fast_Unaligned_Load)) > > - { > > - rep_movsb_threshold = 2048 * (32 / 16); > > - minimum_rep_movsb_threshold = 32 * 8; > > - } > > - else > > - { > > - rep_movsb_threshold = 2048 * (16 / 16); > > - minimum_rep_movsb_threshold = 16 * 8; > > - } > > - if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold) > > - __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; > > - else > > - __x86_rep_movsb_threshold = rep_movsb_threshold; > > + = cpu_features->non_temporal_threshold; > > > > -# if HAVE_TUNABLES > > + __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; > > __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; > > -# endif > > } > > +#endif > > Ok, it is refactoring the code. > > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > > index f26deba38d..51c12d89ca 100644 > > --- a/sysdeps/x86/cpu-features.c > > +++ b/sysdeps/x86/cpu-features.c > > @@ -16,21 +16,12 @@ > > License along with the GNU C Library; if not, see > > <https://www.gnu.org/licenses/>. */ > > > > -#include <cpuid.h> > > #include <dl-hwcap.h> > > #include <libc-pointer-arith.h> > > -#if IS_IN (libc) && !defined SHARED > > -# include <assert.h> > > -# include <unistd.h> > > -# include <dl-cacheinfo.h> > > -# include <cacheinfo.h> > > -#endif > > +#include <cacheinfo.h> > > +#include <dl-cacheinfo.h> > > > > #if HAVE_TUNABLES > > -# define TUNABLE_NAMESPACE cpu > > -# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ > > -# include <elf/dl-tunables.h> > > - > > extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *) > > attribute_hidden; > > > > Ok. > > > @@ -642,24 +633,14 @@ no_cpuid: > > cpu_features->basic.model = model; > > cpu_features->basic.stepping = stepping; > > > > + dl_init_cacheinfo (cpu_features); > > + > > #if HAVE_TUNABLES > > TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps)); > > - cpu_features->non_temporal_threshold > > - = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); > > - cpu_features->rep_movsb_threshold > > - = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); > > - cpu_features->rep_stosb_threshold > > - = TUNABLE_GET (x86_rep_stosb_threshold, long int, NULL); > > - cpu_features->data_cache_size > > - = TUNABLE_GET (x86_data_cache_size, long int, NULL); > > - cpu_features->shared_cache_size > > - = TUNABLE_GET (x86_shared_cache_size, long int, NULL); > > -#endif > > - > > - /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */ > > -#if !HAVE_TUNABLES && defined SHARED > > - /* The glibc.cpu.hwcap_mask tunable is initialized already, so no need to do > > - this. */ > > +#elif defined SHARED > > + /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. The > > + glibc.cpu.hwcap_mask tunable is initialized already, so no > > + need to do this. */ > > GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT; > > #endif > > > > Ok. > > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > > index b2b90074b0..9632ee7818 100644 > > --- a/sysdeps/x86/dl-cacheinfo.h > > +++ b/sysdeps/x86/dl-cacheinfo.h > > @@ -476,3 +476,463 @@ handle_zhaoxin (int name) > > /* Nothing found. */ > > return 0; > > } > > + > > +static void > > +get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, > > + long int core) > > +{ > > + unsigned int eax; > > + unsigned int ebx; > > + unsigned int ecx; > > + unsigned int edx; > > + > > + /* Number of logical processors sharing L2 cache. */ > > + int threads_l2; > > + > > + /* Number of logical processors sharing L3 cache. */ > > + int threads_l3; > > + > > + const struct cpu_features *cpu_features = __get_cpu_features (); > > + int max_cpuid = cpu_features->basic.max_cpuid; > > + unsigned int family = cpu_features->basic.family; > > + unsigned int model = cpu_features->basic.model; > > + long int shared = *shared_ptr; > > + unsigned int threads = *threads_ptr; > > + bool inclusive_cache = true; > > + bool support_count_mask = true; > > + > > + /* Try L3 first. */ > > + unsigned int level = 3; > > + > > + if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) > > + support_count_mask = false; > > + > > + if (shared <= 0) > > + { > > + /* Try L2 otherwise. */ > > + level = 2; > > + shared = core; > > + threads_l2 = 0; > > + threads_l3 = -1; > > + } > > + else > > + { > > + threads_l2 = 0; > > + threads_l3 = 0; > > + } > > + > > + /* A value of 0 for the HTT bit indicates there is only a single > > + logical processor. */ > > + if (HAS_CPU_FEATURE (HTT)) > > + { > > + /* Figure out the number of logical threads that share the > > + highest cache level. */ > > + if (max_cpuid >= 4) > > + { > > + int i = 0; > > + > > + /* Query until cache level 2 and 3 are enumerated. */ > > + int check = 0x1 | (threads_l3 == 0) << 1; > > + do > > + { > > + __cpuid_count (4, i++, eax, ebx, ecx, edx); > > + > > + /* There seems to be a bug in at least some Pentium Ds > > + which sometimes fail to iterate all cache parameters. > > + Do not loop indefinitely here, stop in this case and > > + assume there is no such information. */ > > + if (cpu_features->basic.kind == arch_kind_intel > > + && (eax & 0x1f) == 0 ) > > + goto intel_bug_no_cache_info; > > + > > + switch ((eax >> 5) & 0x7) > > + { > > + default: > > + break; > > + case 2: > > + if ((check & 0x1)) > > + { > > + /* Get maximum number of logical processors > > + sharing L2 cache. */ > > + threads_l2 = (eax >> 14) & 0x3ff; > > + check &= ~0x1; > > + } > > + break; > > + case 3: > > + if ((check & (0x1 << 1))) > > + { > > + /* Get maximum number of logical processors > > + sharing L3 cache. */ > > + threads_l3 = (eax >> 14) & 0x3ff; > > + > > + /* Check if L2 and L3 caches are inclusive. */ > > + inclusive_cache = (edx & 0x2) != 0; > > + check &= ~(0x1 << 1); > > + } > > + break; > > + } > > + } > > + while (check); > > + > > + /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum > > + numbers of addressable IDs for logical processors sharing > > + the cache, instead of the maximum number of threads > > + sharing the cache. */ > > + if (max_cpuid >= 11 && support_count_mask) > > + { > > + /* Find the number of logical processors shipped in > > + one core and apply count mask. */ > > + i = 0; > > + > > + /* Count SMT only if there is L3 cache. Always count > > + core if there is no L3 cache. */ > > + int count = ((threads_l2 > 0 && level == 3) > > + | ((threads_l3 > 0 > > + || (threads_l2 > 0 && level == 2)) << 1)); > > + > > + while (count) > > + { > > + __cpuid_count (11, i++, eax, ebx, ecx, edx); > > + > > + int shipped = ebx & 0xff; > > + int type = ecx & 0xff00; > > + if (shipped == 0 || type == 0) > > + break; > > + else if (type == 0x100) > > + { > > + /* Count SMT. */ > > + if ((count & 0x1)) > > + { > > + int count_mask; > > + > > + /* Compute count mask. */ > > + asm ("bsr %1, %0" > > + : "=r" (count_mask) : "g" (threads_l2)); > > + count_mask = ~(-1 << (count_mask + 1)); > > + threads_l2 = (shipped - 1) & count_mask; > > + count &= ~0x1; > > + } > > + } > > + else if (type == 0x200) > > + { > > + /* Count core. */ > > + if ((count & (0x1 << 1))) > > + { > > + int count_mask; > > + int threads_core > > + = (level == 2 ? threads_l2 : threads_l3); > > + > > + /* Compute count mask. */ > > + asm ("bsr %1, %0" > > + : "=r" (count_mask) : "g" (threads_core)); > > + count_mask = ~(-1 << (count_mask + 1)); > > + threads_core = (shipped - 1) & count_mask; > > + if (level == 2) > > + threads_l2 = threads_core; > > + else > > + threads_l3 = threads_core; > > + count &= ~(0x1 << 1); > > + } > > + } > > + } > > + } > > + if (threads_l2 > 0) > > + threads_l2 += 1; > > + if (threads_l3 > 0) > > + threads_l3 += 1; > > + if (level == 2) > > + { > > + if (threads_l2) > > + { > > + threads = threads_l2; > > + if (cpu_features->basic.kind == arch_kind_intel > > + && threads > 2 > > + && family == 6) > > + switch (model) > > + { > > + case 0x37: > > + case 0x4a: > > + case 0x4d: > > + case 0x5a: > > + case 0x5d: > > + /* Silvermont has L2 cache shared by 2 cores. */ > > + threads = 2; > > + break; > > + default: > > + break; > > + } > > + } > > + } > > + else if (threads_l3) > > + threads = threads_l3; > > + } > > + else > > + { > > +intel_bug_no_cache_info: > > + /* Assume that all logical threads share the highest cache > > + level. */ > > + threads > > + = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx > > + >> 16) & 0xff); > > + } > > + > > + /* Cap usage of highest cache level to the number of supported > > + threads. */ > > + if (shared > 0 && threads > 0) > > + shared /= threads; > > + } > > + > > + /* Account for non-inclusive L2 and L3 caches. */ > > + if (!inclusive_cache) > > + { > > + if (threads_l2 > 0) > > + core /= threads_l2; > > + shared += core; > > + } > > + > > + *shared_ptr = shared; > > + *threads_ptr = threads; > > +} > > + > > Ok, so this is function moved from sysdeps/x86/cacheinfo.h. > > > +static void > > +dl_init_cacheinfo (struct cpu_features *cpu_features) > > +{ > > + /* Find out what brand of processor. */ > > + unsigned int ebx; > > + unsigned int ecx; > > + unsigned int edx; > > + int max_cpuid_ex; > > + long int data = -1; > > + long int shared = -1; > > + long int core; > > + unsigned int threads = 0; > > + unsigned long int level1_icache_size = -1; > > + unsigned long int level1_dcache_size = -1; > > + unsigned long int level1_dcache_assoc = -1; > > + unsigned long int level1_dcache_linesize = -1; > > + unsigned long int level2_cache_size = -1; > > + unsigned long int level2_cache_assoc = -1; > > + unsigned long int level2_cache_linesize = -1; > > + unsigned long int level3_cache_size = -1; > > + unsigned long int level3_cache_assoc = -1; > > + unsigned long int level3_cache_linesize = -1; > > + unsigned long int level4_cache_size = -1; > > + > > + if (cpu_features->basic.kind == arch_kind_intel) > > + { > > + data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > > + core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > > + shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > > + > > + level1_icache_size > > + = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); > > + level1_dcache_size = data; > > + level1_dcache_assoc > > + = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); > > + level1_dcache_linesize > > + = handle_intel (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features); > > + level2_cache_size = core; > > + level2_cache_assoc > > + = handle_intel (_SC_LEVEL2_CACHE_ASSOC, cpu_features); > > + level2_cache_linesize > > + = handle_intel (_SC_LEVEL2_CACHE_LINESIZE, cpu_features); > > + level3_cache_size = shared; > > + level3_cache_assoc > > + = handle_intel (_SC_LEVEL3_CACHE_ASSOC, cpu_features); > > + level3_cache_linesize > > + = handle_intel (_SC_LEVEL3_CACHE_LINESIZE, cpu_features); > > + level4_cache_size > > + = handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features); > > + > > + get_common_cache_info (&shared, &threads, core); > > + } > > + else if (cpu_features->basic.kind == arch_kind_zhaoxin) > > + { > > + data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); > > + core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); > > + shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > > + > > + level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); > > + level1_dcache_size = data; > > + level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); > > + level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE); > > + level2_cache_size = core; > > + level2_cache_assoc = handle_zhaoxin (_SC_LEVEL2_CACHE_ASSOC); > > + level2_cache_linesize = handle_zhaoxin (_SC_LEVEL2_CACHE_LINESIZE); > > + level3_cache_size = shared; > > + level3_cache_assoc = handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC); > > + level3_cache_linesize = handle_zhaoxin (_SC_LEVEL3_CACHE_LINESIZE); > > + > > + get_common_cache_info (&shared, &threads, core); > > + } > > + else if (cpu_features->basic.kind == arch_kind_amd) > > + { > > + data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); > > + core = handle_amd (_SC_LEVEL2_CACHE_SIZE); > > + shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); > > + > > + level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); > > + level1_dcache_size = data; > > + level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); > > + level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); > > + level2_cache_size = core; > > + level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC); > > + level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE); > > + level3_cache_size = shared; > > + level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC); > > + level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE); > > + > > + /* Get maximum extended function. */ > > + __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); > > + > > + if (shared <= 0) > > + /* No shared L3 cache. All we have is the L2 cache. */ > > + shared = core; > > + else > > + { > > + /* Figure out the number of logical threads that share L3. */ > > + if (max_cpuid_ex >= 0x80000008) > > + { > > + /* Get width of APIC ID. */ > > + __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); > > + threads = 1 << ((ecx >> 12) & 0x0f); > > + } > > + > > + if (threads == 0 || cpu_features->basic.family >= 0x17) > > + { > > + /* If APIC ID width is not available, use logical > > + processor count. */ > > + __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); > > + > > + if ((edx & (1 << 28)) != 0) > > + threads = (ebx >> 16) & 0xff; > > + } > > + > > + /* Cap usage of highest cache level to the number of > > + supported threads. */ > > + if (threads > 0) > > + shared /= threads; > > + > > + /* Get shared cache per ccx for Zen architectures. */ > > + if (cpu_features->basic.family >= 0x17) > > + { > > + unsigned int eax; > > + > > + /* Get number of threads share the L3 cache in CCX. */ > > + __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); > > + > > + unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; > > + shared *= threads_per_ccx; > > + } > > + else > > + { > > + /* Account for exclusive L2 and L3 caches. */ > > + shared += core; > > + } > > + } > > + } > > + > > + cpu_features->level1_icache_size = level1_icache_size; > > + cpu_features->level1_dcache_size = level1_dcache_size; > > + cpu_features->level1_dcache_assoc = level1_dcache_assoc; > > + cpu_features->level1_dcache_linesize = level1_dcache_linesize; > > + cpu_features->level2_cache_size = level2_cache_size; > > + cpu_features->level2_cache_assoc = level2_cache_assoc; > > + cpu_features->level2_cache_linesize = level2_cache_linesize; > > + cpu_features->level3_cache_size = level3_cache_size; > > + cpu_features->level3_cache_assoc = level3_cache_assoc; > > + cpu_features->level3_cache_linesize = level3_cache_linesize; > > + cpu_features->level4_cache_size = level4_cache_size; > > Ok, so you are expanding the definitions by family. > > > + > > + /* The default setting for the non_temporal threshold is 3/4 of one > > + thread's share of the chip's cache. For most Intel and AMD processors > > + with an initial release date between 2017 and 2020, a thread's typical > > + share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 > > + threshold leaves 125 KBytes to 500 KBytes of the thread's data > > + in cache after a maximum temporal copy, which will maintain > > + in cache a reasonable portion of the thread's stack and other > > + active data. If the threshold is set higher than one thread's > > + share of the cache, it has a substantial risk of negatively > > + impacting the performance of other threads running on the chip. */ > > + unsigned long int non_temporal_threshold = shared * 3 / 4; > > + > > +#if HAVE_TUNABLES > > + /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ > > + unsigned int minimum_rep_movsb_threshold; > > +#endif > > + /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ > > + unsigned int rep_movsb_threshold; > > + if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) > > + && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) > > + { > > + rep_movsb_threshold = 2048 * (64 / 16); > > +#if HAVE_TUNABLES > > + minimum_rep_movsb_threshold = 64 * 8; > > +#endif > > + } > > + else if (CPU_FEATURE_PREFERRED_P (cpu_features, > > + AVX_Fast_Unaligned_Load)) > > + { > > + rep_movsb_threshold = 2048 * (32 / 16); > > +#if HAVE_TUNABLES > > + minimum_rep_movsb_threshold = 32 * 8; > > +#endif > > + } > > + else > > + { > > + rep_movsb_threshold = 2048 * (16 / 16); > > +#if HAVE_TUNABLES > > + minimum_rep_movsb_threshold = 16 * 8; > > +#endif > > + } > > + > > + /* The default threshold to use Enhanced REP STOSB. */ > > + unsigned long int rep_stosb_threshold = 2048; > > + > > Ok. > > > +#if HAVE_TUNABLES > > + long int tunable_size; > > + > > + tunable_size = TUNABLE_GET (x86_data_cache_size, long int, NULL); > > + /* NB: Ignore the default value 0. */ > > + if (tunable_size) > > No implicit checks, same as the others below. Fixed. > > + data = tunable_size; > > + > > + tunable_size = TUNABLE_GET (x86_shared_cache_size, long int, NULL); > > + /* NB: Ignore the default value 0. */ > > + if (tunable_size) Fixed. > > + shared = tunable_size; > > + > > + tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); > > + /* NB: Ignore the default value 0. */ > > + if (tunable_size) Fixed. > > + non_temporal_threshold = tunable_size; > > + > > + tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); > > + if (tunable_size > minimum_rep_movsb_threshold) > > + rep_movsb_threshold = tunable_size; > > + > > + /* NB: The default value of the x86_rep_stosb_threshold tunable is the > > + same as the default value of __x86_rep_stosb_threshold and the > > + minimum value is fixed. */ > > + rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold, > > + long int, NULL); > > + > > + TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, long int, data, > > + 0, (long int) -1); > > + TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, long int, shared, > > + 0, (long int) -1); > > + TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, long int, > > + non_temporal_threshold, 0, (long int) -1); > > + TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, long int, > > + rep_movsb_threshold, > > + minimum_rep_movsb_threshold, (long int) -1); > > + TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, long int, > > + rep_stosb_threshold, 1, (long int) -1); > > +#endif > > Ok. Are the bounds ok for the architecture? The bounds are OK since they are derived from CPUID. > > + > > + cpu_features->data_cache_size = data; > > + cpu_features->shared_cache_size = shared; > > + cpu_features->non_temporal_threshold = non_temporal_threshold; > > + cpu_features->rep_movsb_threshold = rep_movsb_threshold; > > + cpu_features->rep_stosb_threshold = rep_stosb_threshold; > > +} > > Ok. > > > diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h > > index f62be0b9b3..3f3bd93320 100644 > > --- a/sysdeps/x86/include/cpu-features.h > > +++ b/sysdeps/x86/include/cpu-features.h > > @@ -153,6 +153,28 @@ struct cpu_features > > unsigned long int rep_movsb_threshold; > > /* Threshold to use "rep stosb". */ > > unsigned long int rep_stosb_threshold; > > + /* _SC_LEVEL1_ICACHE_SIZE. */ > > + unsigned long int level1_icache_size; > > + /* _SC_LEVEL1_DCACHE_SIZE. */ > > + unsigned long int level1_dcache_size; > > + /* _SC_LEVEL1_DCACHE_ASSOC. */ > > + unsigned long int level1_dcache_assoc; > > + /* _SC_LEVEL1_DCACHE_LINESIZE. */ > > + unsigned long int level1_dcache_linesize; > > + /* _SC_LEVEL2_CACHE_ASSOC. */ > > + unsigned long int level2_cache_size; > > + /* _SC_LEVEL2_DCACHE_ASSOC. */ > > + unsigned long int level2_cache_assoc; > > + /* _SC_LEVEL2_CACHE_LINESIZE. */ > > + unsigned long int level2_cache_linesize; > > + /* /_SC_LEVEL3_CACHE_SIZE. */ > > + unsigned long int level3_cache_size; > > + /* _SC_LEVEL3_CACHE_ASSOC. */ > > + unsigned long int level3_cache_assoc; > > + /* _SC_LEVEL3_CACHE_LINESIZE. */ > > + unsigned long int level3_cache_linesize; > > + /* /_SC_LEVEL4_CACHE_SIZE. */ > > + unsigned long int level4_cache_size; > > }; > > > > # if defined (_LIBC) && !IS_IN (nonlib) > > > > Ok. Here is the updated patch I am checking in. Thanks. -- H.J. [-- Attachment #2: 0001-x86-Move-x86-processor-cache-info-to-cpu_features.patch --] [-- Type: text/x-patch, Size: 37872 bytes --] From ebef59ae6f104fd0c8b832a7f56136d39fb4e9e3 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Fri, 18 Sep 2020 07:55:14 -0700 Subject: [PATCH] x86: Move x86 processor cache info to cpu_features 1. Move x86 processor cache info to _dl_x86_cpu_features in ld.so. 2. Update tunable bounds with TUNABLE_SET_WITH_BOUNDS. 3. Move x86 cache info initialization to dl-cacheinfo.h and initialize x86 cache info in init_cpu_features (). 4. Put x86 cache info for libc in cacheinfo.h, which is included in libc-start.c in libc.a and is included in cacheinfo.c in libc.so. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> --- sysdeps/x86/cacheinfo.c | 46 ++- sysdeps/x86/cacheinfo.h | 400 ++----------------------- sysdeps/x86/cpu-features.c | 35 +-- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++++++++++ sysdeps/x86/include/cpu-features.h | 22 ++ 5 files changed, 551 insertions(+), 412 deletions(-) diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index ed4e1a5b58..350cba5fda 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -18,11 +18,8 @@ #if IS_IN (libc) -#include <assert.h> #include <unistd.h> -#include <cpuid.h> #include <ldsodefs.h> -#include <dl-cacheinfo.h> /* Get the value of the system variable NAME. */ long int @@ -30,20 +27,45 @@ attribute_hidden __cache_sysconf (int name) { const struct cpu_features *cpu_features = __get_cpu_features (); + switch (name) + { + case _SC_LEVEL1_ICACHE_SIZE: + return cpu_features->level1_icache_size; - if (cpu_features->basic.kind == arch_kind_intel) - return handle_intel (name, cpu_features); + case _SC_LEVEL1_DCACHE_SIZE: + return cpu_features->level1_dcache_size; - if (cpu_features->basic.kind == arch_kind_amd) - return handle_amd (name); + case _SC_LEVEL1_DCACHE_ASSOC: + return cpu_features->level1_dcache_assoc; - if (cpu_features->basic.kind == arch_kind_zhaoxin) - return handle_zhaoxin (name); + case _SC_LEVEL1_DCACHE_LINESIZE: + return cpu_features->level1_dcache_linesize; - // XXX Fill in more vendors. + case _SC_LEVEL2_CACHE_SIZE: + return cpu_features->level2_cache_size; - /* CPU not known, we have no information. */ - return 0; + case _SC_LEVEL2_CACHE_ASSOC: + return cpu_features->level2_cache_assoc; + + case _SC_LEVEL2_CACHE_LINESIZE: + return cpu_features->level2_cache_linesize; + + case _SC_LEVEL3_CACHE_SIZE: + return cpu_features->level3_cache_size; + + case _SC_LEVEL3_CACHE_ASSOC: + return cpu_features->level3_cache_assoc; + + case _SC_LEVEL3_CACHE_LINESIZE: + return cpu_features->level3_cache_linesize; + + case _SC_LEVEL4_CACHE_SIZE: + return cpu_features->level4_cache_size; + + default: + break; + } + return -1; } # ifdef SHARED diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h index 00d2d8a52a..68c253542f 100644 --- a/sysdeps/x86/cacheinfo.h +++ b/sysdeps/x86/cacheinfo.h @@ -18,7 +18,16 @@ #include <assert.h> #include <unistd.h> +#include <cpuid.h> +#include <cpu-features.h> +#if HAVE_TUNABLES +# define TUNABLE_NAMESPACE cpu +# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ +# include <elf/dl-tunables.h> +#endif + +#if IS_IN (libc) /* Data cache size for use in memory and string routines, typically L1 size, rounded to multiple of 256 bytes. */ long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2; @@ -45,385 +54,30 @@ long int __x86_rep_movsb_threshold attribute_hidden = 2048; /* Threshold to use Enhanced REP STOSB. */ long int __x86_rep_stosb_threshold attribute_hidden = 2048; -static void -get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, - long int core) -{ - unsigned int eax; - unsigned int ebx; - unsigned int ecx; - unsigned int edx; - - /* Number of logical processors sharing L2 cache. */ - int threads_l2; - - /* Number of logical processors sharing L3 cache. */ - int threads_l3; - - const struct cpu_features *cpu_features = __get_cpu_features (); - int max_cpuid = cpu_features->basic.max_cpuid; - unsigned int family = cpu_features->basic.family; - unsigned int model = cpu_features->basic.model; - long int shared = *shared_ptr; - unsigned int threads = *threads_ptr; - bool inclusive_cache = true; - bool support_count_mask = true; - - /* Try L3 first. */ - unsigned int level = 3; - - if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) - support_count_mask = false; - - if (shared <= 0) - { - /* Try L2 otherwise. */ - level = 2; - shared = core; - threads_l2 = 0; - threads_l3 = -1; - } - else - { - threads_l2 = 0; - threads_l3 = 0; - } - - /* A value of 0 for the HTT bit indicates there is only a single - logical processor. */ - if (HAS_CPU_FEATURE (HTT)) - { - /* Figure out the number of logical threads that share the - highest cache level. */ - if (max_cpuid >= 4) - { - int i = 0; - - /* Query until cache level 2 and 3 are enumerated. */ - int check = 0x1 | (threads_l3 == 0) << 1; - do - { - __cpuid_count (4, i++, eax, ebx, ecx, edx); - - /* There seems to be a bug in at least some Pentium Ds - which sometimes fail to iterate all cache parameters. - Do not loop indefinitely here, stop in this case and - assume there is no such information. */ - if (cpu_features->basic.kind == arch_kind_intel - && (eax & 0x1f) == 0 ) - goto intel_bug_no_cache_info; - - switch ((eax >> 5) & 0x7) - { - default: - break; - case 2: - if ((check & 0x1)) - { - /* Get maximum number of logical processors - sharing L2 cache. */ - threads_l2 = (eax >> 14) & 0x3ff; - check &= ~0x1; - } - break; - case 3: - if ((check & (0x1 << 1))) - { - /* Get maximum number of logical processors - sharing L3 cache. */ - threads_l3 = (eax >> 14) & 0x3ff; - - /* Check if L2 and L3 caches are inclusive. */ - inclusive_cache = (edx & 0x2) != 0; - check &= ~(0x1 << 1); - } - break; - } - } - while (check); - - /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum - numbers of addressable IDs for logical processors sharing - the cache, instead of the maximum number of threads - sharing the cache. */ - if (max_cpuid >= 11 && support_count_mask) - { - /* Find the number of logical processors shipped in - one core and apply count mask. */ - i = 0; - - /* Count SMT only if there is L3 cache. Always count - core if there is no L3 cache. */ - int count = ((threads_l2 > 0 && level == 3) - | ((threads_l3 > 0 - || (threads_l2 > 0 && level == 2)) << 1)); - - while (count) - { - __cpuid_count (11, i++, eax, ebx, ecx, edx); - - int shipped = ebx & 0xff; - int type = ecx & 0xff00; - if (shipped == 0 || type == 0) - break; - else if (type == 0x100) - { - /* Count SMT. */ - if ((count & 0x1)) - { - int count_mask; - - /* Compute count mask. */ - asm ("bsr %1, %0" - : "=r" (count_mask) : "g" (threads_l2)); - count_mask = ~(-1 << (count_mask + 1)); - threads_l2 = (shipped - 1) & count_mask; - count &= ~0x1; - } - } - else if (type == 0x200) - { - /* Count core. */ - if ((count & (0x1 << 1))) - { - int count_mask; - int threads_core - = (level == 2 ? threads_l2 : threads_l3); - - /* Compute count mask. */ - asm ("bsr %1, %0" - : "=r" (count_mask) : "g" (threads_core)); - count_mask = ~(-1 << (count_mask + 1)); - threads_core = (shipped - 1) & count_mask; - if (level == 2) - threads_l2 = threads_core; - else - threads_l3 = threads_core; - count &= ~(0x1 << 1); - } - } - } - } - if (threads_l2 > 0) - threads_l2 += 1; - if (threads_l3 > 0) - threads_l3 += 1; - if (level == 2) - { - if (threads_l2) - { - threads = threads_l2; - if (cpu_features->basic.kind == arch_kind_intel - && threads > 2 - && family == 6) - switch (model) - { - case 0x37: - case 0x4a: - case 0x4d: - case 0x5a: - case 0x5d: - /* Silvermont has L2 cache shared by 2 cores. */ - threads = 2; - break; - default: - break; - } - } - } - else if (threads_l3) - threads = threads_l3; - } - else - { -intel_bug_no_cache_info: - /* Assume that all logical threads share the highest cache - level. */ - threads - = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx - >> 16) & 0xff); - } - - /* Cap usage of highest cache level to the number of supported - threads. */ - if (shared > 0 && threads > 0) - shared /= threads; - } - - /* Account for non-inclusive L2 and L3 caches. */ - if (!inclusive_cache) - { - if (threads_l2 > 0) - core /= threads_l2; - shared += core; - } - - *shared_ptr = shared; - *threads_ptr = threads; -} - static void init_cacheinfo (void) { - /* Find out what brand of processor. */ - unsigned int ebx; - unsigned int ecx; - unsigned int edx; - int max_cpuid_ex; - long int data = -1; - long int shared = -1; - long int core; - unsigned int threads = 0; const struct cpu_features *cpu_features = __get_cpu_features (); + long int data = cpu_features->data_cache_size; + __x86_raw_data_cache_size_half = data / 2; + __x86_raw_data_cache_size = data; + /* Round data cache size to multiple of 256 bytes. */ + data = data & ~255L; + __x86_data_cache_size_half = data / 2; + __x86_data_cache_size = data; + + long int shared = cpu_features->shared_cache_size; + __x86_raw_shared_cache_size_half = shared / 2; + __x86_raw_shared_cache_size = shared; + /* Round shared cache size to multiple of 256 bytes. */ + shared = shared & ~255L; + __x86_shared_cache_size_half = shared / 2; + __x86_shared_cache_size = shared; - /* NB: In libc.so, cpu_features is defined in ld.so and is initialized - by DL_PLATFORM_INIT or IFUNC relocation before init_cacheinfo is - called by IFUNC relocation. In libc.a, init_cacheinfo is called - from init_cpu_features by ARCH_INIT_CPU_FEATURES. */ - assert (cpu_features->basic.kind != arch_kind_unknown); - - if (cpu_features->basic.kind == arch_kind_intel) - { - data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); - core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); - shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); - - get_common_cache_info (&shared, &threads, core); - } - else if (cpu_features->basic.kind == arch_kind_zhaoxin) - { - data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); - core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); - shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); - - get_common_cache_info (&shared, &threads, core); - } - else if (cpu_features->basic.kind == arch_kind_amd) - { - data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); - long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE); - shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); - - /* Get maximum extended function. */ - __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); - - if (shared <= 0) - /* No shared L3 cache. All we have is the L2 cache. */ - shared = core; - else - { - /* Figure out the number of logical threads that share L3. */ - if (max_cpuid_ex >= 0x80000008) - { - /* Get width of APIC ID. */ - __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); - threads = 1 << ((ecx >> 12) & 0x0f); - } - - if (threads == 0 || cpu_features->basic.family >= 0x17) - { - /* If APIC ID width is not available, use logical - processor count. */ - __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); - - if ((edx & (1 << 28)) != 0) - threads = (ebx >> 16) & 0xff; - } - - /* Cap usage of highest cache level to the number of - supported threads. */ - if (threads > 0) - shared /= threads; - - /* Get shared cache per ccx for Zen architectures. */ - if (cpu_features->basic.family >= 0x17) - { - unsigned int eax; - - /* Get number of threads share the L3 cache in CCX. */ - __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); - - unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; - shared *= threads_per_ccx; - } - else - { - /* Account for exclusive L2 and L3 caches. */ - shared += core; - } - } - } - - /* Prefer cache size configure via tuning. */ - if (cpu_features->data_cache_size != 0) - data = cpu_features->data_cache_size; - - if (data > 0) - { - __x86_raw_data_cache_size_half = data / 2; - __x86_raw_data_cache_size = data; - /* Round data cache size to multiple of 256 bytes. */ - data = data & ~255L; - __x86_data_cache_size_half = data / 2; - __x86_data_cache_size = data; - } - - /* Prefer cache size configure via tuning. */ - if (cpu_features->shared_cache_size != 0) - shared = cpu_features->shared_cache_size; - - if (shared > 0) - { - __x86_raw_shared_cache_size_half = shared / 2; - __x86_raw_shared_cache_size = shared; - /* Round shared cache size to multiple of 256 bytes. */ - shared = shared & ~255L; - __x86_shared_cache_size_half = shared / 2; - __x86_shared_cache_size = shared; - } - - /* The default setting for the non_temporal threshold is 3/4 of one - thread's share of the chip's cache. For most Intel and AMD processors - with an initial release date between 2017 and 2020, a thread's typical - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 - threshold leaves 125 KBytes to 500 KBytes of the thread's data - in cache after a maximum temporal copy, which will maintain - in cache a reasonable portion of the thread's stack and other - active data. If the threshold is set higher than one thread's - share of the cache, it has a substantial risk of negatively - impacting the performance of other threads running on the chip. */ __x86_shared_non_temporal_threshold - = (cpu_features->non_temporal_threshold != 0 - ? cpu_features->non_temporal_threshold - : __x86_shared_cache_size * 3 / 4); - - /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ - unsigned int minimum_rep_movsb_threshold; - /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ - unsigned int rep_movsb_threshold; - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) - && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) - { - rep_movsb_threshold = 2048 * (64 / 16); - minimum_rep_movsb_threshold = 64 * 8; - } - else if (CPU_FEATURE_PREFERRED_P (cpu_features, - AVX_Fast_Unaligned_Load)) - { - rep_movsb_threshold = 2048 * (32 / 16); - minimum_rep_movsb_threshold = 32 * 8; - } - else - { - rep_movsb_threshold = 2048 * (16 / 16); - minimum_rep_movsb_threshold = 16 * 8; - } - if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold) - __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; - else - __x86_rep_movsb_threshold = rep_movsb_threshold; + = cpu_features->non_temporal_threshold; -# if HAVE_TUNABLES + __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; -# endif } +#endif diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index e7da682a2e..06e4307b71 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -16,22 +16,13 @@ License along with the GNU C Library; if not, see <https://www.gnu.org/licenses/>. */ -#include <cpuid.h> #include <dl-hwcap.h> #include <libc-pointer-arith.h> #include <get-isa-level.h> -#if IS_IN (libc) && !defined SHARED -# include <assert.h> -# include <unistd.h> -# include <dl-cacheinfo.h> -# include <cacheinfo.h> -#endif +#include <cacheinfo.h> +#include <dl-cacheinfo.h> #if HAVE_TUNABLES -# define TUNABLE_NAMESPACE cpu -# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */ -# include <elf/dl-tunables.h> - extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *) attribute_hidden; @@ -646,24 +637,14 @@ no_cpuid: cpu_features->basic.model = model; cpu_features->basic.stepping = stepping; + dl_init_cacheinfo (cpu_features); + #if HAVE_TUNABLES TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps)); - cpu_features->non_temporal_threshold - = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); - cpu_features->rep_movsb_threshold - = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); - cpu_features->rep_stosb_threshold - = TUNABLE_GET (x86_rep_stosb_threshold, long int, NULL); - cpu_features->data_cache_size - = TUNABLE_GET (x86_data_cache_size, long int, NULL); - cpu_features->shared_cache_size - = TUNABLE_GET (x86_shared_cache_size, long int, NULL); -#endif - - /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */ -#if !HAVE_TUNABLES && defined SHARED - /* The glibc.cpu.hwcap_mask tunable is initialized already, so no need to do - this. */ +#elif defined SHARED + /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. The + glibc.cpu.hwcap_mask tunable is initialized already, so no + need to do this. */ GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT; #endif diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index 6adce4147c..96c49f2411 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -476,3 +476,463 @@ handle_zhaoxin (int name) /* Nothing found. */ return 0; } + +static void +get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr, + long int core) +{ + unsigned int eax; + unsigned int ebx; + unsigned int ecx; + unsigned int edx; + + /* Number of logical processors sharing L2 cache. */ + int threads_l2; + + /* Number of logical processors sharing L3 cache. */ + int threads_l3; + + const struct cpu_features *cpu_features = __get_cpu_features (); + int max_cpuid = cpu_features->basic.max_cpuid; + unsigned int family = cpu_features->basic.family; + unsigned int model = cpu_features->basic.model; + long int shared = *shared_ptr; + unsigned int threads = *threads_ptr; + bool inclusive_cache = true; + bool support_count_mask = true; + + /* Try L3 first. */ + unsigned int level = 3; + + if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6) + support_count_mask = false; + + if (shared <= 0) + { + /* Try L2 otherwise. */ + level = 2; + shared = core; + threads_l2 = 0; + threads_l3 = -1; + } + else + { + threads_l2 = 0; + threads_l3 = 0; + } + + /* A value of 0 for the HTT bit indicates there is only a single + logical processor. */ + if (HAS_CPU_FEATURE (HTT)) + { + /* Figure out the number of logical threads that share the + highest cache level. */ + if (max_cpuid >= 4) + { + int i = 0; + + /* Query until cache level 2 and 3 are enumerated. */ + int check = 0x1 | (threads_l3 == 0) << 1; + do + { + __cpuid_count (4, i++, eax, ebx, ecx, edx); + + /* There seems to be a bug in at least some Pentium Ds + which sometimes fail to iterate all cache parameters. + Do not loop indefinitely here, stop in this case and + assume there is no such information. */ + if (cpu_features->basic.kind == arch_kind_intel + && (eax & 0x1f) == 0 ) + goto intel_bug_no_cache_info; + + switch ((eax >> 5) & 0x7) + { + default: + break; + case 2: + if ((check & 0x1)) + { + /* Get maximum number of logical processors + sharing L2 cache. */ + threads_l2 = (eax >> 14) & 0x3ff; + check &= ~0x1; + } + break; + case 3: + if ((check & (0x1 << 1))) + { + /* Get maximum number of logical processors + sharing L3 cache. */ + threads_l3 = (eax >> 14) & 0x3ff; + + /* Check if L2 and L3 caches are inclusive. */ + inclusive_cache = (edx & 0x2) != 0; + check &= ~(0x1 << 1); + } + break; + } + } + while (check); + + /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum + numbers of addressable IDs for logical processors sharing + the cache, instead of the maximum number of threads + sharing the cache. */ + if (max_cpuid >= 11 && support_count_mask) + { + /* Find the number of logical processors shipped in + one core and apply count mask. */ + i = 0; + + /* Count SMT only if there is L3 cache. Always count + core if there is no L3 cache. */ + int count = ((threads_l2 > 0 && level == 3) + | ((threads_l3 > 0 + || (threads_l2 > 0 && level == 2)) << 1)); + + while (count) + { + __cpuid_count (11, i++, eax, ebx, ecx, edx); + + int shipped = ebx & 0xff; + int type = ecx & 0xff00; + if (shipped == 0 || type == 0) + break; + else if (type == 0x100) + { + /* Count SMT. */ + if ((count & 0x1)) + { + int count_mask; + + /* Compute count mask. */ + asm ("bsr %1, %0" + : "=r" (count_mask) : "g" (threads_l2)); + count_mask = ~(-1 << (count_mask + 1)); + threads_l2 = (shipped - 1) & count_mask; + count &= ~0x1; + } + } + else if (type == 0x200) + { + /* Count core. */ + if ((count & (0x1 << 1))) + { + int count_mask; + int threads_core + = (level == 2 ? threads_l2 : threads_l3); + + /* Compute count mask. */ + asm ("bsr %1, %0" + : "=r" (count_mask) : "g" (threads_core)); + count_mask = ~(-1 << (count_mask + 1)); + threads_core = (shipped - 1) & count_mask; + if (level == 2) + threads_l2 = threads_core; + else + threads_l3 = threads_core; + count &= ~(0x1 << 1); + } + } + } + } + if (threads_l2 > 0) + threads_l2 += 1; + if (threads_l3 > 0) + threads_l3 += 1; + if (level == 2) + { + if (threads_l2) + { + threads = threads_l2; + if (cpu_features->basic.kind == arch_kind_intel + && threads > 2 + && family == 6) + switch (model) + { + case 0x37: + case 0x4a: + case 0x4d: + case 0x5a: + case 0x5d: + /* Silvermont has L2 cache shared by 2 cores. */ + threads = 2; + break; + default: + break; + } + } + } + else if (threads_l3) + threads = threads_l3; + } + else + { +intel_bug_no_cache_info: + /* Assume that all logical threads share the highest cache + level. */ + threads + = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx + >> 16) & 0xff); + } + + /* Cap usage of highest cache level to the number of supported + threads. */ + if (shared > 0 && threads > 0) + shared /= threads; + } + + /* Account for non-inclusive L2 and L3 caches. */ + if (!inclusive_cache) + { + if (threads_l2 > 0) + core /= threads_l2; + shared += core; + } + + *shared_ptr = shared; + *threads_ptr = threads; +} + +static void +dl_init_cacheinfo (struct cpu_features *cpu_features) +{ + /* Find out what brand of processor. */ + unsigned int ebx; + unsigned int ecx; + unsigned int edx; + int max_cpuid_ex; + long int data = -1; + long int shared = -1; + long int core; + unsigned int threads = 0; + unsigned long int level1_icache_size = -1; + unsigned long int level1_dcache_size = -1; + unsigned long int level1_dcache_assoc = -1; + unsigned long int level1_dcache_linesize = -1; + unsigned long int level2_cache_size = -1; + unsigned long int level2_cache_assoc = -1; + unsigned long int level2_cache_linesize = -1; + unsigned long int level3_cache_size = -1; + unsigned long int level3_cache_assoc = -1; + unsigned long int level3_cache_linesize = -1; + unsigned long int level4_cache_size = -1; + + if (cpu_features->basic.kind == arch_kind_intel) + { + data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); + core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); + shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); + + level1_icache_size + = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); + level1_dcache_size = data; + level1_dcache_assoc + = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); + level1_dcache_linesize + = handle_intel (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features); + level2_cache_size = core; + level2_cache_assoc + = handle_intel (_SC_LEVEL2_CACHE_ASSOC, cpu_features); + level2_cache_linesize + = handle_intel (_SC_LEVEL2_CACHE_LINESIZE, cpu_features); + level3_cache_size = shared; + level3_cache_assoc + = handle_intel (_SC_LEVEL3_CACHE_ASSOC, cpu_features); + level3_cache_linesize + = handle_intel (_SC_LEVEL3_CACHE_LINESIZE, cpu_features); + level4_cache_size + = handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features); + + get_common_cache_info (&shared, &threads, core); + } + else if (cpu_features->basic.kind == arch_kind_zhaoxin) + { + data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); + core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); + shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); + + level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); + level1_dcache_size = data; + level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); + level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE); + level2_cache_size = core; + level2_cache_assoc = handle_zhaoxin (_SC_LEVEL2_CACHE_ASSOC); + level2_cache_linesize = handle_zhaoxin (_SC_LEVEL2_CACHE_LINESIZE); + level3_cache_size = shared; + level3_cache_assoc = handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC); + level3_cache_linesize = handle_zhaoxin (_SC_LEVEL3_CACHE_LINESIZE); + + get_common_cache_info (&shared, &threads, core); + } + else if (cpu_features->basic.kind == arch_kind_amd) + { + data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); + core = handle_amd (_SC_LEVEL2_CACHE_SIZE); + shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); + + level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); + level1_dcache_size = data; + level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); + level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); + level2_cache_size = core; + level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC); + level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE); + level3_cache_size = shared; + level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC); + level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE); + + /* Get maximum extended function. */ + __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); + + if (shared <= 0) + /* No shared L3 cache. All we have is the L2 cache. */ + shared = core; + else + { + /* Figure out the number of logical threads that share L3. */ + if (max_cpuid_ex >= 0x80000008) + { + /* Get width of APIC ID. */ + __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); + threads = 1 << ((ecx >> 12) & 0x0f); + } + + if (threads == 0 || cpu_features->basic.family >= 0x17) + { + /* If APIC ID width is not available, use logical + processor count. */ + __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); + + if ((edx & (1 << 28)) != 0) + threads = (ebx >> 16) & 0xff; + } + + /* Cap usage of highest cache level to the number of + supported threads. */ + if (threads > 0) + shared /= threads; + + /* Get shared cache per ccx for Zen architectures. */ + if (cpu_features->basic.family >= 0x17) + { + unsigned int eax; + + /* Get number of threads share the L3 cache in CCX. */ + __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); + + unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; + shared *= threads_per_ccx; + } + else + { + /* Account for exclusive L2 and L3 caches. */ + shared += core; + } + } + } + + cpu_features->level1_icache_size = level1_icache_size; + cpu_features->level1_dcache_size = level1_dcache_size; + cpu_features->level1_dcache_assoc = level1_dcache_assoc; + cpu_features->level1_dcache_linesize = level1_dcache_linesize; + cpu_features->level2_cache_size = level2_cache_size; + cpu_features->level2_cache_assoc = level2_cache_assoc; + cpu_features->level2_cache_linesize = level2_cache_linesize; + cpu_features->level3_cache_size = level3_cache_size; + cpu_features->level3_cache_assoc = level3_cache_assoc; + cpu_features->level3_cache_linesize = level3_cache_linesize; + cpu_features->level4_cache_size = level4_cache_size; + + /* The default setting for the non_temporal threshold is 3/4 of one + thread's share of the chip's cache. For most Intel and AMD processors + with an initial release date between 2017 and 2020, a thread's typical + share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 + threshold leaves 125 KBytes to 500 KBytes of the thread's data + in cache after a maximum temporal copy, which will maintain + in cache a reasonable portion of the thread's stack and other + active data. If the threshold is set higher than one thread's + share of the cache, it has a substantial risk of negatively + impacting the performance of other threads running on the chip. */ + unsigned long int non_temporal_threshold = shared * 3 / 4; + +#if HAVE_TUNABLES + /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ + unsigned int minimum_rep_movsb_threshold; +#endif + /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */ + unsigned int rep_movsb_threshold; + if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) + && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512)) + { + rep_movsb_threshold = 2048 * (64 / 16); +#if HAVE_TUNABLES + minimum_rep_movsb_threshold = 64 * 8; +#endif + } + else if (CPU_FEATURE_PREFERRED_P (cpu_features, + AVX_Fast_Unaligned_Load)) + { + rep_movsb_threshold = 2048 * (32 / 16); +#if HAVE_TUNABLES + minimum_rep_movsb_threshold = 32 * 8; +#endif + } + else + { + rep_movsb_threshold = 2048 * (16 / 16); +#if HAVE_TUNABLES + minimum_rep_movsb_threshold = 16 * 8; +#endif + } + + /* The default threshold to use Enhanced REP STOSB. */ + unsigned long int rep_stosb_threshold = 2048; + +#if HAVE_TUNABLES + long int tunable_size; + + tunable_size = TUNABLE_GET (x86_data_cache_size, long int, NULL); + /* NB: Ignore the default value 0. */ + if (tunable_size != 0) + data = tunable_size; + + tunable_size = TUNABLE_GET (x86_shared_cache_size, long int, NULL); + /* NB: Ignore the default value 0. */ + if (tunable_size != 0) + shared = tunable_size; + + tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); + /* NB: Ignore the default value 0. */ + if (tunable_size != 0) + non_temporal_threshold = tunable_size; + + tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); + if (tunable_size > minimum_rep_movsb_threshold) + rep_movsb_threshold = tunable_size; + + /* NB: The default value of the x86_rep_stosb_threshold tunable is the + same as the default value of __x86_rep_stosb_threshold and the + minimum value is fixed. */ + rep_stosb_threshold = TUNABLE_GET (x86_rep_stosb_threshold, + long int, NULL); + + TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, long int, data, + 0, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, long int, shared, + 0, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, long int, + non_temporal_threshold, 0, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, long int, + rep_movsb_threshold, + minimum_rep_movsb_threshold, (long int) -1); + TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, long int, + rep_stosb_threshold, 1, (long int) -1); +#endif + + cpu_features->data_cache_size = data; + cpu_features->shared_cache_size = shared; + cpu_features->non_temporal_threshold = non_temporal_threshold; + cpu_features->rep_movsb_threshold = rep_movsb_threshold; + cpu_features->rep_stosb_threshold = rep_stosb_threshold; +} diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 99e7ee08cf..50cb5a15f5 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -149,6 +149,28 @@ struct cpu_features unsigned long int rep_movsb_threshold; /* Threshold to use "rep stosb". */ unsigned long int rep_stosb_threshold; + /* _SC_LEVEL1_ICACHE_SIZE. */ + unsigned long int level1_icache_size; + /* _SC_LEVEL1_DCACHE_SIZE. */ + unsigned long int level1_dcache_size; + /* _SC_LEVEL1_DCACHE_ASSOC. */ + unsigned long int level1_dcache_assoc; + /* _SC_LEVEL1_DCACHE_LINESIZE. */ + unsigned long int level1_dcache_linesize; + /* _SC_LEVEL2_CACHE_ASSOC. */ + unsigned long int level2_cache_size; + /* _SC_LEVEL2_DCACHE_ASSOC. */ + unsigned long int level2_cache_assoc; + /* _SC_LEVEL2_CACHE_LINESIZE. */ + unsigned long int level2_cache_linesize; + /* /_SC_LEVEL3_CACHE_SIZE. */ + unsigned long int level3_cache_size; + /* _SC_LEVEL3_CACHE_ASSOC. */ + unsigned long int level3_cache_assoc; + /* _SC_LEVEL3_CACHE_LINESIZE. */ + unsigned long int level3_cache_linesize; + /* /_SC_LEVEL4_CACHE_SIZE. */ + unsigned long int level4_cache_size; }; #if defined (_LIBC) && !IS_IN (nonlib) -- 2.29.2 ^ permalink raw reply [flat|nested] 12+ messages in thread
* V4 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values 2020-10-31 15:44 V4 [PATCH 0/2] ld.so: Add --list-tunables to print tunable values H.J. Lu 2020-10-31 15:44 ` V4 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features H.J. Lu @ 2020-10-31 15:44 ` H.J. Lu 2021-01-14 18:35 ` Adhemerval Zanella 1 sibling, 1 reply; 12+ messages in thread From: H.J. Lu @ 2020-10-31 15:44 UTC (permalink / raw) To: libc-alpha; +Cc: Florian Weimer, Carlos O'Donell Pass --list-tunables to ld.so to print tunables with min and max values. --- NEWS | 2 ++ elf/Makefile | 8 ++++++++ elf/dl-main.h | 2 +- elf/dl-tunables.c | 36 ++++++++++++++++++++++++++++++++++++ elf/dl-tunables.h | 2 ++ elf/dl-usage.c | 7 ++++++- elf/rtld.c | 23 +++++++++++++++++++++++ manual/tunables.texi | 37 +++++++++++++++++++++++++++++++++++++ 8 files changed, 115 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 4307c4b1b0..a62e7307ef 100644 --- a/NEWS +++ b/NEWS @@ -9,6 +9,8 @@ Version 2.33 Major new features: +* Pass --list-tunables to ld.so to print tunable values. + * The dynamic linker accepts the --argv0 argument and provides opportunity to change argv[0] string. diff --git a/elf/Makefile b/elf/Makefile index f10cc59e7c..86b282a32b 100644 --- a/elf/Makefile +++ b/elf/Makefile @@ -44,6 +44,10 @@ dl-routines += dl-tunables tunables-type = $(addprefix TUNABLES_FRONTEND_,$(have-tunables)) CPPFLAGS-dl-tunables.c += -DTUNABLES_FRONTEND=$(tunables-type) +ifeq (yesyes,$(build-shared)$(run-built-tests)) +tests-special += $(objpfx)list-tunables.out +endif + # Make sure that the compiler does not insert any library calls in tunables # code paths. ifeq (yes,$(have-loop-to-function)) @@ -1812,3 +1816,7 @@ $(objpfx)argv0test.out: tst-rtld-argv0.sh $(objpfx)ld.so \ '$(test-wrapper-env)' '$(run_program_env)' \ '$(rpath-link)' 'test-argv0' > $@; \ $(evaluate-test) + +$(objpfx)list-tunables.out: $(objpfx)ld.so + $(objpfx)ld.so --list-tunables > $@; \ + $(evaluate-test) diff --git a/elf/dl-main.h b/elf/dl-main.h index b51256d3b4..f229867b8e 100644 --- a/elf/dl-main.h +++ b/elf/dl-main.h @@ -63,7 +63,7 @@ struct audit_list enum rtld_mode { rtld_mode_normal, rtld_mode_list, rtld_mode_verify, rtld_mode_trace, - rtld_mode_help, + rtld_mode_list_tunables, rtld_mode_help, }; /* Aggregated state information extracted from environment variables diff --git a/elf/dl-tunables.c b/elf/dl-tunables.c index 2ba2844075..048601b704 100644 --- a/elf/dl-tunables.c +++ b/elf/dl-tunables.c @@ -398,6 +398,42 @@ __tunables_init (char **envp) } } +void +__tunables_print (void) +{ + for (int i = 0; i < sizeof (tunable_list) / sizeof (tunable_t); i++) + { + tunable_t *cur = &tunable_list[i]; + _dl_printf ("%s: ", cur->name); + switch (cur->type.type_code) + { + case TUNABLE_TYPE_INT_32: + _dl_printf ("%d (min: %d, max: %d)\n", + (int) cur->val.numval, + (int) cur->type.min, + (int) cur->type.max); + break; + case TUNABLE_TYPE_UINT_64: + _dl_printf ("0x%lx (min: 0x%lx, max: 0x%lx)\n", + (long int) cur->val.numval, + (long int) cur->type.min, + (long int) cur->type.max); + break; + case TUNABLE_TYPE_SIZE_T: + _dl_printf ("0x%Zx (min: 0x%Zx, max: 0x%Zx)\n", + (size_t) cur->val.numval, + (size_t) cur->type.min, + (size_t) cur->type.max); + break; + case TUNABLE_TYPE_STRING: + _dl_printf ("%s\n", cur->val.strval ? cur->val.strval : ""); + break; + default: + __builtin_unreachable (); + } + } +} + /* Set the tunable value. This is called by the module that the tunable exists in. */ void diff --git a/elf/dl-tunables.h b/elf/dl-tunables.h index 550b0cc7f4..4a0c90f3e0 100644 --- a/elf/dl-tunables.h +++ b/elf/dl-tunables.h @@ -69,9 +69,11 @@ typedef struct _tunable tunable_t; # include "dl-tunable-list.h" extern void __tunables_init (char **); +extern void __tunables_print (void); extern void __tunable_get_val (tunable_id_t, void *, tunable_callback_t); extern void __tunable_set_val (tunable_id_t, void *, void *, void *); rtld_hidden_proto (__tunables_init) +rtld_hidden_proto (__tunables_print) rtld_hidden_proto (__tunable_get_val) rtld_hidden_proto (__tunable_set_val) diff --git a/elf/dl-usage.c b/elf/dl-usage.c index 796ad38b43..3ce19fb892 100644 --- a/elf/dl-usage.c +++ b/elf/dl-usage.c @@ -190,7 +190,12 @@ setting environment variables (which would be inherited by subprocesses).\n\ in LIST\n\ --audit LIST use objects named in LIST as auditors\n\ --preload LIST preload objects named in LIST\n\ - --argv0 STRING set argv[0] to STRING before running\n\ + --argv0 STRING set argv[0] to STRING before running\n" +#if HAVE_TUNABLES +"\ + --list-tunables list all tunables with minimum and maximum values\n" +#endif +"\ --help display this help and exit\n\ --version output version information and exit\n\ \n\ diff --git a/elf/rtld.c b/elf/rtld.c index 5d117d0d2c..33993a6f8b 100644 --- a/elf/rtld.c +++ b/elf/rtld.c @@ -49,6 +49,10 @@ #include <libc-early-init.h> #include <dl-main.h> +#if HAVE_TUNABLES +# include <dl-tunables.h> +#endif + #include <assert.h> /* Only enables rtld profiling for architectures which provides non generic @@ -1248,6 +1252,16 @@ dl_main (const ElfW(Phdr) *phdr, _dl_argc -= 2; _dl_argv += 2; } +#if HAVE_TUNABLES + else if (! strcmp (_dl_argv[1], "--list-tunables")) + { + state.mode = rtld_mode_list_tunables; + + ++_dl_skip_args; + --_dl_argc; + ++_dl_argv; + } +#endif else if (strcmp (_dl_argv[1], "--help") == 0) { state.mode = rtld_mode_help; @@ -1268,6 +1282,15 @@ dl_main (const ElfW(Phdr) *phdr, else break; +#if HAVE_TUNABLES + if (__builtin_expect (state.mode, rtld_mode_normal) + == rtld_mode_list_tunables) + { + __tunables_print (); + _exit (0); + } +#endif + /* If we have no further argument the program was called incorrectly. Grant the user some education. */ if (_dl_argc < 2) diff --git a/manual/tunables.texi b/manual/tunables.texi index d72d7a5ec0..924dac8876 100644 --- a/manual/tunables.texi +++ b/manual/tunables.texi @@ -28,6 +28,43 @@ Finally, the set of tunables available may vary between distributions as the tunables feature allows distributions to add their own tunables under their own namespace. +Passing @option{--list-tunables} to the dynamic loader to print all +tunables with minimum and maximum values: + +@example +$ /lib64/ld-linux-x86-64.so.2 --list-tunables +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) +glibc.elision.skip_lock_after_retries: 3 (min: -2147483648, max: 2147483647) +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.malloc.perturb: 0 (min: 0, max: 255) +glibc.cpu.x86_shared_cache_size: 0x100000 (min: 0x0, max: 0xffffffffffffffff) +glibc.elision.tries: 3 (min: -2147483648, max: 2147483647) +glibc.elision.enable: 0 (min: 0, max: 1) +glibc.cpu.x86_rep_movsb_threshold: 0x800 (min: 0x100, max: 0xffffffffffffffff) +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647) +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffffffffffff) +glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x0, max: 0xffffffffffffffff) +glibc.cpu.x86_shstk: +glibc.cpu.hwcap_mask: 0x6 (min: 0x0, max: 0xffffffffffffffff) +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) +glibc.elision.skip_trylock_internal_abort: 3 (min: -2147483648, max: 2147483647) +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.cpu.x86_ibt: +glibc.cpu.hwcaps: +glibc.elision.skip_lock_internal_abort: 3 (min: -2147483648, max: 2147483647) +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0xffffffffffffffff) +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.cpu.x86_data_cache_size: 0x8000 (min: 0x0, max: 0xffffffffffffffff) +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0xffffffffffffffff) +glibc.pthread.mutex_spin_count: 100 (min: 0, max: 32767) +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0xffffffffffffffff) +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0xffffffffffffffff) +glibc.malloc.check: 0 (min: 0, max: 3) +@end example + @menu * Tunable names:: The structure of a tunable name * Memory Allocation Tunables:: Tunables in the memory allocation subsystem -- 2.28.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: V4 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values 2020-10-31 15:44 ` V4 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values H.J. Lu @ 2021-01-14 18:35 ` Adhemerval Zanella 2021-01-14 22:25 ` V5 " H.J. Lu 0 siblings, 1 reply; 12+ messages in thread From: Adhemerval Zanella @ 2021-01-14 18:35 UTC (permalink / raw) To: libc-alpha, H.J. Lu; +Cc: Florian Weimer On 31/10/2020 12:44, H.J. Lu via Libc-alpha wrote: > Pass --list-tunables to ld.so to print tunables with min and max values. > --- > NEWS | 2 ++ > elf/Makefile | 8 ++++++++ > elf/dl-main.h | 2 +- > elf/dl-tunables.c | 36 ++++++++++++++++++++++++++++++++++++ > elf/dl-tunables.h | 2 ++ > elf/dl-usage.c | 7 ++++++- > elf/rtld.c | 23 +++++++++++++++++++++++ > manual/tunables.texi | 37 +++++++++++++++++++++++++++++++++++++ > 8 files changed, 115 insertions(+), 2 deletions(-) > > diff --git a/NEWS b/NEWS > index 4307c4b1b0..a62e7307ef 100644 > --- a/NEWS > +++ b/NEWS > @@ -9,6 +9,8 @@ Version 2.33 > > Major new features: > > +* Pass --list-tunables to ld.so to print tunable values. > + Maybe use a similar sentence as for argv0: * The dynamic linker accepts the --list-tunables argument which prints all the supported tunables. This option is disable is glibc is configured with tunables disabled (--enable-tunables=no). > * The dynamic linker accepts the --argv0 argument and provides opportunity > to change argv[0] string. > > diff --git a/elf/Makefile b/elf/Makefile > index f10cc59e7c..86b282a32b 100644 > --- a/elf/Makefile > +++ b/elf/Makefile > @@ -44,6 +44,10 @@ dl-routines += dl-tunables > tunables-type = $(addprefix TUNABLES_FRONTEND_,$(have-tunables)) > CPPFLAGS-dl-tunables.c += -DTUNABLES_FRONTEND=$(tunables-type) > > +ifeq (yesyes,$(build-shared)$(run-built-tests)) > +tests-special += $(objpfx)list-tunables.out > +endif > + > # Make sure that the compiler does not insert any library calls in tunables > # code paths. Ok, it is enabled iff 'ifneq (no,$(have-tunables))'. > ifeq (yes,$(have-loop-to-function)) > @@ -1812,3 +1816,7 @@ $(objpfx)argv0test.out: tst-rtld-argv0.sh $(objpfx)ld.so \ > '$(test-wrapper-env)' '$(run_program_env)' \ > '$(rpath-link)' 'test-argv0' > $@; \ > $(evaluate-test) > + > +$(objpfx)list-tunables.out: $(objpfx)ld.so > + $(objpfx)ld.so --list-tunables > $@; \ > + $(evaluate-test) Maybe at least check for a tunable with a default value which be equal to all architecture, like glibc.rtld.nns, glibc.malloc.perturb, etc? > diff --git a/elf/dl-main.h b/elf/dl-main.h > index b51256d3b4..f229867b8e 100644 > --- a/elf/dl-main.h > +++ b/elf/dl-main.h > @@ -63,7 +63,7 @@ struct audit_list > enum rtld_mode > { > rtld_mode_normal, rtld_mode_list, rtld_mode_verify, rtld_mode_trace, > - rtld_mode_help, > + rtld_mode_list_tunables, rtld_mode_help, > }; > > /* Aggregated state information extracted from environment variables Ok. > diff --git a/elf/dl-tunables.c b/elf/dl-tunables.c > index 2ba2844075..048601b704 100644 > --- a/elf/dl-tunables.c > +++ b/elf/dl-tunables.c > @@ -398,6 +398,42 @@ __tunables_init (char **envp) > } > } > > +void > +__tunables_print (void) > +{ > + for (int i = 0; i < sizeof (tunable_list) / sizeof (tunable_t); i++) Use array_length here. > + { > + tunable_t *cur = &tunable_list[i]; Maybe use a const modifier here. > + _dl_printf ("%s: ", cur->name); > + switch (cur->type.type_code) > + { > + case TUNABLE_TYPE_INT_32: > + _dl_printf ("%d (min: %d, max: %d)\n", > + (int) cur->val.numval, > + (int) cur->type.min, > + (int) cur->type.max); > + break; > + case TUNABLE_TYPE_UINT_64: > + _dl_printf ("0x%lx (min: 0x%lx, max: 0x%lx)\n", > + (long int) cur->val.numval, > + (long int) cur->type.min, > + (long int) cur->type.max); > + break; > + case TUNABLE_TYPE_SIZE_T: > + _dl_printf ("0x%Zx (min: 0x%Zx, max: 0x%Zx)\n", > + (size_t) cur->val.numval, > + (size_t) cur->type.min, > + (size_t) cur->type.max); > + break; > + case TUNABLE_TYPE_STRING: > + _dl_printf ("%s\n", cur->val.strval ? cur->val.strval : ""); > + break; > + default: > + __builtin_unreachable (); > + } > + } > +} > + Ok, it should be ok to use '%d' for signed and 'lx' for unsigned. > /* Set the tunable value. This is called by the module that the tunable exists > in. */ > void > diff --git a/elf/dl-tunables.h b/elf/dl-tunables.h > index 550b0cc7f4..4a0c90f3e0 100644 > --- a/elf/dl-tunables.h > +++ b/elf/dl-tunables.h > @@ -69,9 +69,11 @@ typedef struct _tunable tunable_t; > # include "dl-tunable-list.h" > > extern void __tunables_init (char **); > +extern void __tunables_print (void); > extern void __tunable_get_val (tunable_id_t, void *, tunable_callback_t); > extern void __tunable_set_val (tunable_id_t, void *, void *, void *); > rtld_hidden_proto (__tunables_init) > +rtld_hidden_proto (__tunables_print) > rtld_hidden_proto (__tunable_get_val) > rtld_hidden_proto (__tunable_set_val) > Ok. > diff --git a/elf/dl-usage.c b/elf/dl-usage.c > index 796ad38b43..3ce19fb892 100644 > --- a/elf/dl-usage.c > +++ b/elf/dl-usage.c > @@ -190,7 +190,12 @@ setting environment variables (which would be inherited by subprocesses).\n\ > in LIST\n\ > --audit LIST use objects named in LIST as auditors\n\ > --preload LIST preload objects named in LIST\n\ > - --argv0 STRING set argv[0] to STRING before running\n\ > + --argv0 STRING set argv[0] to STRING before running\n" > +#if HAVE_TUNABLES > +"\ > + --list-tunables list all tunables with minimum and maximum values\n" > +#endif > +"\ > --help display this help and exit\n\ > --version output version information and exit\n\ > \n\ Ok. > diff --git a/elf/rtld.c b/elf/rtld.c > index 5d117d0d2c..33993a6f8b 100644 > --- a/elf/rtld.c > +++ b/elf/rtld.c > @@ -49,6 +49,10 @@ > #include <libc-early-init.h> > #include <dl-main.h> > > +#if HAVE_TUNABLES > +# include <dl-tunables.h> > +#endif > + You can include this header regadless of HAVE_TUNABLES (it handles it internally). > #include <assert.h> > > /* Only enables rtld profiling for architectures which provides non generic > @@ -1248,6 +1252,16 @@ dl_main (const ElfW(Phdr) *phdr, > _dl_argc -= 2; > _dl_argv += 2; > } > +#if HAVE_TUNABLES > + else if (! strcmp (_dl_argv[1], "--list-tunables")) > + { > + state.mode = rtld_mode_list_tunables; > + > + ++_dl_skip_args; > + --_dl_argc; > + ++_dl_argv; > + } > +#endif > else if (strcmp (_dl_argv[1], "--help") == 0) > { > state.mode = rtld_mode_help; > @@ -1268,6 +1282,15 @@ dl_main (const ElfW(Phdr) *phdr, > else > break; > > +#if HAVE_TUNABLES > + if (__builtin_expect (state.mode, rtld_mode_normal) > + == rtld_mode_list_tunables) Use if (__glibc_unlikely (state.mode == rtld_mode_list_tunables) > + { > + __tunables_print (); > + _exit (0); > + } > +#endif > + > /* If we have no further argument the program was called incorrectly. > Grant the user some education. */ > if (_dl_argc < 2) > diff --git a/manual/tunables.texi b/manual/tunables.texi > index d72d7a5ec0..924dac8876 100644 > --- a/manual/tunables.texi > +++ b/manual/tunables.texi > @@ -28,6 +28,43 @@ Finally, the set of tunables available may vary between distributions as > the tunables feature allows distributions to add their own tunables under > their own namespace. > > +Passing @option{--list-tunables} to the dynamic loader to print all > +tunables with minimum and maximum values: > + > +@example > +$ /lib64/ld-linux-x86-64.so.2 --list-tunables > +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) > +glibc.elision.skip_lock_after_retries: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.perturb: 0 (min: 0, max: 255) > +glibc.cpu.x86_shared_cache_size: 0x100000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.elision.tries: 3 (min: -2147483648, max: 2147483647) > +glibc.elision.enable: 0 (min: 0, max: 1) > +glibc.cpu.x86_rep_movsb_threshold: 0x800 (min: 0x100, max: 0xffffffffffffffff) > +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffffffffffff) > +glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_shstk: Trailing whitespace. > +glibc.cpu.hwcap_mask: 0x6 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > +glibc.elision.skip_trylock_internal_abort: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_ibt: Ditto. > +glibc.cpu.hwcaps: Ditto. > +glibc.elision.skip_lock_internal_abort: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0xffffffffffffffff) > +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_data_cache_size: 0x8000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0xffffffffffffffff) > +glibc.pthread.mutex_spin_count: 100 (min: 0, max: 32767) > +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.check: 0 (min: 0, max: 3) > +@end example > + > @menu > * Tunable names:: The structure of a tunable name > * Memory Allocation Tunables:: Tunables in the memory allocation subsystem > ^ permalink raw reply [flat|nested] 12+ messages in thread
* V5 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values 2021-01-14 18:35 ` Adhemerval Zanella @ 2021-01-14 22:25 ` H.J. Lu 2021-01-15 12:47 ` Adhemerval Zanella 2021-02-02 10:59 ` Andreas Schwab 0 siblings, 2 replies; 12+ messages in thread From: H.J. Lu @ 2021-01-14 22:25 UTC (permalink / raw) To: Adhemerval Zanella; +Cc: GNU C Library, Florian Weimer [-- Attachment #1: Type: text/plain, Size: 10718 bytes --] On Thu, Jan 14, 2021 at 10:35 AM Adhemerval Zanella <adhemerval.zanella@linaro.org> wrote: > > > > On 31/10/2020 12:44, H.J. Lu via Libc-alpha wrote: > > Pass --list-tunables to ld.so to print tunables with min and max values. > > --- > > NEWS | 2 ++ > > elf/Makefile | 8 ++++++++ > > elf/dl-main.h | 2 +- > > elf/dl-tunables.c | 36 ++++++++++++++++++++++++++++++++++++ > > elf/dl-tunables.h | 2 ++ > > elf/dl-usage.c | 7 ++++++- > > elf/rtld.c | 23 +++++++++++++++++++++++ > > manual/tunables.texi | 37 +++++++++++++++++++++++++++++++++++++ > > 8 files changed, 115 insertions(+), 2 deletions(-) > > > > diff --git a/NEWS b/NEWS > > index 4307c4b1b0..a62e7307ef 100644 > > --- a/NEWS > > +++ b/NEWS > > @@ -9,6 +9,8 @@ Version 2.33 > > > > Major new features: > > > > +* Pass --list-tunables to ld.so to print tunable values. > > + > > Maybe use a similar sentence as for argv0: > > * The dynamic linker accepts the --list-tunables argument which prints > all the supported tunables. This option is disable is glibc is > configured with tunables disabled (--enable-tunables=no). Fixed. > > * The dynamic linker accepts the --argv0 argument and provides opportunity > > to change argv[0] string. > > > > diff --git a/elf/Makefile b/elf/Makefile > > index f10cc59e7c..86b282a32b 100644 > > --- a/elf/Makefile > > +++ b/elf/Makefile > > @@ -44,6 +44,10 @@ dl-routines += dl-tunables > > tunables-type = $(addprefix TUNABLES_FRONTEND_,$(have-tunables)) > > CPPFLAGS-dl-tunables.c += -DTUNABLES_FRONTEND=$(tunables-type) > > > > +ifeq (yesyes,$(build-shared)$(run-built-tests)) > > +tests-special += $(objpfx)list-tunables.out > > +endif > > + > > # Make sure that the compiler does not insert any library calls in tunables > > # code paths. > > Ok, it is enabled iff 'ifneq (no,$(have-tunables))'. > > > ifeq (yes,$(have-loop-to-function)) > > @@ -1812,3 +1816,7 @@ $(objpfx)argv0test.out: tst-rtld-argv0.sh $(objpfx)ld.so \ > > '$(test-wrapper-env)' '$(run_program_env)' \ > > '$(rpath-link)' 'test-argv0' > $@; \ > > $(evaluate-test) > > + > > +$(objpfx)list-tunables.out: $(objpfx)ld.so > > + $(objpfx)ld.so --list-tunables > $@; \ > > + $(evaluate-test) > > Maybe at least check for a tunable with a default value which be > equal to all architecture, like glibc.rtld.nns, glibc.malloc.perturb, etc? I added elf/tst-rtld-list-tunables.exp and elf/tst-rtld-list-tunables.sh to compare against rtld and malloc tunables. It passed on i686, x32 and x86-64. > > diff --git a/elf/dl-main.h b/elf/dl-main.h > > index b51256d3b4..f229867b8e 100644 > > --- a/elf/dl-main.h > > +++ b/elf/dl-main.h > > @@ -63,7 +63,7 @@ struct audit_list > > enum rtld_mode > > { > > rtld_mode_normal, rtld_mode_list, rtld_mode_verify, rtld_mode_trace, > > - rtld_mode_help, > > + rtld_mode_list_tunables, rtld_mode_help, > > }; > > > > /* Aggregated state information extracted from environment variables > > Ok. > > > diff --git a/elf/dl-tunables.c b/elf/dl-tunables.c > > index 2ba2844075..048601b704 100644 > > --- a/elf/dl-tunables.c > > +++ b/elf/dl-tunables.c > > @@ -398,6 +398,42 @@ __tunables_init (char **envp) > > } > > } > > > > +void > > +__tunables_print (void) > > +{ > > + for (int i = 0; i < sizeof (tunable_list) / sizeof (tunable_t); i++) > > Use array_length here. Fixed. > > + { > > + tunable_t *cur = &tunable_list[i]; > > Maybe use a const modifier here. Fixed. > > + _dl_printf ("%s: ", cur->name); > > + switch (cur->type.type_code) > > + { > > + case TUNABLE_TYPE_INT_32: > > + _dl_printf ("%d (min: %d, max: %d)\n", > > + (int) cur->val.numval, > > + (int) cur->type.min, > > + (int) cur->type.max); > > + break; > > + case TUNABLE_TYPE_UINT_64: > > + _dl_printf ("0x%lx (min: 0x%lx, max: 0x%lx)\n", > > + (long int) cur->val.numval, > > + (long int) cur->type.min, > > + (long int) cur->type.max); > > + break; > > + case TUNABLE_TYPE_SIZE_T: > > + _dl_printf ("0x%Zx (min: 0x%Zx, max: 0x%Zx)\n", > > + (size_t) cur->val.numval, > > + (size_t) cur->type.min, > > + (size_t) cur->type.max); > > + break; > > + case TUNABLE_TYPE_STRING: > > + _dl_printf ("%s\n", cur->val.strval ? cur->val.strval : ""); > > + break; > > + default: > > + __builtin_unreachable (); > > + } > > + } > > +} > > + > > Ok, it should be ok to use '%d' for signed and 'lx' for unsigned. > > > /* Set the tunable value. This is called by the module that the tunable exists > > in. */ > > void > > diff --git a/elf/dl-tunables.h b/elf/dl-tunables.h > > index 550b0cc7f4..4a0c90f3e0 100644 > > --- a/elf/dl-tunables.h > > +++ b/elf/dl-tunables.h > > @@ -69,9 +69,11 @@ typedef struct _tunable tunable_t; > > # include "dl-tunable-list.h" > > > > extern void __tunables_init (char **); > > +extern void __tunables_print (void); > > extern void __tunable_get_val (tunable_id_t, void *, tunable_callback_t); > > extern void __tunable_set_val (tunable_id_t, void *, void *, void *); > > rtld_hidden_proto (__tunables_init) > > +rtld_hidden_proto (__tunables_print) > > rtld_hidden_proto (__tunable_get_val) > > rtld_hidden_proto (__tunable_set_val) > > > > Ok. > > > diff --git a/elf/dl-usage.c b/elf/dl-usage.c > > index 796ad38b43..3ce19fb892 100644 > > --- a/elf/dl-usage.c > > +++ b/elf/dl-usage.c > > @@ -190,7 +190,12 @@ setting environment variables (which would be inherited by subprocesses).\n\ > > in LIST\n\ > > --audit LIST use objects named in LIST as auditors\n\ > > --preload LIST preload objects named in LIST\n\ > > - --argv0 STRING set argv[0] to STRING before running\n\ > > + --argv0 STRING set argv[0] to STRING before running\n" > > +#if HAVE_TUNABLES > > +"\ > > + --list-tunables list all tunables with minimum and maximum values\n" > > +#endif > > +"\ > > --help display this help and exit\n\ > > --version output version information and exit\n\ > > \n\ > > Ok. > > > diff --git a/elf/rtld.c b/elf/rtld.c > > index 5d117d0d2c..33993a6f8b 100644 > > --- a/elf/rtld.c > > +++ b/elf/rtld.c > > @@ -49,6 +49,10 @@ > > #include <libc-early-init.h> > > #include <dl-main.h> > > > > +#if HAVE_TUNABLES > > +# include <dl-tunables.h> > > +#endif > > + > > You can include this header regadless of HAVE_TUNABLES (it handles it > internally). Fixed. > > #include <assert.h> > > > > /* Only enables rtld profiling for architectures which provides non generic > > @@ -1248,6 +1252,16 @@ dl_main (const ElfW(Phdr) *phdr, > > _dl_argc -= 2; > > _dl_argv += 2; > > } > > +#if HAVE_TUNABLES > > + else if (! strcmp (_dl_argv[1], "--list-tunables")) > > + { > > + state.mode = rtld_mode_list_tunables; > > + > > + ++_dl_skip_args; > > + --_dl_argc; > > + ++_dl_argv; > > + } > > +#endif > > else if (strcmp (_dl_argv[1], "--help") == 0) > > { > > state.mode = rtld_mode_help; > > @@ -1268,6 +1282,15 @@ dl_main (const ElfW(Phdr) *phdr, > > else > > break; > > > > +#if HAVE_TUNABLES > > + if (__builtin_expect (state.mode, rtld_mode_normal) > > + == rtld_mode_list_tunables) > > Use > > if (__glibc_unlikely (state.mode == rtld_mode_list_tunables) Fixed. > > + { > > + __tunables_print (); > > + _exit (0); > > + } > > +#endif > > + > > /* If we have no further argument the program was called incorrectly. > > Grant the user some education. */ > > if (_dl_argc < 2) > > diff --git a/manual/tunables.texi b/manual/tunables.texi > > index d72d7a5ec0..924dac8876 100644 > > --- a/manual/tunables.texi > > +++ b/manual/tunables.texi > > @@ -28,6 +28,43 @@ Finally, the set of tunables available may vary between distributions as > > the tunables feature allows distributions to add their own tunables under > > their own namespace. > > > > +Passing @option{--list-tunables} to the dynamic loader to print all > > +tunables with minimum and maximum values: > > + > > +@example > > +$ /lib64/ld-linux-x86-64.so.2 --list-tunables > > +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) > > +glibc.elision.skip_lock_after_retries: 3 (min: -2147483648, max: 2147483647) > > +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.malloc.perturb: 0 (min: 0, max: 255) > > +glibc.cpu.x86_shared_cache_size: 0x100000 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.elision.tries: 3 (min: -2147483648, max: 2147483647) > > +glibc.elision.enable: 0 (min: 0, max: 1) > > +glibc.cpu.x86_rep_movsb_threshold: 0x800 (min: 0x100, max: 0xffffffffffffffff) > > +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647) > > +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffffffffffff) > > +glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.cpu.x86_shstk: > > Trailing whitespace. Fixed. > > +glibc.cpu.hwcap_mask: 0x6 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > > +glibc.elision.skip_trylock_internal_abort: 3 (min: -2147483648, max: 2147483647) > > +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.cpu.x86_ibt: > > Ditto. Fixed. > > +glibc.cpu.hwcaps: > > Ditto. Fixed. > > +glibc.elision.skip_lock_internal_abort: 3 (min: -2147483648, max: 2147483647) > > +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0xffffffffffffffff) > > +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.cpu.x86_data_cache_size: 0x8000 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0xffffffffffffffff) > > +glibc.pthread.mutex_spin_count: 100 (min: 0, max: 32767) > > +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0xffffffffffffffff) > > +glibc.malloc.check: 0 (min: 0, max: 3) > > +@end example > > + > > @menu > > * Tunable names:: The structure of a tunable name > > * Memory Allocation Tunables:: Tunables in the memory allocation subsystem > > Here is the updated patch. OK for master? Thanks. -- H.J. [-- Attachment #2: 0001-ld.so-Add-list-tunables-to-print-tunable-values.patch --] [-- Type: application/x-patch, Size: 11587 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: V5 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values 2021-01-14 22:25 ` V5 " H.J. Lu @ 2021-01-15 12:47 ` Adhemerval Zanella 2021-02-02 10:59 ` Andreas Schwab 1 sibling, 0 replies; 12+ messages in thread From: Adhemerval Zanella @ 2021-01-15 12:47 UTC (permalink / raw) To: H.J. Lu; +Cc: GNU C Library, Florian Weimer On 14/01/2021 19:25, H.J. Lu wrote: > On Thu, Jan 14, 2021 at 10:35 AM Adhemerval Zanella > <adhemerval.zanella@linaro.org> wrote: >> >> >> >> On 31/10/2020 12:44, H.J. Lu via Libc-alpha wrote: > > Here is the updated patch. OK for master? > > Thanks. LGTM, thanks. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> > > From 2745fc527295ad735d14bdaf6052c40dc24772a8 Mon Sep 17 00:00:00 2001 > From: "H.J. Lu" <hjl.tools@gmail.com> > Date: Sun, 12 Jul 2020 06:04:53 -0700 > Subject: [PATCH] ld.so: Add --list-tunables to print tunable values > > Pass --list-tunables to ld.so to print tunables with min and max values. > --- > NEWS | 4 ++++ > elf/Makefile | 13 ++++++++++ > elf/dl-main.h | 2 +- > elf/dl-tunables.c | 43 ++++++++++++++++++++++++++++++++++ > elf/dl-tunables.h | 2 ++ > elf/dl-usage.c | 7 +++++- > elf/rtld.c | 19 +++++++++++++++ > elf/tst-rtld-list-tunables.exp | 14 +++++++++++ > elf/tst-rtld-list-tunables.sh | 34 +++++++++++++++++++++++++++ > manual/tunables.texi | 38 ++++++++++++++++++++++++++++++ > 10 files changed, 174 insertions(+), 2 deletions(-) > create mode 100644 elf/tst-rtld-list-tunables.exp > create mode 100755 elf/tst-rtld-list-tunables.sh > > diff --git a/NEWS b/NEWS > index face78cd10..d121f7df87 100644 > --- a/NEWS > +++ b/NEWS > @@ -9,6 +9,10 @@ Version 2.33 > > Major new features: > > +* The dynamic linker accepts the --list-tunables argument which prints > + all the supported tunables. This option is disable if glibc is > + configured with tunables disabled (--enable-tunables=no). > + > * The dynamic linker accepts the --argv0 argument and provides opportunity > to change argv[0] string. > Ok. > diff --git a/elf/Makefile b/elf/Makefile > index c41d11693b..0e46cab699 100644 > --- a/elf/Makefile > +++ b/elf/Makefile > @@ -45,6 +45,10 @@ dl-routines += dl-tunables > tunables-type = $(addprefix TUNABLES_FRONTEND_,$(have-tunables)) > CPPFLAGS-dl-tunables.c += -DTUNABLES_FRONTEND=$(tunables-type) > > +ifeq (yesyes,$(build-shared)$(run-built-tests)) > +tests-special += $(objpfx)list-tunables.out > +endif > + > # Make sure that the compiler does not insert any library calls in tunables > # code paths. > ifeq (yes,$(have-loop-to-function)) Ok. > @@ -1896,3 +1900,12 @@ $(objpfx)tst-glibc-hwcaps-mask.out: \ > # Generic dependency for sysdeps implementation of > # tst-glibc-hwcaps-cache. > $(objpfx)tst-glibc-hwcaps-cache.out: $(objpfx)tst-glibc-hwcaps > + > +$(objpfx)list-tunables.out: tst-rtld-list-tunables.sh $(objpfx)ld.so > + $(objpfx)ld.so --list-tunables > $@; \ > + $(evaluate-test) > + $(SHELL) $< $(objpfx)ld.so '$(test-wrapper-env)' \ > + '$(run_program_env)' > $(objpfx)/tst-rtld-list-tunables.out > + cmp tst-rtld-list-tunables.exp \ > + $(objpfx)/tst-rtld-list-tunables.out > $@; \ > + $(evaluate-test) Ok. > diff --git a/elf/dl-main.h b/elf/dl-main.h > index 0bccab165f..3a5e13c739 100644 > --- a/elf/dl-main.h > +++ b/elf/dl-main.h > @@ -63,7 +63,7 @@ struct audit_list > enum rtld_mode > { > rtld_mode_normal, rtld_mode_list, rtld_mode_verify, rtld_mode_trace, > - rtld_mode_help, > + rtld_mode_list_tunables, rtld_mode_help, > }; > > /* Aggregated state information extracted from environment variables Ok. > diff --git a/elf/dl-tunables.c b/elf/dl-tunables.c > index 9b4d737fb8..33be00e447 100644 > --- a/elf/dl-tunables.c > +++ b/elf/dl-tunables.c > @@ -26,6 +26,7 @@ > #include <sysdep.h> > #include <fcntl.h> > #include <ldsodefs.h> > +#include <array_length.h> > > #define TUNABLES_INTERNAL 1 > #include "dl-tunables.h" > @@ -398,6 +399,48 @@ __tunables_init (char **envp) > } > } > > +void > +__tunables_print (void) > +{ > + for (int i = 0; i < array_length (tunable_list); i++) > + { > + const tunable_t *cur = &tunable_list[i]; > + if (cur->type.type_code == TUNABLE_TYPE_STRING > + && cur->val.strval == NULL) > + _dl_printf ("%s:\n", cur->name); > + else > + { > + _dl_printf ("%s: ", cur->name); > + switch (cur->type.type_code) > + { > + case TUNABLE_TYPE_INT_32: > + _dl_printf ("%d (min: %d, max: %d)\n", > + (int) cur->val.numval, > + (int) cur->type.min, > + (int) cur->type.max); > + break; > + case TUNABLE_TYPE_UINT_64: > + _dl_printf ("0x%lx (min: 0x%lx, max: 0x%lx)\n", > + (long int) cur->val.numval, > + (long int) cur->type.min, > + (long int) cur->type.max); > + break; > + case TUNABLE_TYPE_SIZE_T: > + _dl_printf ("0x%Zx (min: 0x%Zx, max: 0x%Zx)\n", > + (size_t) cur->val.numval, > + (size_t) cur->type.min, > + (size_t) cur->type.max); > + break; > + case TUNABLE_TYPE_STRING: > + _dl_printf ("%s\n", cur->val.strval); > + break; > + default: > + __builtin_unreachable (); > + } > + } > + } > +} > + > /* Set the tunable value. This is called by the module that the tunable exists > in. */ > void Ok. > diff --git a/elf/dl-tunables.h b/elf/dl-tunables.h > index 518342a300..dfa16c1977 100644 > --- a/elf/dl-tunables.h > +++ b/elf/dl-tunables.h > @@ -69,9 +69,11 @@ typedef struct _tunable tunable_t; > # include "dl-tunable-list.h" > > extern void __tunables_init (char **); > +extern void __tunables_print (void); > extern void __tunable_get_val (tunable_id_t, void *, tunable_callback_t); > extern void __tunable_set_val (tunable_id_t, void *, void *, void *); > rtld_hidden_proto (__tunables_init) > +rtld_hidden_proto (__tunables_print) > rtld_hidden_proto (__tunable_get_val) > rtld_hidden_proto (__tunable_set_val) > Ok. > diff --git a/elf/dl-usage.c b/elf/dl-usage.c > index 907f068cfb..6e26818bd7 100644 > --- a/elf/dl-usage.c > +++ b/elf/dl-usage.c > @@ -255,7 +255,12 @@ setting environment variables (which would be inherited by subprocesses).\n\ > in LIST\n\ > --audit LIST use objects named in LIST as auditors\n\ > --preload LIST preload objects named in LIST\n\ > - --argv0 STRING set argv[0] to STRING before running\n\ > + --argv0 STRING set argv[0] to STRING before running\n" > +#if HAVE_TUNABLES > +"\ > + --list-tunables list all tunables with minimum and maximum values\n" > +#endif > +"\ > --help display this help and exit\n\ > --version output version information and exit\n\ > \n\ Ok. > diff --git a/elf/rtld.c b/elf/rtld.c > index 8d9add90e3..596b6ac3d9 100644 > --- a/elf/rtld.c > +++ b/elf/rtld.c > @@ -50,6 +50,7 @@ > #include <dl-main.h> > #include <list.h> > #include <gnu/lib-names.h> > +#include <dl-tunables.h> > > #include <assert.h> > > @@ -1276,6 +1277,16 @@ dl_main (const ElfW(Phdr) *phdr, > _dl_argc -= 2; > _dl_argv += 2; > } > +#if HAVE_TUNABLES > + else if (! strcmp (_dl_argv[1], "--list-tunables")) > + { > + state.mode = rtld_mode_list_tunables; > + > + ++_dl_skip_args; > + --_dl_argc; > + ++_dl_argv; > + } > +#endif > else if (strcmp (_dl_argv[1], "--help") == 0) > { > state.mode = rtld_mode_help; > @@ -1296,6 +1307,14 @@ dl_main (const ElfW(Phdr) *phdr, > else > break; > > +#if HAVE_TUNABLES > + if (__glibc_unlikely (state.mode == rtld_mode_list_tunables)) > + { > + __tunables_print (); > + _exit (0); > + } > +#endif > + > /* If we have no further argument the program was called incorrectly. > Grant the user some education. */ > if (_dl_argc < 2) Ok. > diff --git a/elf/tst-rtld-list-tunables.exp b/elf/tst-rtld-list-tunables.exp > new file mode 100644 > index 0000000000..4f3f7ee4e3 > --- /dev/null > +++ b/elf/tst-rtld-list-tunables.exp > @@ -0,0 +1,14 @@ > +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0x[f]+) > +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0x[f]+) > +glibc.malloc.check: 0 (min: 0, max: 3) > +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.perturb: 0 (min: 0, max: 255) > +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) > +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0x[f]+) Ok, it seems to be to common ones. > diff --git a/elf/tst-rtld-list-tunables.sh b/elf/tst-rtld-list-tunables.sh > new file mode 100755 > index 0000000000..e7bbdde949 > --- /dev/null > +++ b/elf/tst-rtld-list-tunables.sh > @@ -0,0 +1,34 @@ > +#!/bin/sh > +# Test for --list-tunables option ld.so. > +# Copyright (C) 2021 Free Software Foundation, Inc. > +# This file is part of the GNU C Library. > +# > +# The GNU C Library is free software; you can redistribute it and/or > +# modify it under the terms of the GNU Lesser General Public > +# License as published by the Free Software Foundation; either > +# version 2.1 of the License, or (at your option) any later version. > +# > +# The GNU C Library is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > +# Lesser General Public License for more details. > +# > +# You should have received a copy of the GNU Lesser General Public > +# License along with the GNU C Library; if not, see > +# <https://www.gnu.org/licenses/>. > + > +set -e > + > +rtld=$1 > +test_wrapper_env=$2 > +run_program_env=$3 > + > +LC_ALL=C > +export LC_ALL > + > +${test_wrapper_env} \ > +${run_program_env} \ > +$rtld --list-tunables \ > +| sort -u \ > +| egrep "(rtld|malloc)" \ > +| sed -e "s/0xf\+/0x[f]+/" Ok. > diff --git a/manual/tunables.texi b/manual/tunables.texi > index 1bbdc88281..1b746c0fa1 100644 > --- a/manual/tunables.texi > +++ b/manual/tunables.texi > @@ -28,6 +28,44 @@ Finally, the set of tunables available may vary between distributions as > the tunables feature allows distributions to add their own tunables under > their own namespace. > > +Passing @option{--list-tunables} to the dynamic loader to print all > +tunables with minimum and maximum values: > + > +@example > +$ /lib64/ld-linux-x86-64.so.2 --list-tunables > +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) > +glibc.elision.skip_lock_after_retries: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.perturb: 0 (min: 0, max: 255) > +glibc.cpu.x86_shared_cache_size: 0x100000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.mem.tagging: 0 (min: 0, max: 255) > +glibc.elision.tries: 3 (min: -2147483648, max: 2147483647) > +glibc.elision.enable: 0 (min: 0, max: 1) > +glibc.cpu.x86_rep_movsb_threshold: 0x1000 (min: 0x100, max: 0xffffffffffffffff) > +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffffffffffff) > +glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_shstk: > +glibc.cpu.hwcap_mask: 0x6 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > +glibc.elision.skip_trylock_internal_abort: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_ibt: > +glibc.cpu.hwcaps: > +glibc.elision.skip_lock_internal_abort: 3 (min: -2147483648, max: 2147483647) > +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0xffffffffffffffff) > +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_data_cache_size: 0x8000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0xffffffffffffffff) > +glibc.pthread.mutex_spin_count: 100 (min: 0, max: 32767) > +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0xffffffffffffffff) > +glibc.malloc.check: 0 (min: 0, max: 3) > +@end example > + > @menu > * Tunable names:: The structure of a tunable name > * Memory Allocation Tunables:: Tunables in the memory allocation subsystem > -- > 2.29.2 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: V5 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values 2021-01-14 22:25 ` V5 " H.J. Lu 2021-01-15 12:47 ` Adhemerval Zanella @ 2021-02-02 10:59 ` Andreas Schwab 2021-02-02 17:36 ` [PATCH] ld.so: Unset glibc tunables for --list-tunables test H.J. Lu 1 sibling, 1 reply; 12+ messages in thread From: Andreas Schwab @ 2021-02-02 10:59 UTC (permalink / raw) To: H.J. Lu via Libc-alpha; +Cc: Adhemerval Zanella, H.J. Lu, Florian Weimer On Jan 14 2021, H.J. Lu via Libc-alpha wrote: > diff --git a/elf/tst-rtld-list-tunables.exp b/elf/tst-rtld-list-tunables.exp > new file mode 100644 > index 0000000000..4f3f7ee4e3 > --- /dev/null > +++ b/elf/tst-rtld-list-tunables.exp > @@ -0,0 +1,14 @@ > +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0x[f]+) > +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0x[f]+) > +glibc.malloc.check: 0 (min: 0, max: 3) > +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.perturb: 0 (min: 0, max: 255) > +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0x[f]+) > +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) > +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0x[f]+) This won't match if MALLOC_PERTURB_ is set. Andreas. -- Andreas Schwab, schwab@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different." ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] ld.so: Unset glibc tunables for --list-tunables test 2021-02-02 10:59 ` Andreas Schwab @ 2021-02-02 17:36 ` H.J. Lu 2021-02-02 18:07 ` Andreas Schwab 0 siblings, 1 reply; 12+ messages in thread From: H.J. Lu @ 2021-02-02 17:36 UTC (permalink / raw) To: Andreas Schwab; +Cc: H.J. Lu via Libc-alpha, Adhemerval Zanella, Florian Weimer [-- Attachment #1: Type: text/plain, Size: 1332 bytes --] On Tue, Feb 2, 2021 at 2:59 AM Andreas Schwab <schwab@linux-m68k.org> wrote: > > On Jan 14 2021, H.J. Lu via Libc-alpha wrote: > > > diff --git a/elf/tst-rtld-list-tunables.exp b/elf/tst-rtld-list-tunables.exp > > new file mode 100644 > > index 0000000000..4f3f7ee4e3 > > --- /dev/null > > +++ b/elf/tst-rtld-list-tunables.exp > > @@ -0,0 +1,14 @@ > > +glibc.malloc.arena_max: 0x0 (min: 0x1, max: 0x[f]+) > > +glibc.malloc.arena_test: 0x0 (min: 0x1, max: 0x[f]+) > > +glibc.malloc.check: 0 (min: 0, max: 3) > > +glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > > +glibc.malloc.mmap_threshold: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.malloc.perturb: 0 (min: 0, max: 255) > > +glibc.malloc.tcache_count: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.malloc.tcache_max: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.malloc.tcache_unsorted_limit: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.malloc.trim_threshold: 0x0 (min: 0x0, max: 0x[f]+) > > +glibc.rtld.nns: 0x4 (min: 0x1, max: 0x10) > > +glibc.rtld.optional_static_tls: 0x200 (min: 0x0, max: 0x[f]+) > > This won't match if MALLOC_PERTURB_ is set. > > Andreas. Here is the patch to unset tunables and their aliases for --list-tunables test. OK for master? Thanks. -- H.J. [-- Attachment #2: 0001-ld.so-Unset-glibc-tunables-for-list-tunables-test.patch --] [-- Type: text/x-patch, Size: 915 bytes --] From 321acb682702dd6ee273207b7ce832f8133abbfa Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 2 Feb 2021 09:31:56 -0800 Subject: [PATCH] ld.so: Unset glibc tunables for --list-tunables test Unset glibc tunables and their aliases for --list-tunables test. --- elf/tst-rtld-list-tunables.sh | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/elf/tst-rtld-list-tunables.sh b/elf/tst-rtld-list-tunables.sh index e7bbdde949..78f4ed2ebb 100755 --- a/elf/tst-rtld-list-tunables.sh +++ b/elf/tst-rtld-list-tunables.sh @@ -26,6 +26,17 @@ run_program_env=$3 LC_ALL=C export LC_ALL +# Unset tunables and their aliases. +GLIBC_TUNABLES= +MALLOC_ARENA_MAX= +MALLOC_ARENA_TEST= +MALLOC_CHECK_= +MALLOC_MMAP_MAX_= +MALLOC_MMAP_THRESHOLD_= +MALLOC_PERTURB_= +MALLOC_TOP_PAD_= +MALLOC_TRIM_THRESHOLD_= + ${test_wrapper_env} \ ${run_program_env} \ $rtld --list-tunables \ -- 2.29.2 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ld.so: Unset glibc tunables for --list-tunables test 2021-02-02 17:36 ` [PATCH] ld.so: Unset glibc tunables for --list-tunables test H.J. Lu @ 2021-02-02 18:07 ` Andreas Schwab 2021-02-02 18:12 ` [PATCH] tst-rtld-list-tunables.sh: Unset glibc tunables H.J. Lu 0 siblings, 1 reply; 12+ messages in thread From: Andreas Schwab @ 2021-02-02 18:07 UTC (permalink / raw) To: H.J. Lu; +Cc: H.J. Lu via Libc-alpha, Adhemerval Zanella, Florian Weimer On Feb 02 2021, H.J. Lu wrote: > From 321acb682702dd6ee273207b7ce832f8133abbfa Mon Sep 17 00:00:00 2001 > From: "H.J. Lu" <hjl.tools@gmail.com> > Date: Tue, 2 Feb 2021 09:31:56 -0800 > Subject: [PATCH] ld.so: Unset glibc tunables for --list-tunables test > > Unset glibc tunables and their aliases for --list-tunables test. Ok. I think the subject should use tst-rtld-list-tunables.sh as the topic prefix, since it doesn't change ld.so. Andreas. -- Andreas Schwab, schwab@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different." ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] tst-rtld-list-tunables.sh: Unset glibc tunables 2021-02-02 18:07 ` Andreas Schwab @ 2021-02-02 18:12 ` H.J. Lu 0 siblings, 0 replies; 12+ messages in thread From: H.J. Lu @ 2021-02-02 18:12 UTC (permalink / raw) To: Andreas Schwab; +Cc: H.J. Lu via Libc-alpha, Adhemerval Zanella, Florian Weimer [-- Attachment #1: Type: text/plain, Size: 624 bytes --] On Tue, Feb 2, 2021 at 10:07 AM Andreas Schwab <schwab@linux-m68k.org> wrote: > > On Feb 02 2021, H.J. Lu wrote: > > > From 321acb682702dd6ee273207b7ce832f8133abbfa Mon Sep 17 00:00:00 2001 > > From: "H.J. Lu" <hjl.tools@gmail.com> > > Date: Tue, 2 Feb 2021 09:31:56 -0800 > > Subject: [PATCH] ld.so: Unset glibc tunables for --list-tunables test > > > > Unset glibc tunables and their aliases for --list-tunables test. > > Ok. I think the subject should use tst-rtld-list-tunables.sh as the > topic prefix, since it doesn't change ld.so. Fixed. > Andreas. Here is the updated patch I am checking in. Thanks. -- H.J. [-- Attachment #2: 0001-tst-rtld-list-tunables.sh-Unset-glibc-tunables.patch --] [-- Type: text/x-patch, Size: 910 bytes --] From b711bfe5480bf55ae0cb18e03defc1e2a405e1b6 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 2 Feb 2021 09:31:56 -0800 Subject: [PATCH] tst-rtld-list-tunables.sh: Unset glibc tunables Unset glibc tunables and their aliases for --list-tunables test. --- elf/tst-rtld-list-tunables.sh | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/elf/tst-rtld-list-tunables.sh b/elf/tst-rtld-list-tunables.sh index e7bbdde949..78f4ed2ebb 100755 --- a/elf/tst-rtld-list-tunables.sh +++ b/elf/tst-rtld-list-tunables.sh @@ -26,6 +26,17 @@ run_program_env=$3 LC_ALL=C export LC_ALL +# Unset tunables and their aliases. +GLIBC_TUNABLES= +MALLOC_ARENA_MAX= +MALLOC_ARENA_TEST= +MALLOC_CHECK_= +MALLOC_MMAP_MAX_= +MALLOC_MMAP_THRESHOLD_= +MALLOC_PERTURB_= +MALLOC_TOP_PAD_= +MALLOC_TRIM_THRESHOLD_= + ${test_wrapper_env} \ ${run_program_env} \ $rtld --list-tunables \ -- 2.29.2 ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-02-02 18:12 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-31 15:44 V4 [PATCH 0/2] ld.so: Add --list-tunables to print tunable values H.J. Lu 2020-10-31 15:44 ` V4 [PATCH 1/2] x86: Move x86 processor cache info to cpu_features H.J. Lu 2021-01-14 14:13 ` Adhemerval Zanella 2021-01-14 19:28 ` V5 " H.J. Lu 2020-10-31 15:44 ` V4 [PATCH 2/2] ld.so: Add --list-tunables to print tunable values H.J. Lu 2021-01-14 18:35 ` Adhemerval Zanella 2021-01-14 22:25 ` V5 " H.J. Lu 2021-01-15 12:47 ` Adhemerval Zanella 2021-02-02 10:59 ` Andreas Schwab 2021-02-02 17:36 ` [PATCH] ld.so: Unset glibc tunables for --list-tunables test H.J. Lu 2021-02-02 18:07 ` Andreas Schwab 2021-02-02 18:12 ` [PATCH] tst-rtld-list-tunables.sh: Unset glibc tunables H.J. Lu
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).