Patch V2: add hp-timing support and minor fix

Patch V2: add hp-timing support and minor fix

[Huang Pei]

PATCH V2 1/2 : restrict hp-timing in rtld, since the time range of 32 
bit counter is too small(8 seconds, at half of CPU frequence 800Mhz)

PATCH V2 2/2 : merge previous Patch 2/3 and Patch 3/3, since they
both fix the same problem;

[PATCH V2 1/2] mips: add hp-timing support for MIPS R2

[Huang Pei]

MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
enough for glibc.

DO remember Linux/MIPS added emulation for 'rdhwr %0, $2'，when disabled
or not supported, which would make the precision worse. If you got
unreasonable result, check your CPU Manual for whether your CPU
implemented it or not
---
 sysdeps/mips/hp-timing.h | 44 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 sysdeps/mips/hp-timing.h

diff --git a/sysdeps/mips/hp-timing.h b/sysdeps/mips/hp-timing.h
new file mode 100644
index 0000000000..43cb695f2f
--- /dev/null
+++ b/sysdeps/mips/hp-timing.h
@@ -0,0 +1,44 @@
+/* High precision, low overhead timing functions. MIPS version.
+   Copyright (C) 2020 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Huang Pei <huangpei@loongson.cn>, 2020.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _HP_TIMING_MIPS_H
+#define _HP_TIMING_MIPS_H	1
+
+#if IS_IN(rtld) && __mips_isa_rev >= 2
+/* MIPS R2 always have the timestamp register. but it's got only 8 seconds
+ * range, assuming half of cpu frequence 800Mhz . Use it for ld.so
+ * profiling only*/
+#define HP_TIMING_INLINE	(1)
+
+/* We use 32bit values for the times.  */
+typedef unsigned int hp_timing_t;
+
+/* Read the cp0 count, this maybe inaccurate.  */
+#define HP_TIMING_NOW(Var) \
+  ({ unsigned int _count; \
+     asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \
+     (Var) = _count; })
+
+# include <hp-timing-common.h>
+
+#else
+# include <sysdeps/generic/hp-timing.h>
+#endif /* IS_IN(rtld) && __mips_isa_rev >= 2 */
+
+#endif /* hp-timing.h */
-- 
2.17.1

[PATCH V2 2/2] mips: remove register spill

[Huang Pei]

Before Linux/MIPS 2.6.36, kernel expected setting syscall number(aka
"li v0, #sys_number") right precedes "syscall", so the kernel syscall
restart sequence can use CP0 EPC - 4 to restart the syscall, because
kernel DID NOT save v0 during syscall handling. Linux 2.6.36 canceled
this restriction.

See sysdeps/unix/sysv/linux/mips/{mips32/sysdep.h,mips64/sysdep.h,sysdep.h}

Since glibc-2.24 the minimum kernel version is 3.2(much higer than
2.6.36), I think it is OK to remove the ugly register spill in
syscall.S just because of the old convention

This also remove the unaligned stack pointer operation
---
 sysdeps/unix/sysv/linux/mips/mips64/syscall.S | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/sysdeps/unix/sysv/linux/mips/mips64/syscall.S b/sysdeps/unix/sysv/linux/mips/mips64/syscall.S
index a9baff3c17..089524a40b 100644
--- a/sysdeps/unix/sysv/linux/mips/mips64/syscall.S
+++ b/sysdeps/unix/sysv/linux/mips/mips64/syscall.S
@@ -27,14 +27,9 @@
 
 	.text
 NESTED (syscall, SZREG, ra)
-	.mask 0x00010000, -SZREG
+	.mask 0x00000000, 0
 	.fmask 0x00000000, 0
-	PTR_ADDIU sp, -SZREG
-	cfi_adjust_cfa_offset (SZREG)
-	REG_S s0, (sp)
-	cfi_rel_offset (s0, 0)
-
-	move s0, a0
+	move v0, a0
 	move a0, a1		/* shift arg1 - arg7.  */
 	move a1, a2
 	move a2, a3
@@ -43,13 +38,8 @@ NESTED (syscall, SZREG, ra)
 	move a5, a6
 	move a6, a7
 
-	move v0, s0		/* Syscall number -> v0 */
 	syscall			/* Do the system call.  */
 
-	REG_L s0, (sp)
-	cfi_restore (s0)
-	PTR_ADDIU sp, SZREG
-	cfi_adjust_cfa_offset (-SZREG)
 	bne a3, zero, L(error)
 
 	ret
-- 
2.17.1

Re: [PATCH V2 2/2] mips: remove register spill

[Adhemerval Zanella]

On 02/12/2020 00:33, Huang Pei wrote:
> Before Linux/MIPS 2.6.36, kernel expected setting syscall number(aka
> "li v0, #sys_number") right precedes "syscall", so the kernel syscall
> restart sequence can use CP0 EPC - 4 to restart the syscall, because
> kernel DID NOT save v0 during syscall handling. Linux 2.6.36 canceled
> this restriction.
> 
> See sysdeps/unix/sysv/linux/mips/{mips32/sysdep.h,mips64/sysdep.h,sysdep.h}
> 
> Since glibc-2.24 the minimum kernel version is 3.2(much higer than
> 2.6.36), I think it is OK to remove the ugly register spill in
> syscall.S just because of the old convention
> 
> This also remove the unaligned stack pointer operation

LGTM, thanks.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>

> ---
>  sysdeps/unix/sysv/linux/mips/mips64/syscall.S | 14 ++------------
>  1 file changed, 2 insertions(+), 12 deletions(-)
> 
> diff --git a/sysdeps/unix/sysv/linux/mips/mips64/syscall.S b/sysdeps/unix/sysv/linux/mips/mips64/syscall.S
> index a9baff3c17..089524a40b 100644
> --- a/sysdeps/unix/sysv/linux/mips/mips64/syscall.S
> +++ b/sysdeps/unix/sysv/linux/mips/mips64/syscall.S
> @@ -27,14 +27,9 @@
>  
>  	.text
>  NESTED (syscall, SZREG, ra)
> -	.mask 0x00010000, -SZREG
> +	.mask 0x00000000, 0
>  	.fmask 0x00000000, 0
> -	PTR_ADDIU sp, -SZREG
> -	cfi_adjust_cfa_offset (SZREG)
> -	REG_S s0, (sp)
> -	cfi_rel_offset (s0, 0)
> -
> -	move s0, a0
> +	move v0, a0
>  	move a0, a1		/* shift arg1 - arg7.  */
>  	move a1, a2
>  	move a2, a3
> @@ -43,13 +38,8 @@ NESTED (syscall, SZREG, ra)
>  	move a5, a6
>  	move a6, a7
>  
> -	move v0, s0		/* Syscall number -> v0 */
>  	syscall			/* Do the system call.  */
>  
> -	REG_L s0, (sp)
> -	cfi_restore (s0)
> -	PTR_ADDIU sp, SZREG
> -	cfi_adjust_cfa_offset (-SZREG)
>  	bne a3, zero, L(error)
>  
>  	ret
> 

Re: [PATCH V2 1/2] mips: add hp-timing support for MIPS R2

[Adhemerval Zanella]

On 02/12/2020 00:33, Huang Pei wrote:
> MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
> enough for glibc.
> 
> DO remember Linux/MIPS added emulation for 'rdhwr %0, $2'，when disabled
> or not supported, which would make the precision worse. If you got
> unreasonable result, check your CPU Manual for whether your CPU
> implemented it or not

Could you confirm that all MIPS R2 machine do implement this instruction?
I don't want to slow down the loader for such machine, if they exists.

Patch looks ok, some indentation fixes below.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>

> ---
>  sysdeps/mips/hp-timing.h | 44 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 sysdeps/mips/hp-timing.h
> 
> diff --git a/sysdeps/mips/hp-timing.h b/sysdeps/mips/hp-timing.h
> new file mode 100644
> index 0000000000..43cb695f2f
> --- /dev/null
> +++ b/sysdeps/mips/hp-timing.h
> @@ -0,0 +1,44 @@
> +/* High precision, low overhead timing functions. MIPS version.
> +   Copyright (C) 2020 Free Software Foundation, Inc.
> +   This file is part of the GNU C Library.
> +   Contributed by Huang Pei <huangpei@loongson.cn>, 2020.
> +
> +   The GNU C Library is free software; you can redistribute it and/or
> +   modify it under the terms of the GNU Lesser General Public
> +   License as published by the Free Software Foundation; either
> +   version 2.1 of the License, or (at your option) any later version.
> +
> +   The GNU C Library is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +   Lesser General Public License for more details.
> +
> +   You should have received a copy of the GNU Lesser General Public
> +   License along with the GNU C Library; if not, see
> +   <http://www.gnu.org/licenses/>.  */
> +
> +#ifndef _HP_TIMING_MIPS_H
> +#define _HP_TIMING_MIPS_H	1
> +
> +#if IS_IN(rtld) && __mips_isa_rev >= 2
> +/* MIPS R2 always have the timestamp register. but it's got only 8 seconds
> + * range, assuming half of cpu frequence 800Mhz . Use it for ld.so
> + * profiling only*/
> +#define HP_TIMING_INLINE	(1)

Missing onne space indentation for preprocessor. 

> +
> +/* We use 32bit values for the times.  */
> +typedef unsigned int hp_timing_t;
> +
> +/* Read the cp0 count, this maybe inaccurate.  */
> +#define HP_TIMING_NOW(Var) \
> +  ({ unsigned int _count; \
> +     asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \
> +     (Var) = _count; })

Same as before.

> +
> +# include <hp-timing-common.h>
> +
> +#else
> +# include <sysdeps/generic/hp-timing.h>
> +#endif /* IS_IN(rtld) && __mips_isa_rev >= 2 */
> +
> +#endif /* hp-timing.h */
> 

Re: [PATCH V2 2/2] mips: remove register spill

[Maciej W. Rozycki]

On Wed, 2 Dec 2020, Huang Pei wrote:

> Before Linux/MIPS 2.6.36, kernel expected setting syscall number(aka
> "li v0, #sys_number") right precedes "syscall", so the kernel syscall
> restart sequence can use CP0 EPC - 4 to restart the syscall, because
> kernel DID NOT save v0 during syscall handling. Linux 2.6.36 canceled
> this restriction.

 I object, as I previously noted.

  Maciej

Re: [PATCH V2 1/2] mips: add hp-timing support for MIPS R2

[Maciej W. Rozycki]

On Wed, 2 Dec 2020, Huang Pei wrote:

> MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
> enough for glibc.
> 
> DO remember Linux/MIPS added emulation for 'rdhwr %0, $2'，when disabled
> or not supported, which would make the precision worse. If you got
> unreasonable result, check your CPU Manual for whether your CPU
> implemented it or not

 As discussed previously please rewrite the change description so as not 
to mislead with irrelevant information.

  Maciej

Re: [PATCH V2 1/2] mips: add hp-timing support for MIPS R2

[Huang Pei]

On Fri, Dec 04, 2020 at 11:05:54AM +0000, Maciej W. Rozycki wrote:
> On Wed, 2 Dec 2020, Huang Pei wrote:
> 
> > MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
> > enough for glibc.
> > 
> > DO remember Linux/MIPS added emulation for 'rdhwr %0, $2'，when disabled
> > or not supported, which would make the precision worse. If you got
> > unreasonable result, check your CPU Manual for whether your CPU
> > implemented it or not
> 
>  As discussed previously please rewrite the change description so as not 
> to mislead with irrelevant information.
> 
>   Maciej

What about this one?

......

MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
enough for glibc.

"rhdwr/CP0 Hwena and kerel/hypervisor emulation" makes userspace CAN NOT
tell whether rdhwr is not enabled(AKA CP0 Hwena bit[2] is not set, so 
kernel/hypervisor emulated it) or not implemented but still emulated by
kernel/hypervisor, however, it DO "feel something is wrong with rdhwr" by
specific test(like computing the difference between the results of two
nearby rdhwr)

If you get unreasonable result, check your environment(CPU manual,
kernel, hypervisor)
......