From: Richard Earnshaw <rearnsha@arm.com>
To: libc-alpha@sourceware.org
Cc: Richard Earnshaw <rearnsha@arm.com>,
dj@redhat.com, szabolcs.nagy@arm.com
Subject: [PATCH v5 5/6] aarch64: Add sysv specific enabling code for memory tagging
Date: Mon, 21 Dec 2020 15:33:44 +0000 [thread overview]
Message-ID: <20201221153345.3742-6-rearnsha@arm.com> (raw)
In-Reply-To: <20201221153345.3742-1-rearnsha@arm.com>
[-- Attachment #1: Type: text/plain, Size: 961 bytes --]
Add various defines and stubs for enabling MTE on AArch64 sysv-like
systems such as Linux. The HWCAP feature bit is copied over in the
same way as other feature bits. Similarly we add a new wrapper header
for mman.h to define the PROT_MTE flag that can be used with mmap and
related functions.
We add a new field to struct cpu_features that can be used, for
example, to check whether or not certain ifunc'd routines should be
bound to MTE-safe versions.
Finally, if we detect that MTE should be enabled (ie via the glibc
tunable); we enable MTE during startup as required.
Support in the Linux kernel was added in version 5.10.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
---
sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 1 +
sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 1 +
.../unix/sysv/linux/aarch64/cpu-features.c | 30 +++++++++++++++++++
.../unix/sysv/linux/aarch64/cpu-features.h | 2 ++
4 files changed, 34 insertions(+)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v5-0005-aarch64-Add-sysv-specific-enabling-code-for-memor.patch --]
[-- Type: text/x-patch; name="v5-0005-aarch64-Add-sysv-specific-enabling-code-for-memor.patch", Size: 3139 bytes --]
diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h
index af90d8a626..389852f1d9 100644
--- a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h
+++ b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h
@@ -73,3 +73,4 @@
#define HWCAP2_DGH (1 << 15)
#define HWCAP2_RNG (1 << 16)
#define HWCAP2_BTI (1 << 17)
+#define HWCAP2_MTE (1 << 18)
diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h
index ecae046344..c5ec0aa7d0 100644
--- a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h
+++ b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h
@@ -24,6 +24,7 @@
arch/arm64/include/uapi/asm/mman.h. */
#define PROT_BTI 0x10
+#define PROT_MTE 0x20
#include <bits/mman-map-flags-generic.h>
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index b9ab827aca..bd899c4b09 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -19,10 +19,17 @@
#include <cpu-features.h>
#include <sys/auxv.h>
#include <elf/dl-hwcaps.h>
+#include <sys/prctl.h>
#define DCZID_DZP_MASK (1 << 4)
#define DCZID_BS_MASK (0xf)
+/* The maximal set of permitted tags that the MTE random tag generation
+ instruction may use. We exclude tag 0 because a) we want to reserve
+ that for the libc heap structures and b) because it makes it easier
+ to see when pointer have been correctly tagged. */
+#define MTE_ALLOWED_TAGS (0xfffe << PR_MTE_TAG_SHIFT)
+
#if HAVE_TUNABLES
struct cpu_list
{
@@ -86,4 +93,27 @@ init_cpu_features (struct cpu_features *cpu_features)
/* Check if BTI is supported. */
cpu_features->bti = GLRO (dl_hwcap2) & HWCAP2_BTI;
+
+ /* Setup memory tagging support if the HW and kernel support it, and if
+ the user has requested it. */
+ cpu_features->mte_state = 0;
+
+#ifdef USE_MTAG
+# if HAVE_TUNABLES
+ int mte_state = TUNABLE_GET (glibc, mem, tagging, unsigned, 0);
+ cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0;
+ /* If we lack the MTE feature, disable the tunable, since it will
+ otherwise cause instructions that won't run on this CPU to be used. */
+ TUNABLE_SET (glibc, mem, tagging, unsigned, cpu_features->mte_state);
+# endif
+
+ if (cpu_features->mte_state & 2)
+ __prctl (PR_SET_TAGGED_ADDR_CTRL,
+ (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS),
+ 0, 0, 0);
+ else if (cpu_features->mte_state)
+ __prctl (PR_SET_TAGGED_ADDR_CTRL,
+ (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC | MTE_ALLOWED_TAGS),
+ 0, 0, 0);
+#endif
}
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
index 00a4d0c8e7..bebf321a21 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
@@ -70,6 +70,8 @@ struct cpu_features
uint64_t midr_el1;
unsigned zva_size;
bool bti;
+ /* Currently, the GLIBC memory tagging tunable only defines 8 bits. */
+ uint8_t mte_state;
};
#endif /* _CPU_FEATURES_AARCH64_H */
next prev parent reply other threads:[~2020-12-21 15:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-21 15:33 [PATCH v5 0/6] [committed] Memory tagging support Richard Earnshaw
2020-12-21 15:33 ` [PATCH v5 1/6] config: Allow memory tagging to be enabled when configuring glibc Richard Earnshaw
2020-12-21 15:33 ` [PATCH v5 2/6] elf: Add a tunable to control use of tagged memory Richard Earnshaw
2020-12-21 15:33 ` [PATCH v5 3/6] malloc: Basic support for memory tagging in the malloc() family Richard Earnshaw
2020-12-21 15:33 ` [PATCH v5 4/6] linux: Add compatibility definitions to sys/prctl.h for MTE Richard Earnshaw
2020-12-21 15:33 ` Richard Earnshaw [this message]
2020-12-21 15:33 ` [PATCH v5 6/6] aarch64: Add aarch64-specific files for memory tagging support Richard Earnshaw
2020-12-22 12:49 ` [PATCH v5 0/6] [committed] Memory " Andreas Schwab
2020-12-22 12:58 ` Siddhesh Poyarekar
2020-12-22 13:21 ` Andreas Schwab
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