From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 8B591386F430 for ; Mon, 21 Dec 2020 15:34:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8B591386F430 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 27C1D1FB; Mon, 21 Dec 2020 07:34:05 -0800 (PST) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 730103F6CF; Mon, 21 Dec 2020 07:34:04 -0800 (PST) From: Richard Earnshaw To: libc-alpha@sourceware.org Cc: Richard Earnshaw , dj@redhat.com, szabolcs.nagy@arm.com Subject: [PATCH v5 5/6] aarch64: Add sysv specific enabling code for memory tagging Date: Mon, 21 Dec 2020 15:33:44 +0000 Message-Id: <20201221153345.3742-6-rearnsha@arm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201221153345.3742-1-rearnsha@arm.com> References: <20201221153345.3742-1-rearnsha@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.29.2" Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Dec 2020 15:34:07 -0000 This is a multi-part message in MIME format. --------------2.29.2 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: 8bit Add various defines and stubs for enabling MTE on AArch64 sysv-like systems such as Linux. The HWCAP feature bit is copied over in the same way as other feature bits. Similarly we add a new wrapper header for mman.h to define the PROT_MTE flag that can be used with mmap and related functions. We add a new field to struct cpu_features that can be used, for example, to check whether or not certain ifunc'd routines should be bound to MTE-safe versions. Finally, if we detect that MTE should be enabled (ie via the glibc tunable); we enable MTE during startup as required. Support in the Linux kernel was added in version 5.10. Reviewed-by: Szabolcs Nagy --- sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 1 + sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 1 + .../unix/sysv/linux/aarch64/cpu-features.c | 30 +++++++++++++++++++ .../unix/sysv/linux/aarch64/cpu-features.h | 2 ++ 4 files changed, 34 insertions(+) --------------2.29.2 Content-Type: text/x-patch; name="v5-0005-aarch64-Add-sysv-specific-enabling-code-for-memor.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="v5-0005-aarch64-Add-sysv-specific-enabling-code-for-memor.patch" diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h index af90d8a626..389852f1d9 100644 --- a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h +++ b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h @@ -73,3 +73,4 @@ #define HWCAP2_DGH (1 << 15) #define HWCAP2_RNG (1 << 16) #define HWCAP2_BTI (1 << 17) +#define HWCAP2_MTE (1 << 18) diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h index ecae046344..c5ec0aa7d0 100644 --- a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h +++ b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h @@ -24,6 +24,7 @@ arch/arm64/include/uapi/asm/mman.h. */ #define PROT_BTI 0x10 +#define PROT_MTE 0x20 #include diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index b9ab827aca..bd899c4b09 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -19,10 +19,17 @@ #include #include #include +#include #define DCZID_DZP_MASK (1 << 4) #define DCZID_BS_MASK (0xf) +/* The maximal set of permitted tags that the MTE random tag generation + instruction may use. We exclude tag 0 because a) we want to reserve + that for the libc heap structures and b) because it makes it easier + to see when pointer have been correctly tagged. */ +#define MTE_ALLOWED_TAGS (0xfffe << PR_MTE_TAG_SHIFT) + #if HAVE_TUNABLES struct cpu_list { @@ -86,4 +93,27 @@ init_cpu_features (struct cpu_features *cpu_features) /* Check if BTI is supported. */ cpu_features->bti = GLRO (dl_hwcap2) & HWCAP2_BTI; + + /* Setup memory tagging support if the HW and kernel support it, and if + the user has requested it. */ + cpu_features->mte_state = 0; + +#ifdef USE_MTAG +# if HAVE_TUNABLES + int mte_state = TUNABLE_GET (glibc, mem, tagging, unsigned, 0); + cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0; + /* If we lack the MTE feature, disable the tunable, since it will + otherwise cause instructions that won't run on this CPU to be used. */ + TUNABLE_SET (glibc, mem, tagging, unsigned, cpu_features->mte_state); +# endif + + if (cpu_features->mte_state & 2) + __prctl (PR_SET_TAGGED_ADDR_CTRL, + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS), + 0, 0, 0); + else if (cpu_features->mte_state) + __prctl (PR_SET_TAGGED_ADDR_CTRL, + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC | MTE_ALLOWED_TAGS), + 0, 0, 0); +#endif } diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h index 00a4d0c8e7..bebf321a21 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h @@ -70,6 +70,8 @@ struct cpu_features uint64_t midr_el1; unsigned zva_size; bool bti; + /* Currently, the GLIBC memory tagging tunable only defines 8 bits. */ + uint8_t mte_state; }; #endif /* _CPU_FEATURES_AARCH64_H */ --------------2.29.2--