From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) by sourceware.org (Postfix) with ESMTPS id A5FD33836007 for ; Tue, 6 Jul 2021 10:51:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A5FD33836007 Received: by ozlabs.org (Postfix, from userid 1010) id 4GJzr304Z6z9shx; Tue, 6 Jul 2021 20:51:14 +1000 (AEST) From: Anton Blanchard To: tuliom@linux.ibm.com Cc: libc-alpha@sourceware.org Subject: [PATCH 2/3] powerpc64: Check cacheline size before using optimised memset routines Date: Tue, 6 Jul 2021 20:51:06 +1000 Message-Id: <20210706105107.1866836-2-anton@ozlabs.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210706105107.1866836-1-anton@ozlabs.org> References: <20210706105107.1866836-1-anton@ozlabs.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jul 2021 10:51:19 -0000 A number of optimised memset routines assume the cacheline size is 128B, so we better check before using them. --- sysdeps/powerpc/powerpc64/multiarch/memset.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c index c1aa143f60..056e911699 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/memset.c +++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c @@ -43,16 +43,21 @@ libc_ifunc (__libc_memset, # ifdef __LITTLE_ENDIAN__ (hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX) + && hwcap & PPC_FEATURE_HAS_VSX + && GLRO(dl_cache_line_size) == 128) ? __memset_power10 : # endif - (hwcap2 & PPC_FEATURE2_ARCH_2_07) + (hwcap2 & PPC_FEATURE2_ARCH_2_07 + && GLRO(dl_cache_line_size) == 128) ? __memset_power8 : - (hwcap & PPC_FEATURE_ARCH_2_06) + (hwcap & PPC_FEATURE_ARCH_2_06 + && GLRO(dl_cache_line_size) == 128) ? __memset_power7 : - (hwcap & PPC_FEATURE_ARCH_2_05) + (hwcap & PPC_FEATURE_ARCH_2_05 + && GLRO(dl_cache_line_size) == 128) ? __memset_power6 : - (hwcap & PPC_FEATURE_POWER4) + (hwcap & PPC_FEATURE_POWER4 + && GLRO(dl_cache_line_size) == 128) ? __memset_power4 : __memset_ppc); -- 2.31.1