From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by sourceware.org (Postfix) with ESMTPS id D9A9E39960C0 for ; Thu, 8 Jul 2021 17:57:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D9A9E39960C0 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8E52E617ED; Thu, 8 Jul 2021 17:57:28 +0000 (UTC) Date: Thu, 8 Jul 2021 18:56:55 +0100 From: Mark Brown To: Florian Weimer Cc: libc-alpha@sourceware.org, linux-api@vger.kernel.org, x86@kernel.org, linux-arch@vger.kernel.org, "H.J. Lu" , Catalin Marinas , Will Deacon Subject: Re: x86 CPU features detection for applications (and AMX) Message-ID: <20210708175655.GA33786@sirena.org.uk> References: <87tulo39ms.fsf@oldenburg.str.redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="5vNYLRcllDrimb99" Content-Disposition: inline In-Reply-To: <87tulo39ms.fsf@oldenburg.str.redhat.com> X-Cookie: "Elvis is my copilot." User-Agent: Mutt/1.10.1 (2018-07-13) X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jul 2021 17:57:32 -0000 --5vNYLRcllDrimb99 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jun 23, 2021 at 05:04:27PM +0200, Florian Weimer wrote: Copying in Catalin & Will. > We have an interface in glibc to query CPU features: > X86-specific Facilities > > CPU_FEATURE_USABLE all preconditions for a feature are met, > HAS_CPU_FEATURE means it's in silicon but possibly dormant. > CPU_FEATURE_USABLE is supposed to look at XCR0, AT_HWCAP2 etc. before > enabling the relevant bit (so it cannot pass through any unknown bits). ... > When we designed this glibc interface, we assumed that bits would be > static during the life-time of the process, initialized at process > start. That follows the model of previous x86 CPU feature enablement. ... > This still wouldn't cover the enable/disable side, but at least it would > work for CPU features which are modal and come and go. The fact that we > tell GCC to cache the returned pointer from that internal function, but > not that the data is immutable works to our advantage here. > On the other hand, maybe there is a way to give users a better > interface. Obviously we want to avoid a syscall for a simple CPU > feature check. And we also need something to enable/disable CPU > features. This enabling and disabling of CPU features sounds like something that might also become relevant for arm64, for example I can see a use case for having something that allows some of the more expensive features to be masked from some userspace processes for resource management purposes. This sounds like a bit of a different use case to x86 AIUI but I think there's overlap in the actual operations that would be needed. --5vNYLRcllDrimb99 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmDnPGYACgkQJNaLcl1U h9CmMAgAgoVAsCnhVpOX+qfExOdJuwLQ3o0KisscXB9Lbg7xX4PiM7hCBDnFpVSP Ik+oZKueIi66qoFc/ca/UhQFI5wWBGdL2Ih3FfVOx5LJTjMNmkUR+vgJqy/G4qwP lHbN3J52gSsRoXov3LF85GE2KUCax+r/XyHY7++/VmC9ylEOzSXhItUheL6YUqhn AYxplSFPHP8Gha2gqN/Hc4Zzi2wpe6TNaHujDzTE6SVPdJi2PupWT+gQj6nAmyOg czDzchCbkyHxPvvEH4bUFrvwPKJXFx5aoMcUOLR2nQk98MauMUb2D8bhBRxLnmP+ ZW1JhazXCO6p23WXdhGY47vx58/xiQ== =wOfR -----END PGP SIGNATURE----- --5vNYLRcllDrimb99--