From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) by sourceware.org (Postfix) with ESMTPS id 20C04383B41B for ; Tue, 27 Jul 2021 05:48:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 20C04383B41B Received: by ozlabs.org (Postfix, from userid 1010) id 4GYm6X5N2pz9sXG; Tue, 27 Jul 2021 15:48:04 +1000 (AEST) From: Anton Blanchard To: tuliom@linux.ibm.com, adhemerval.zanella@linaro.org Cc: libc-alpha@sourceware.org Subject: [PATCH 2/3] powerpc64: Check cacheline size before using optimised memset routines Date: Tue, 27 Jul 2021 15:47:50 +1000 Message-Id: <20210727054751.3972562-2-anton@ozlabs.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210727054751.3972562-1-anton@ozlabs.org> References: <20210727054751.3972562-1-anton@ozlabs.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jul 2021 05:48:09 -0000 A number of optimised memset routines assume the cacheline size is 128B, so we better check before using them. --- .../powerpc64/multiarch/ifunc-impl-list.c | 18 +++++++++++++----- sysdeps/powerpc/powerpc64/multiarch/memset.c | 15 ++++++++++----- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c index 32564c8f1f..a3fdcd43bd 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c +++ b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c @@ -35,6 +35,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, unsigned long int hwcap = GLRO(dl_hwcap); unsigned long int hwcap2 = GLRO(dl_hwcap2); +#ifdef SHARED + int cacheline_size = GLRO(dl_cache_line_size); +#endif /* hwcap contains only the latest supported ISA, the code checks which is and fills the previous supported ones. */ @@ -90,16 +93,21 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX, + && hwcap & PPC_FEATURE_HAS_VSX + && cacheline_size == 128, __memset_power10) #endif - IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07, + IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07 + && cacheline_size == 128, __memset_power8) - IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_06, + IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_06 + && cacheline_size == 128, __memset_power7) - IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_05, + IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_05 + && cacheline_size == 128, __memset_power6) - IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_POWER4, + IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_POWER4 + && cacheline_size == 128, __memset_power4) IFUNC_IMPL_ADD (array, i, memset, 1, __memset_ppc)) diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c index c1aa143f60..056e911699 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/memset.c +++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c @@ -43,16 +43,21 @@ libc_ifunc (__libc_memset, # ifdef __LITTLE_ENDIAN__ (hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX) + && hwcap & PPC_FEATURE_HAS_VSX + && GLRO(dl_cache_line_size) == 128) ? __memset_power10 : # endif - (hwcap2 & PPC_FEATURE2_ARCH_2_07) + (hwcap2 & PPC_FEATURE2_ARCH_2_07 + && GLRO(dl_cache_line_size) == 128) ? __memset_power8 : - (hwcap & PPC_FEATURE_ARCH_2_06) + (hwcap & PPC_FEATURE_ARCH_2_06 + && GLRO(dl_cache_line_size) == 128) ? __memset_power7 : - (hwcap & PPC_FEATURE_ARCH_2_05) + (hwcap & PPC_FEATURE_ARCH_2_05 + && GLRO(dl_cache_line_size) == 128) ? __memset_power6 : - (hwcap & PPC_FEATURE_POWER4) + (hwcap & PPC_FEATURE_POWER4 + && GLRO(dl_cache_line_size) == 128) ? __memset_power4 : __memset_ppc); -- 2.31.1