[PATCH v2 0/2] RISC-V: Add vector ISA support

[Vincent Chen <vincent.chen@sifive.com>]

According to the feedback for the version 1 patch set, only the
"RISC-V: Remove riscv-specific sigcontext.h" patch remains in this version
patch set. It means that MINSIGSTKSZ, SIGSTKSZ, and PTHREAD_STACK_MIN are not
changed after introducing the V-extension support. Therefore, the current
definition of the above stack size is insufficient to backup all vector
registers. In this circumstance, users have to use the mechanisms submitted by
H.J. Lu https://sourceware.org/git/?p=glibc.git;a=commit;h=6c57d320484988e87e446e2e60ce42816bf51d53
and https://sourceware.org/git/?p=glibc.git;a=commit;h=5d98a7dae955bafa6740c26eaba9c86060ae0344
to obtain the appropriate size of the current system setting.

Besides, a new calling convention using vector registers to transfer argument
or return value probably be proposed in the feature. It may cause the resolved
functions and audit functions to corrupt the content of the vector registers,
which are used as argument registers and address return registers. To avoid
this problem, this patch set includes Hsiangkai Wang's patch to enable the
Glibc dynamic loader to directly resolve the function symbols whose calling
convention is incompatible with the standard calling convention. The
corresponding implementation in Binutils can be found in
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8155b8539b55bca87378129e02009cd8907d8c8c.


Hsiangkai Wang (1):
  riscv: Resolve symbols directly for symbols with STO_RISCV_VARIANT_CC.

Vincent Chen (1):
  RISC-V: remove riscv-specific sigcontext.h

 elf/elf.h                                     |  7 +++++
 manual/platform.texi                          |  6 +++++
 .../sigcontext.h => riscv/dl-dtprocnum.h}     | 22 +++++-----------
 sysdeps/riscv/dl-machine.h                    | 26 +++++++++++++++++++
 4 files changed, 45 insertions(+), 16 deletions(-)
 rename sysdeps/{unix/sysv/linux/riscv/bits/sigcontext.h => riscv/dl-dtprocnum.h} (55%)

-- 
2.17.1