From: Sunil K Pandey <skpgkp2@gmail.com>
To: libc-alpha@sourceware.org
Subject: [PATCH 054/126] x86_64: Fix svml_d_cosh8_core_avx512.S code formatting
Date: Mon, 7 Mar 2022 07:00:49 -0800 [thread overview]
Message-ID: <20220307150201.10590-55-skpgkp2@gmail.com> (raw)
In-Reply-To: <20220307150201.10590-1-skpgkp2@gmail.com>
This commit contains following formatting changes
1. Instructions proceeded by a tab.
2. Instruction less than 8 characters in length have a tab
between it and the first operand.
3. Instruction greater than 7 characters in length have a
space between it and the first operand.
4. Tabs after `#define`d names and their value.
5. 8 space at the beginning of line replaced by tab.
6. Indent comments with code.
7. Remove redundent .text section.
---
.../fpu/multiarch/svml_d_cosh8_core_avx512.S | 520 +++++++++---------
1 file changed, 259 insertions(+), 261 deletions(-)
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_cosh8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_cosh8_core_avx512.S
index fd010c61b4..066bbc7de6 100644
--- a/sysdeps/x86_64/fpu/multiarch/svml_d_cosh8_core_avx512.S
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_cosh8_core_avx512.S
@@ -34,290 +34,288 @@
/* Offsets for data table __svml_dcosh_data_internal
*/
-#define _dTp_h 0
-#define _dTn_h 128
-#define _dbShifter_UISA 256
-#define _dPC2_UISA 320
-#define _dPC3_UISA 384
-#define _dPC4_UISA 448
-#define _dPC5_UISA 512
-#define _dPC6_UISA 576
-#define _dPC7_UISA 640
-#define _dbInvLn2 704
-#define _dbLn2hi 768
-#define _dbLn2lo 832
-#define _dbShifter 896
-#define _dPC2 960
-#define _dPC3 1024
-#define _dPC4 1088
-#define _lExpMask 1152
-#define _dSign 1216
-#define _iDomainRange 1280
+#define _dTp_h 0
+#define _dTn_h 128
+#define _dbShifter_UISA 256
+#define _dPC2_UISA 320
+#define _dPC3_UISA 384
+#define _dPC4_UISA 448
+#define _dPC5_UISA 512
+#define _dPC6_UISA 576
+#define _dPC7_UISA 640
+#define _dbInvLn2 704
+#define _dbLn2hi 768
+#define _dbLn2lo 832
+#define _dbShifter 896
+#define _dPC2 960
+#define _dPC3 1024
+#define _dPC4 1088
+#define _lExpMask 1152
+#define _dSign 1216
+#define _iDomainRange 1280
#include <sysdep.h>
- .text
- .section .text.evex512,"ax",@progbits
+ .section .text.evex512, "ax", @progbits
ENTRY(_ZGVeN8v_cosh_skx)
- pushq %rbp
- cfi_def_cfa_offset(16)
- movq %rsp, %rbp
- cfi_def_cfa(6, 16)
- cfi_offset(6, -16)
- andq $-64, %rsp
- subq $192, %rsp
- vmovups _dSign+__svml_dcosh_data_internal(%rip), %zmm11
- vmovups _dbShifter_UISA+__svml_dcosh_data_internal(%rip), %zmm15
-
-/*
- * Load argument
- * dM = x*2^K/log(2) + RShifter
- */
- vmovups _dbInvLn2+__svml_dcosh_data_internal(%rip), %zmm4
- vmovups _dbLn2hi+__svml_dcosh_data_internal(%rip), %zmm2
- vmovups _dbLn2lo+__svml_dcosh_data_internal(%rip), %zmm3
- vmovups _dPC7_UISA+__svml_dcosh_data_internal(%rip), %zmm8
- vmovups _dPC6_UISA+__svml_dcosh_data_internal(%rip), %zmm9
- vmovups _dPC2_UISA+__svml_dcosh_data_internal(%rip), %zmm7
- vmovups _dPC3_UISA+__svml_dcosh_data_internal(%rip), %zmm6
- vmovaps %zmm0, %zmm10
-
-/* Abs argument */
- vandnpd %zmm10, %zmm11, %zmm5
-
-/* Index and lookup */
- vmovups __svml_dcosh_data_internal(%rip), %zmm11
- vmovups _dTn_h+__svml_dcosh_data_internal(%rip), %zmm0
- vfmadd213pd {rn-sae}, %zmm15, %zmm5, %zmm4
-
-/*
- * Check for overflow\underflow
- *
- */
- vpsrlq $32, %zmm5, %zmm12
-
-/* dN = dM - RShifter */
- vsubpd {rn-sae}, %zmm15, %zmm4, %zmm1
- vpmovqd %zmm12, %ymm13
- vpermt2pd _dTn_h+64+__svml_dcosh_data_internal(%rip), %zmm4, %zmm0
- vpermt2pd _dTp_h+64+__svml_dcosh_data_internal(%rip), %zmm4, %zmm11
-
-/* dR = dX - dN*Log2_hi/2^K */
- vfnmadd231pd {rn-sae}, %zmm2, %zmm1, %zmm5
-
-/*
- * poly(r) = Gmjp(1 + a2*r^2 + a4*r^4) + Gmjn*(r+ a3*r^3 +a5*r^5) =
- * = Gmjp_h +Gmjp_l+ Gmjp*r^2*(a2 + a4*r^2) + Gmjn*(r+ r^3*(a3 +a5*r^2)
- */
- vmovups _dPC5_UISA+__svml_dcosh_data_internal(%rip), %zmm12
- vpsllq $48, %zmm4, %zmm2
-
-/* dR = dX - dN*Log2_hi/2^K */
- vfnmadd231pd {rn-sae}, %zmm3, %zmm1, %zmm5
- vmulpd {rn-sae}, %zmm5, %zmm5, %zmm1
- vfmadd231pd {rn-sae}, %zmm1, %zmm8, %zmm12
- vmovups _dPC4_UISA+__svml_dcosh_data_internal(%rip), %zmm8
- vfmadd213pd {rn-sae}, %zmm6, %zmm1, %zmm12
- vfmadd231pd {rn-sae}, %zmm1, %zmm9, %zmm8
- vfmadd213pd {rn-sae}, %zmm7, %zmm1, %zmm8
- vpcmpgtd _iDomainRange+__svml_dcosh_data_internal(%rip), %ymm13, %ymm14
- vmovmskps %ymm14, %edx
-
-/* dOut=r^2*(a2 + a4*r^2) */
- vmulpd {rn-sae}, %zmm1, %zmm8, %zmm6
-
-/* lM now is an EXP(2^N) */
- vpandq _lExpMask+__svml_dcosh_data_internal(%rip), %zmm2, %zmm3
- vpaddq %zmm3, %zmm11, %zmm4
- vpsubq %zmm3, %zmm0, %zmm0
- vsubpd {rn-sae}, %zmm0, %zmm4, %zmm14
- vaddpd {rn-sae}, %zmm0, %zmm4, %zmm13
-
-/* dM=r^2*(a3 +a5*r^2) */
- vmulpd {rn-sae}, %zmm1, %zmm12, %zmm0
- vfmadd213pd {rn-sae}, %zmm13, %zmm13, %zmm6
-
-/* dM= r + r^3*(a3 +a5*r^2) */
- vfmadd213pd {rn-sae}, %zmm5, %zmm5, %zmm0
- vfmadd213pd {rn-sae}, %zmm6, %zmm14, %zmm0
- testl %edx, %edx
-
-/* Go to special inputs processing branch */
- jne L(SPECIAL_VALUES_BRANCH)
- # LOE rbx r12 r13 r14 r15 edx zmm0 zmm10
-
-/* Restore registers
- * and exit the function
- */
+ pushq %rbp
+ cfi_def_cfa_offset(16)
+ movq %rsp, %rbp
+ cfi_def_cfa(6, 16)
+ cfi_offset(6, -16)
+ andq $-64, %rsp
+ subq $192, %rsp
+ vmovups _dSign+__svml_dcosh_data_internal(%rip), %zmm11
+ vmovups _dbShifter_UISA+__svml_dcosh_data_internal(%rip), %zmm15
+
+ /*
+ * Load argument
+ * dM = x*2^K/log(2) + RShifter
+ */
+ vmovups _dbInvLn2+__svml_dcosh_data_internal(%rip), %zmm4
+ vmovups _dbLn2hi+__svml_dcosh_data_internal(%rip), %zmm2
+ vmovups _dbLn2lo+__svml_dcosh_data_internal(%rip), %zmm3
+ vmovups _dPC7_UISA+__svml_dcosh_data_internal(%rip), %zmm8
+ vmovups _dPC6_UISA+__svml_dcosh_data_internal(%rip), %zmm9
+ vmovups _dPC2_UISA+__svml_dcosh_data_internal(%rip), %zmm7
+ vmovups _dPC3_UISA+__svml_dcosh_data_internal(%rip), %zmm6
+ vmovaps %zmm0, %zmm10
+
+ /* Abs argument */
+ vandnpd %zmm10, %zmm11, %zmm5
+
+ /* Index and lookup */
+ vmovups __svml_dcosh_data_internal(%rip), %zmm11
+ vmovups _dTn_h+__svml_dcosh_data_internal(%rip), %zmm0
+ vfmadd213pd {rn-sae}, %zmm15, %zmm5, %zmm4
+
+ /*
+ * Check for overflow\underflow
+ *
+ */
+ vpsrlq $32, %zmm5, %zmm12
+
+ /* dN = dM - RShifter */
+ vsubpd {rn-sae}, %zmm15, %zmm4, %zmm1
+ vpmovqd %zmm12, %ymm13
+ vpermt2pd _dTn_h+64+__svml_dcosh_data_internal(%rip), %zmm4, %zmm0
+ vpermt2pd _dTp_h+64+__svml_dcosh_data_internal(%rip), %zmm4, %zmm11
+
+ /* dR = dX - dN*Log2_hi/2^K */
+ vfnmadd231pd {rn-sae}, %zmm2, %zmm1, %zmm5
+
+ /*
+ * poly(r) = Gmjp(1 + a2*r^2 + a4*r^4) + Gmjn*(r+ a3*r^3 +a5*r^5) =
+ * = Gmjp_h +Gmjp_l+ Gmjp*r^2*(a2 + a4*r^2) + Gmjn*(r+ r^3*(a3 +a5*r^2)
+ */
+ vmovups _dPC5_UISA+__svml_dcosh_data_internal(%rip), %zmm12
+ vpsllq $48, %zmm4, %zmm2
+
+ /* dR = dX - dN*Log2_hi/2^K */
+ vfnmadd231pd {rn-sae}, %zmm3, %zmm1, %zmm5
+ vmulpd {rn-sae}, %zmm5, %zmm5, %zmm1
+ vfmadd231pd {rn-sae}, %zmm1, %zmm8, %zmm12
+ vmovups _dPC4_UISA+__svml_dcosh_data_internal(%rip), %zmm8
+ vfmadd213pd {rn-sae}, %zmm6, %zmm1, %zmm12
+ vfmadd231pd {rn-sae}, %zmm1, %zmm9, %zmm8
+ vfmadd213pd {rn-sae}, %zmm7, %zmm1, %zmm8
+ vpcmpgtd _iDomainRange+__svml_dcosh_data_internal(%rip), %ymm13, %ymm14
+ vmovmskps %ymm14, %edx
+
+ /* dOut=r^2*(a2 + a4*r^2) */
+ vmulpd {rn-sae}, %zmm1, %zmm8, %zmm6
+
+ /* lM now is an EXP(2^N) */
+ vpandq _lExpMask+__svml_dcosh_data_internal(%rip), %zmm2, %zmm3
+ vpaddq %zmm3, %zmm11, %zmm4
+ vpsubq %zmm3, %zmm0, %zmm0
+ vsubpd {rn-sae}, %zmm0, %zmm4, %zmm14
+ vaddpd {rn-sae}, %zmm0, %zmm4, %zmm13
+
+ /* dM=r^2*(a3 +a5*r^2) */
+ vmulpd {rn-sae}, %zmm1, %zmm12, %zmm0
+ vfmadd213pd {rn-sae}, %zmm13, %zmm13, %zmm6
+
+ /* dM= r + r^3*(a3 +a5*r^2) */
+ vfmadd213pd {rn-sae}, %zmm5, %zmm5, %zmm0
+ vfmadd213pd {rn-sae}, %zmm6, %zmm14, %zmm0
+ testl %edx, %edx
+
+ /* Go to special inputs processing branch */
+ jne L(SPECIAL_VALUES_BRANCH)
+ # LOE rbx r12 r13 r14 r15 edx zmm0 zmm10
+
+ /* Restore registers
+ * and exit the function
+ */
L(EXIT):
- movq %rbp, %rsp
- popq %rbp
- cfi_def_cfa(7, 8)
- cfi_restore(6)
- ret
- cfi_def_cfa(6, 16)
- cfi_offset(6, -16)
-
-/* Branch to process
- * special inputs
- */
+ movq %rbp, %rsp
+ popq %rbp
+ cfi_def_cfa(7, 8)
+ cfi_restore(6)
+ ret
+ cfi_def_cfa(6, 16)
+ cfi_offset(6, -16)
+
+ /* Branch to process
+ * special inputs
+ */
L(SPECIAL_VALUES_BRANCH):
- vmovups %zmm10, 64(%rsp)
- vmovups %zmm0, 128(%rsp)
- # LOE rbx r12 r13 r14 r15 edx zmm0
-
- xorl %eax, %eax
- # LOE rbx r12 r13 r14 r15 eax edx
-
- vzeroupper
- movq %r12, 16(%rsp)
- /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */
- .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22
- movl %eax, %r12d
- movq %r13, 8(%rsp)
- /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */
- .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22
- movl %edx, %r13d
- movq %r14, (%rsp)
- /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */
- .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22
- # LOE rbx r15 r12d r13d
-
-/* Range mask
- * bits check
- */
+ vmovups %zmm10, 64(%rsp)
+ vmovups %zmm0, 128(%rsp)
+ # LOE rbx r12 r13 r14 r15 edx zmm0
+
+ xorl %eax, %eax
+ # LOE rbx r12 r13 r14 r15 eax edx
+
+ vzeroupper
+ movq %r12, 16(%rsp)
+ /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */
+ .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22
+ movl %eax, %r12d
+ movq %r13, 8(%rsp)
+ /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */
+ .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22
+ movl %edx, %r13d
+ movq %r14, (%rsp)
+ /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */
+ .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22
+ # LOE rbx r15 r12d r13d
+
+ /* Range mask
+ * bits check
+ */
L(RANGEMASK_CHECK):
- btl %r12d, %r13d
+ btl %r12d, %r13d
-/* Call scalar math function */
- jc L(SCALAR_MATH_CALL)
- # LOE rbx r15 r12d r13d
+ /* Call scalar math function */
+ jc L(SCALAR_MATH_CALL)
+ # LOE rbx r15 r12d r13d
-/* Special inputs
- * processing loop
- */
+ /* Special inputs
+ * processing loop
+ */
L(SPECIAL_VALUES_LOOP):
- incl %r12d
- cmpl $8, %r12d
-
-/* Check bits in range mask */
- jl L(RANGEMASK_CHECK)
- # LOE rbx r15 r12d r13d
-
- movq 16(%rsp), %r12
- cfi_restore(12)
- movq 8(%rsp), %r13
- cfi_restore(13)
- movq (%rsp), %r14
- cfi_restore(14)
- vmovups 128(%rsp), %zmm0
-
-/* Go to exit */
- jmp L(EXIT)
- /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */
- .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22
- /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */
- .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22
- /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */
- .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22
- # LOE rbx r12 r13 r14 r15 zmm0
-
-/* Scalar math fucntion call
- * to process special input
- */
+ incl %r12d
+ cmpl $8, %r12d
+
+ /* Check bits in range mask */
+ jl L(RANGEMASK_CHECK)
+ # LOE rbx r15 r12d r13d
+
+ movq 16(%rsp), %r12
+ cfi_restore(12)
+ movq 8(%rsp), %r13
+ cfi_restore(13)
+ movq (%rsp), %r14
+ cfi_restore(14)
+ vmovups 128(%rsp), %zmm0
+
+ /* Go to exit */
+ jmp L(EXIT)
+ /* DW_CFA_expression: r12 (r12) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -176; DW_OP_plus) */
+ .cfi_escape 0x10, 0x0c, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x50, 0xff, 0xff, 0xff, 0x22
+ /* DW_CFA_expression: r13 (r13) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -184; DW_OP_plus) */
+ .cfi_escape 0x10, 0x0d, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x48, 0xff, 0xff, 0xff, 0x22
+ /* DW_CFA_expression: r14 (r14) (DW_OP_lit8; DW_OP_minus; DW_OP_const4s: -64; DW_OP_and; DW_OP_const4s: -192; DW_OP_plus) */
+ .cfi_escape 0x10, 0x0e, 0x0e, 0x38, 0x1c, 0x0d, 0xc0, 0xff, 0xff, 0xff, 0x1a, 0x0d, 0x40, 0xff, 0xff, 0xff, 0x22
+ # LOE rbx r12 r13 r14 r15 zmm0
+
+ /* Scalar math fucntion call
+ * to process special input
+ */
L(SCALAR_MATH_CALL):
- movl %r12d, %r14d
- movsd 64(%rsp,%r14,8), %xmm0
- call cosh@PLT
- # LOE rbx r14 r15 r12d r13d xmm0
+ movl %r12d, %r14d
+ movsd 64(%rsp, %r14, 8), %xmm0
+ call cosh@PLT
+ # LOE rbx r14 r15 r12d r13d xmm0
- movsd %xmm0, 128(%rsp,%r14,8)
+ movsd %xmm0, 128(%rsp, %r14, 8)
-/* Process special inputs in loop */
- jmp L(SPECIAL_VALUES_LOOP)
- # LOE rbx r15 r12d r13d
+ /* Process special inputs in loop */
+ jmp L(SPECIAL_VALUES_LOOP)
+ # LOE rbx r15 r12d r13d
END(_ZGVeN8v_cosh_skx)
- .section .rodata, "a"
- .align 64
+ .section .rodata, "a"
+ .align 64
#ifdef __svml_dcosh_data_internal_typedef
typedef unsigned int VUINT32;
-typedef struct
-{
- __declspec(align(64)) VUINT32 _dTp_h[(1<<4)][2];
- __declspec(align(64)) VUINT32 _dTn_h[(1<<4)][2];
- __declspec(align(64)) VUINT32 _dbShifter_UISA[8][2];
- __declspec(align(64)) VUINT32 _dPC2_UISA[8][2];
- __declspec(align(64)) VUINT32 _dPC3_UISA[8][2];
- __declspec(align(64)) VUINT32 _dPC4_UISA[8][2];
- __declspec(align(64)) VUINT32 _dPC5_UISA[8][2];
- __declspec(align(64)) VUINT32 _dPC6_UISA[8][2];
- __declspec(align(64)) VUINT32 _dPC7_UISA[8][2];
- __declspec(align(64)) VUINT32 _dbInvLn2[8][2];
- __declspec(align(64)) VUINT32 _dbLn2hi[8][2];
- __declspec(align(64)) VUINT32 _dbLn2lo[8][2];
- __declspec(align(64)) VUINT32 _dbShifter[8][2];
- __declspec(align(64)) VUINT32 _dPC2[8][2];
- __declspec(align(64)) VUINT32 _dPC3[8][2];
- __declspec(align(64)) VUINT32 _dPC4[8][2];
- __declspec(align(64)) VUINT32 _lExpMask[8][2];
- __declspec(align(64)) VUINT32 _dSign[8][2]; //0x8000000000000000
- __declspec(align(64)) VUINT32 _iDomainRange[16][1];
+typedef struct {
+ __declspec(align(64)) VUINT32 _dTp_h[(1<<4)][2];
+ __declspec(align(64)) VUINT32 _dTn_h[(1<<4)][2];
+ __declspec(align(64)) VUINT32 _dbShifter_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dPC2_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dPC3_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dPC4_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dPC5_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dPC6_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dPC7_UISA[8][2];
+ __declspec(align(64)) VUINT32 _dbInvLn2[8][2];
+ __declspec(align(64)) VUINT32 _dbLn2hi[8][2];
+ __declspec(align(64)) VUINT32 _dbLn2lo[8][2];
+ __declspec(align(64)) VUINT32 _dbShifter[8][2];
+ __declspec(align(64)) VUINT32 _dPC2[8][2];
+ __declspec(align(64)) VUINT32 _dPC3[8][2];
+ __declspec(align(64)) VUINT32 _dPC4[8][2];
+ __declspec(align(64)) VUINT32 _lExpMask[8][2];
+ __declspec(align(64)) VUINT32 _dSign[8][2]; // 0x8000000000000000
+ __declspec(align(64)) VUINT32 _iDomainRange[16][1];
} __svml_dcosh_data_internal;
#endif
__svml_dcosh_data_internal:
- /*== _dTp_h ==*/
- .quad 0x3fe0000000000000, 0x3fe0b5586cf9890f, 0x3fe172b83c7d517b, 0x3fe2387a6e756238
- .quad 0x3fe306fe0a31b715, 0x3fe3dea64c123422, 0x3fe4bfdad5362a27, 0x3fe5ab07dd485429
- .quad 0x3fe6a09e667f3bcd, 0x3fe7a11473eb0187, 0x3fe8ace5422aa0db, 0x3fe9c49182a3f090
- .quad 0x3feae89f995ad3ad, 0x3fec199bdd85529c, 0x3fed5818dcfba487, 0x3feea4afa2a490da
- /*== dTn_h ==*/
- .align 64
- .quad 0x3fe0000000000000, 0x3fdea4afa2a490da, 0x3fdd5818dcfba487, 0x3fdc199bdd85529c
- .quad 0x3fdae89f995ad3ad, 0x3fd9c49182a3f090, 0x3fd8ace5422aa0db, 0x3fd7a11473eb0187
- .quad 0x3fd6a09e667f3bcd, 0x3fd5ab07dd485429, 0x3fd4bfdad5362a27, 0x3fd3dea64c123422
- .quad 0x3fd306fe0a31b715, 0x3fd2387a6e756238, 0x3fd172b83c7d517b, 0x3fd0b5586cf9890f
- .align 64
- .quad 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000 /* _dbShifter_UISA */
- .align 64
- .quad 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004 /* _dPC2_UISA */
- .align 64
- .quad 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543 /* _dPC3_UISA */
- .align 64
- .quad 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37 /* _dPC4_UISA */
- .align 64
- .quad 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c /* _dPC5_UISA */
- .align 64
- .quad 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116 /* _dPC6_UISA */
- .align 64
- .quad 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da /* _dPC7_UISA */
- /*== _dbT ==*/
- .align 64
- .quad 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe /* _dbInvLn2 = 1/log(2) */
- .align 64
- .quad 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000 /* _dbLn2hi = log(2) hi*/
- .align 64
- .quad 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899 /* _dbLn2lo = log(2) lo*/
- .align 64
- .quad 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000 /* _dbShifter */
- .align 64
- .quad 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD /* _dPC2 */
- .align 64
- .quad 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14 /* _dPC3 */
- .align 64
- .quad 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299 /* _dPC4 */
- .align 64
- .quad 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000 /* _lExpMask */
- .align 64
- .quad 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000 /* _dSign*/
- .align 64
- .long 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99 /* _iDomainRange 0x40861d9ac12a3e85 =(1021*2^K-0.5)*log(2)/2^K -needed for quick exp*/
- .align 64
- .type __svml_dcosh_data_internal,@object
- .size __svml_dcosh_data_internal,.-__svml_dcosh_data_internal
+ /* _dTp_h */
+ .quad 0x3fe0000000000000, 0x3fe0b5586cf9890f, 0x3fe172b83c7d517b, 0x3fe2387a6e756238
+ .quad 0x3fe306fe0a31b715, 0x3fe3dea64c123422, 0x3fe4bfdad5362a27, 0x3fe5ab07dd485429
+ .quad 0x3fe6a09e667f3bcd, 0x3fe7a11473eb0187, 0x3fe8ace5422aa0db, 0x3fe9c49182a3f090
+ .quad 0x3feae89f995ad3ad, 0x3fec199bdd85529c, 0x3fed5818dcfba487, 0x3feea4afa2a490da
+ /* dTn_h */
+ .align 64
+ .quad 0x3fe0000000000000, 0x3fdea4afa2a490da, 0x3fdd5818dcfba487, 0x3fdc199bdd85529c
+ .quad 0x3fdae89f995ad3ad, 0x3fd9c49182a3f090, 0x3fd8ace5422aa0db, 0x3fd7a11473eb0187
+ .quad 0x3fd6a09e667f3bcd, 0x3fd5ab07dd485429, 0x3fd4bfdad5362a27, 0x3fd3dea64c123422
+ .quad 0x3fd306fe0a31b715, 0x3fd2387a6e756238, 0x3fd172b83c7d517b, 0x3fd0b5586cf9890f
+ .align 64
+ .quad 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000, 0x42F8000000000000 /* _dbShifter_UISA */
+ .align 64
+ .quad 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004, 0x3fe0000000000004 /* _dPC2_UISA */
+ .align 64
+ .quad 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543, 0x3fc5555555555543 /* _dPC3_UISA */
+ .align 64
+ .quad 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37, 0x3fa5555555484f37 /* _dPC4_UISA */
+ .align 64
+ .quad 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c, 0x3f81111111286a0c /* _dPC5_UISA */
+ .align 64
+ .quad 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116, 0x3f56c183da08f116 /* _dPC6_UISA */
+ .align 64
+ .quad 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da, 0x3f2a018d76da03da /* _dPC7_UISA */
+ /* _dbT */
+ .align 64
+ .quad 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe, 0x3ff71547652b82fe /* _dbInvLn2 = 1/log(2) */
+ .align 64
+ .quad 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000, 0x3FE62E42FEFC0000 /* _dbLn2hi = log(2) hi */
+ .align 64
+ .quad 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899, 0xBDAC610CA86C3899 /* _dbLn2lo = log(2) lo */
+ .align 64
+ .quad 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000, 0x42B8000000000000 /* _dbShifter */
+ .align 64
+ .quad 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD, 0x3FDFFFFFFFFFFDBD /* _dPC2 */
+ .align 64
+ .quad 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14, 0x3FC5555570813E14 /* _dPC3 */
+ .align 64
+ .quad 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299, 0x3FA55555CF16D299 /* _dPC4 */
+ .align 64
+ .quad 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000 /* _lExpMask */
+ .align 64
+ .quad 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000 /* _dSign */
+ .align 64
+ .long 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99, 0x40861d99 /* _iDomainRange 0x40861d9ac12a3e85 =(1021*2^K-0.5)*log(2)/2^K -needed for quick exp */
+ .align 64
+ .type __svml_dcosh_data_internal, @object
+ .size __svml_dcosh_data_internal, .-__svml_dcosh_data_internal
--
2.34.1
next prev parent reply other threads:[~2022-03-07 15:02 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 14:59 [PATCH 000/126] x86_64: Fix libmvec assembly " Sunil K Pandey
2022-03-07 14:59 ` [PATCH 001/126] x86_64: Fix svml_s_acosf16_core_avx512.S " Sunil K Pandey
2022-03-07 21:50 ` Sunil Pandey
2022-03-07 22:52 ` Noah Goldstein
2022-03-07 14:59 ` [PATCH 002/126] x86_64: Fix svml_s_acosf4_core_sse4.S " Sunil K Pandey
2022-03-07 14:59 ` [PATCH 003/126] x86_64: Fix svml_s_acosf8_core_avx2.S " Sunil K Pandey
2022-03-07 14:59 ` [PATCH 004/126] x86_64: Fix svml_d_acos2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 005/126] x86_64: Fix svml_d_acos4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 006/126] x86_64: Fix svml_d_acos8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 007/126] x86_64: Fix svml_s_acoshf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 008/126] x86_64: Fix svml_s_acoshf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 009/126] x86_64: Fix svml_s_acoshf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 010/126] x86_64: Fix svml_d_acosh2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 011/126] x86_64: Fix svml_d_acosh4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 012/126] x86_64: Fix svml_d_acosh8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 013/126] x86_64: Fix svml_s_asinf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 014/126] x86_64: Fix svml_s_asinf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 015/126] x86_64: Fix svml_s_asinf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 016/126] x86_64: Fix svml_d_asin2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 017/126] x86_64: Fix svml_d_asin4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 018/126] x86_64: Fix svml_d_asin8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 019/126] x86_64: Fix svml_s_asinhf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 020/126] x86_64: Fix svml_s_asinhf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 021/126] x86_64: Fix svml_s_asinhf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 022/126] x86_64: Fix svml_d_asinh2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 023/126] x86_64: Fix svml_d_asinh4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 024/126] x86_64: Fix svml_d_asinh8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 025/126] x86_64: Fix svml_s_atanf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 026/126] x86_64: Fix svml_s_atanf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 027/126] x86_64: Fix svml_s_atanf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 028/126] x86_64: Fix svml_d_atan2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 029/126] x86_64: Fix svml_d_atan4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 030/126] x86_64: Fix svml_d_atan8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 031/126] x86_64: Fix svml_s_atan2f16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 032/126] x86_64: Fix svml_s_atan2f4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 033/126] x86_64: Fix svml_s_atan2f8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 034/126] x86_64: Fix svml_d_atan22_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 035/126] x86_64: Fix svml_d_atan24_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 036/126] x86_64: Fix svml_d_atan28_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 037/126] x86_64: Fix svml_s_atanhf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 038/126] x86_64: Fix svml_s_atanhf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 039/126] x86_64: Fix svml_s_atanhf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 040/126] x86_64: Fix svml_d_atanh2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 041/126] x86_64: Fix svml_d_atanh4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 042/126] x86_64: Fix svml_d_atanh8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 043/126] x86_64: Fix svml_s_cbrtf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 044/126] x86_64: Fix svml_s_cbrtf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 045/126] x86_64: Fix svml_s_cbrtf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 046/126] x86_64: Fix svml_d_cbrt2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 047/126] x86_64: Fix svml_d_cbrt4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 048/126] x86_64: Fix svml_d_cbrt8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 049/126] x86_64: Fix svml_s_coshf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 050/126] x86_64: Fix svml_s_coshf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 051/126] x86_64: Fix svml_s_coshf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 052/126] x86_64: Fix svml_d_cosh2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 053/126] x86_64: Fix svml_d_cosh4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` Sunil K Pandey [this message]
2022-03-07 15:00 ` [PATCH 055/126] x86_64: Fix svml_s_erff16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 056/126] x86_64: Fix svml_s_erff4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 057/126] x86_64: Fix svml_s_erff8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 058/126] x86_64: Fix svml_d_erf2_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 059/126] x86_64: Fix svml_d_erf4_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 060/126] x86_64: Fix svml_d_erf8_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 061/126] x86_64: Fix svml_s_erfcf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 062/126] x86_64: Fix svml_s_erfcf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 063/126] x86_64: Fix svml_s_erfcf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:00 ` [PATCH 064/126] x86_64: Fix svml_d_erfc2_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 065/126] x86_64: Fix svml_d_erfc4_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 066/126] x86_64: Fix svml_d_erfc8_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 067/126] x86_64: Fix svml_s_exp10f16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 068/126] x86_64: Fix svml_s_exp10f4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 069/126] x86_64: Fix svml_s_exp10f8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 070/126] x86_64: Fix svml_d_exp102_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 071/126] x86_64: Fix svml_d_exp104_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 072/126] x86_64: Fix svml_d_exp108_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 073/126] x86_64: Fix svml_s_exp2f16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 074/126] x86_64: Fix svml_s_exp2f4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 075/126] x86_64: Fix svml_s_exp2f8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 076/126] x86_64: Fix svml_d_exp22_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 077/126] x86_64: Fix svml_d_exp24_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 078/126] x86_64: Fix svml_d_exp28_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 079/126] x86_64: Fix svml_s_expm1f16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 080/126] x86_64: Fix svml_s_expm1f4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 081/126] x86_64: Fix svml_s_expm1f8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 082/126] x86_64: Fix svml_d_expm12_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 083/126] x86_64: Fix svml_d_expm14_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 084/126] x86_64: Fix svml_d_expm18_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 085/126] x86_64: Fix svml_s_hypotf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 086/126] x86_64: Fix svml_s_hypotf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 087/126] x86_64: Fix svml_s_hypotf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 088/126] x86_64: Fix svml_d_hypot2_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 089/126] x86_64: Fix svml_d_hypot4_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 090/126] x86_64: Fix svml_d_hypot8_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 091/126] x86_64: Fix svml_s_log10f16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 092/126] x86_64: Fix svml_s_log10f4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 093/126] x86_64: Fix svml_s_log10f8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 094/126] x86_64: Fix svml_d_log102_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 095/126] x86_64: Fix svml_d_log104_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 096/126] x86_64: Fix svml_d_log108_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 097/126] x86_64: Fix svml_s_log1pf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 098/126] x86_64: Fix svml_s_log1pf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 099/126] x86_64: Fix svml_s_log1pf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 100/126] x86_64: Fix svml_d_log1p2_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 101/126] x86_64: Fix svml_d_log1p4_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 102/126] x86_64: Fix svml_d_log1p8_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 103/126] x86_64: Fix svml_s_log2f16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 104/126] x86_64: Fix svml_s_log2f4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 105/126] x86_64: Fix svml_s_log2f8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 106/126] x86_64: Fix svml_d_log22_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 107/126] x86_64: Fix svml_d_log24_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 108/126] x86_64: Fix svml_d_log28_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 109/126] x86_64: Fix svml_s_sinhf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 110/126] x86_64: Fix svml_s_sinhf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 111/126] x86_64: Fix svml_s_sinhf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 112/126] x86_64: Fix svml_d_sinh2_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 113/126] x86_64: Fix svml_d_sinh4_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 114/126] x86_64: Fix svml_d_sinh8_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 115/126] x86_64: Fix svml_s_tanf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 116/126] x86_64: Fix svml_s_tanf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 117/126] x86_64: Fix svml_s_tanf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 118/126] x86_64: Fix svml_d_tan2_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 119/126] x86_64: Fix svml_d_tan4_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 120/126] x86_64: Fix svml_d_tan8_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 121/126] x86_64: Fix svml_s_tanhf16_core_avx512.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 122/126] x86_64: Fix svml_s_tanhf4_core_sse4.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 123/126] x86_64: Fix svml_s_tanhf8_core_avx2.S " Sunil K Pandey
2022-03-07 15:01 ` [PATCH 124/126] x86_64: Fix svml_d_tanh2_core_sse4.S " Sunil K Pandey
2022-03-07 15:02 ` [PATCH 125/126] x86_64: Fix svml_d_tanh4_core_avx2.S " Sunil K Pandey
2022-03-07 15:02 ` [PATCH 126/126] x86_64: Fix svml_d_tanh8_core_avx512.S " Sunil K Pandey
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