* [PATCH v2] linux: add RISC-V rseq signature
@ 2022-06-14 14:46 Michael Jeanson
0 siblings, 0 replies; only message in thread
From: Michael Jeanson @ 2022-06-14 14:46 UTC (permalink / raw)
To: fweimer; +Cc: carlos, libc-alpha, mathieu.desnoyers, Michael Jeanson
The rseq syscall for the RISC-V architecture was added in Linux 5.18.
---
sysdeps/unix/sysv/linux/riscv/bits/rseq.h | 43 +++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/rseq.h
diff --git a/sysdeps/unix/sysv/linux/riscv/bits/rseq.h b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h
new file mode 100644
index 0000000000..59d1bb24fa
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h
@@ -0,0 +1,43 @@
+/* Restartable Sequences Linux RISC-V architecture header.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _SYS_RSEQ_H
+# error "Never use <bits/rseq.h> directly; include <sys/rseq.h> instead."
+#endif
+
+#include <bits/endian.h>
+
+/*
+ RSEQ_SIG is a signature required before each abort handler code.
+
+ It is a 32-bit value that maps to actual architecture code compiled
+ into applications and libraries. It needs to be defined for each
+ architecture. When choosing this value, it needs to be taken into
+ account that generating invalid instructions may have ill effects on
+ tools like objdump, and may also have impact on the CPU speculative
+ execution efficiency in some cases.
+
+ Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike
+ other architectures, the ebreak instruction has no immediate field for
+ distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG.
+ "csrw mhartid, x0" can also satisfy the RSEQ requirement because it
+ is an uncommon instruction and will raise an illegal instruction
+ exception when executed in all modes. */
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define RSEQ_SIG 0xf1401073
+#endif
--
2.34.1
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