* [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265]
@ 2022-06-21 16:18 Noah Goldstein
2022-06-22 7:09 ` Siddhesh Poyarekar
` (8 more replies)
0 siblings, 9 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-21 16:18 UTC (permalink / raw)
To: libc-alpha
mbstows is defined if dst is NULL and is defined to special cased if
dst is NULL so the fortify objsize check if incorrect in that case.
Tested on x86-64 linux.
---
Note. I wasn't able to get the test to actually throw an error
before the change.
stdlib/Makefile | 3 +++
stdlib/bits/stdlib.h | 16 +++++++++++-----
stdlib/testmb.c | 7 +++++++
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/stdlib/Makefile b/stdlib/Makefile
index 60fc59c12c..6ef725ef74 100644
--- a/stdlib/Makefile
+++ b/stdlib/Makefile
@@ -373,6 +373,9 @@ CFLAGS-tst-qsort.c += $(stack-align-test-flags)
CFLAGS-tst-makecontext.c += -funwind-tables
CFLAGS-tst-makecontext2.c += $(stack-align-test-flags)
+CFLAGS-testmb.c += -D_FORTIFY_SOURCE=2 -Wall -Werror
+
+
# Run a test on the header files we use.
tests-special += $(objpfx)isomac.out
diff --git a/stdlib/bits/stdlib.h b/stdlib/bits/stdlib.h
index 277d099e22..9ab66db6a4 100644
--- a/stdlib/bits/stdlib.h
+++ b/stdlib/bits/stdlib.h
@@ -96,6 +96,11 @@ extern size_t __mbstowcs_chk (wchar_t *__restrict __dst,
const char *__restrict __src,
size_t __len, size_t __dstlen) __THROW
__attr_access ((__write_only__, 1, 3)) __attr_access ((__read_only__, 2));
+extern size_t __REDIRECT_NTH (__mbstowcs_chk_nulldst,
+ (wchar_t *__restrict __dst,
+ const char *__restrict __src,
+ size_t __len), mbstowcs_chk)
+ __attr_access ((__read_only__, 2));
extern size_t __REDIRECT_NTH (__mbstowcs_alias,
(wchar_t *__restrict __dst,
const char *__restrict __src,
@@ -108,16 +113,17 @@ extern size_t __REDIRECT_NTH (__mbstowcs_chk_warn,
__warnattr ("mbstowcs called with dst buffer smaller than len "
"* sizeof (wchar_t)");
-__fortify_function size_t
+__always_inline __fortify_function size_t
__NTH (mbstowcs (wchar_t *__restrict __dst, const char *__restrict __src,
size_t __len))
{
- return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
- __glibc_objsize (__dst),
- __dst, __src, __len);
+ if (__builtin_constant_p (__dst) && __dst == NULL)
+ return __mbstowcs_chk_nulldst (__dst, __src, __len);
+ else
+ return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
+ __glibc_objsize (__dst), __dst, __src, __len);
}
-
extern size_t __wcstombs_chk (char *__restrict __dst,
const wchar_t *__restrict __src,
size_t __len, size_t __dstlen) __THROW
diff --git a/stdlib/testmb.c b/stdlib/testmb.c
index 45dae7db61..6ac4dfd21d 100644
--- a/stdlib/testmb.c
+++ b/stdlib/testmb.c
@@ -16,6 +16,13 @@ main (int argc, char *argv[])
lose = 1;
}
+ i = mbstowcs (NULL, "bar", 4);
+ if (!(i == 3 && w[1] == 'a'))
+ {
+ puts ("mbstowcs FAILED2!");
+ lose = 1;
+ }
+
mbstowcs (w, "blah", 5);
i = wcstombs (c, w, 10);
if (i != 4)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265]
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
@ 2022-06-22 7:09 ` Siddhesh Poyarekar
2022-06-22 15:24 ` Noah Goldstein
2022-06-22 15:24 ` [PATCH v2] " Noah Goldstein
` (7 subsequent siblings)
8 siblings, 1 reply; 36+ messages in thread
From: Siddhesh Poyarekar @ 2022-06-22 7:09 UTC (permalink / raw)
To: Noah Goldstein, libc-alpha
On 21/06/2022 21:48, Noah Goldstein via Libc-alpha wrote:
> mbstows is defined if dst is NULL and is defined to special cased if
> dst is NULL so the fortify objsize check if incorrect in that case.
>
> Tested on x86-64 linux.
> ---
> Note. I wasn't able to get the test to actually throw an error
> before the change.
The test would rely on whether the middle end is able to fold away the
condition late enough, so it's flaky enough for us to not care about it.
It's fine to have it in though as a smoke test.
>
>
> stdlib/Makefile | 3 +++
> stdlib/bits/stdlib.h | 16 +++++++++++-----
> stdlib/testmb.c | 7 +++++++
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/stdlib/Makefile b/stdlib/Makefile
> index 60fc59c12c..6ef725ef74 100644
> --- a/stdlib/Makefile
> +++ b/stdlib/Makefile
> @@ -373,6 +373,9 @@ CFLAGS-tst-qsort.c += $(stack-align-test-flags)
> CFLAGS-tst-makecontext.c += -funwind-tables
> CFLAGS-tst-makecontext2.c += $(stack-align-test-flags)
>
> +CFLAGS-testmb.c += -D_FORTIFY_SOURCE=2 -Wall -Werror
> +
> +
> # Run a test on the header files we use.
> tests-special += $(objpfx)isomac.out
>
> diff --git a/stdlib/bits/stdlib.h b/stdlib/bits/stdlib.h
> index 277d099e22..9ab66db6a4 100644
> --- a/stdlib/bits/stdlib.h
> +++ b/stdlib/bits/stdlib.h
> @@ -96,6 +96,11 @@ extern size_t __mbstowcs_chk (wchar_t *__restrict __dst,
> const char *__restrict __src,
> size_t __len, size_t __dstlen) __THROW
> __attr_access ((__write_only__, 1, 3)) __attr_access ((__read_only__, 2));
> +extern size_t __REDIRECT_NTH (__mbstowcs_chk_nulldst,
> + (wchar_t *__restrict __dst,
> + const char *__restrict __src,
> + size_t __len), mbstowcs_chk)
> + __attr_access ((__read_only__, 2));
> extern size_t __REDIRECT_NTH (__mbstowcs_alias,
> (wchar_t *__restrict __dst,
> const char *__restrict __src,
> @@ -108,16 +113,17 @@ extern size_t __REDIRECT_NTH (__mbstowcs_chk_warn,
> __warnattr ("mbstowcs called with dst buffer smaller than len "
> "* sizeof (wchar_t)");
>
> -__fortify_function size_t
> +__always_inline __fortify_function size_t
> __NTH (mbstowcs (wchar_t *__restrict __dst, const char *__restrict __src,
> size_t __len))
> {
> - return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
> - __glibc_objsize (__dst),
> - __dst, __src, __len);
> + if (__builtin_constant_p (__dst) && __dst == NULL)
Perhaps a better condition would be __builtin_constant_p (__dst == NULL)
&& __dst == NULL so that it does not rely on __dst to be a constant.
For example, it could be a variable that the compiler decides can have
only a NULL value.
> + return __mbstowcs_chk_nulldst (__dst, __src, __len);
> + else
> + return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
> + __glibc_objsize (__dst), __dst, __src, __len);
OK.
> }
>
> -
> extern size_t __wcstombs_chk (char *__restrict __dst,
> const wchar_t *__restrict __src,
> size_t __len, size_t __dstlen) __THROW
> diff --git a/stdlib/testmb.c b/stdlib/testmb.c
> index 45dae7db61..6ac4dfd21d 100644
> --- a/stdlib/testmb.c
> +++ b/stdlib/testmb.c
> @@ -16,6 +16,13 @@ main (int argc, char *argv[])
> lose = 1;
> }
>
> + i = mbstowcs (NULL, "bar", 4);
> + if (!(i == 3 && w[1] == 'a'))
> + {
> + puts ("mbstowcs FAILED2!");
> + lose = 1;
> + }
> +
> mbstowcs (w, "blah", 5);
> i = wcstombs (c, w, 10);
> if (i != 4)
OK.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v2] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265]
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
2022-06-22 7:09 ` Siddhesh Poyarekar
@ 2022-06-22 15:24 ` Noah Goldstein
2022-06-22 15:30 ` Siddhesh Poyarekar
2022-06-22 17:11 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (6 subsequent siblings)
8 siblings, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 15:24 UTC (permalink / raw)
To: libc-alpha
mbstows is defined if dst is NULL and is defined to special cased if
dst is NULL so the fortify objsize check if incorrect in that case.
Tested on x86-64 linux.
---
stdlib/Makefile | 3 +++
stdlib/bits/stdlib.h | 16 +++++++++++-----
stdlib/testmb.c | 7 +++++++
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/stdlib/Makefile b/stdlib/Makefile
index 60fc59c12c..6ef725ef74 100644
--- a/stdlib/Makefile
+++ b/stdlib/Makefile
@@ -373,6 +373,9 @@ CFLAGS-tst-qsort.c += $(stack-align-test-flags)
CFLAGS-tst-makecontext.c += -funwind-tables
CFLAGS-tst-makecontext2.c += $(stack-align-test-flags)
+CFLAGS-testmb.c += -D_FORTIFY_SOURCE=2 -Wall -Werror
+
+
# Run a test on the header files we use.
tests-special += $(objpfx)isomac.out
diff --git a/stdlib/bits/stdlib.h b/stdlib/bits/stdlib.h
index 277d099e22..d9c2d822a5 100644
--- a/stdlib/bits/stdlib.h
+++ b/stdlib/bits/stdlib.h
@@ -96,6 +96,11 @@ extern size_t __mbstowcs_chk (wchar_t *__restrict __dst,
const char *__restrict __src,
size_t __len, size_t __dstlen) __THROW
__attr_access ((__write_only__, 1, 3)) __attr_access ((__read_only__, 2));
+extern size_t __REDIRECT_NTH (__mbstowcs_chk_nulldst,
+ (wchar_t *__restrict __dst,
+ const char *__restrict __src,
+ size_t __len), mbstowcs_chk)
+ __attr_access ((__read_only__, 2));
extern size_t __REDIRECT_NTH (__mbstowcs_alias,
(wchar_t *__restrict __dst,
const char *__restrict __src,
@@ -108,16 +113,17 @@ extern size_t __REDIRECT_NTH (__mbstowcs_chk_warn,
__warnattr ("mbstowcs called with dst buffer smaller than len "
"* sizeof (wchar_t)");
-__fortify_function size_t
+__always_inline __fortify_function size_t
__NTH (mbstowcs (wchar_t *__restrict __dst, const char *__restrict __src,
size_t __len))
{
- return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
- __glibc_objsize (__dst),
- __dst, __src, __len);
+ if (__builtin_constant_p (__dst == NULL) && __dst == NULL)
+ return __mbstowcs_chk_nulldst (__dst, __src, __len);
+ else
+ return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
+ __glibc_objsize (__dst), __dst, __src, __len);
}
-
extern size_t __wcstombs_chk (char *__restrict __dst,
const wchar_t *__restrict __src,
size_t __len, size_t __dstlen) __THROW
diff --git a/stdlib/testmb.c b/stdlib/testmb.c
index 45dae7db61..6ac4dfd21d 100644
--- a/stdlib/testmb.c
+++ b/stdlib/testmb.c
@@ -16,6 +16,13 @@ main (int argc, char *argv[])
lose = 1;
}
+ i = mbstowcs (NULL, "bar", 4);
+ if (!(i == 3 && w[1] == 'a'))
+ {
+ puts ("mbstowcs FAILED2!");
+ lose = 1;
+ }
+
mbstowcs (w, "blah", 5);
i = wcstombs (c, w, 10);
if (i != 4)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265]
2022-06-22 7:09 ` Siddhesh Poyarekar
@ 2022-06-22 15:24 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 15:24 UTC (permalink / raw)
To: Siddhesh Poyarekar; +Cc: GNU C Library
On Wed, Jun 22, 2022 at 12:09 AM Siddhesh Poyarekar <siddhesh@gotplt.org> wrote:
>
> On 21/06/2022 21:48, Noah Goldstein via Libc-alpha wrote:
> > mbstows is defined if dst is NULL and is defined to special cased if
> > dst is NULL so the fortify objsize check if incorrect in that case.
> >
> > Tested on x86-64 linux.
> > ---
> > Note. I wasn't able to get the test to actually throw an error
> > before the change.
>
> The test would rely on whether the middle end is able to fold away the
> condition late enough, so it's flaky enough for us to not care about it.
> It's fine to have it in though as a smoke test.
Alright.
>
> >
> >
> > stdlib/Makefile | 3 +++
> > stdlib/bits/stdlib.h | 16 +++++++++++-----
> > stdlib/testmb.c | 7 +++++++
> > 3 files changed, 21 insertions(+), 5 deletions(-)
> >
> > diff --git a/stdlib/Makefile b/stdlib/Makefile
> > index 60fc59c12c..6ef725ef74 100644
> > --- a/stdlib/Makefile
> > +++ b/stdlib/Makefile
> > @@ -373,6 +373,9 @@ CFLAGS-tst-qsort.c += $(stack-align-test-flags)
> > CFLAGS-tst-makecontext.c += -funwind-tables
> > CFLAGS-tst-makecontext2.c += $(stack-align-test-flags)
> >
> > +CFLAGS-testmb.c += -D_FORTIFY_SOURCE=2 -Wall -Werror
> > +
> > +
> > # Run a test on the header files we use.
> > tests-special += $(objpfx)isomac.out
> >
> > diff --git a/stdlib/bits/stdlib.h b/stdlib/bits/stdlib.h
> > index 277d099e22..9ab66db6a4 100644
> > --- a/stdlib/bits/stdlib.h
> > +++ b/stdlib/bits/stdlib.h
> > @@ -96,6 +96,11 @@ extern size_t __mbstowcs_chk (wchar_t *__restrict __dst,
> > const char *__restrict __src,
> > size_t __len, size_t __dstlen) __THROW
> > __attr_access ((__write_only__, 1, 3)) __attr_access ((__read_only__, 2));
> > +extern size_t __REDIRECT_NTH (__mbstowcs_chk_nulldst,
> > + (wchar_t *__restrict __dst,
> > + const char *__restrict __src,
> > + size_t __len), mbstowcs_chk)
> > + __attr_access ((__read_only__, 2));
> > extern size_t __REDIRECT_NTH (__mbstowcs_alias,
> > (wchar_t *__restrict __dst,
> > const char *__restrict __src,
> > @@ -108,16 +113,17 @@ extern size_t __REDIRECT_NTH (__mbstowcs_chk_warn,
> > __warnattr ("mbstowcs called with dst buffer smaller than len "
> > "* sizeof (wchar_t)");
> >
> > -__fortify_function size_t
> > +__always_inline __fortify_function size_t
> > __NTH (mbstowcs (wchar_t *__restrict __dst, const char *__restrict __src,
> > size_t __len))
> > {
> > - return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
> > - __glibc_objsize (__dst),
> > - __dst, __src, __len);
> > + if (__builtin_constant_p (__dst) && __dst == NULL)
>
> Perhaps a better condition would be __builtin_constant_p (__dst == NULL)
> && __dst == NULL so that it does not rely on __dst to be a constant.
> For example, it could be a variable that the compiler decides can have
> only a NULL value.
>
Bright. Fixed in v2.
> > + return __mbstowcs_chk_nulldst (__dst, __src, __len);
> > + else
> > + return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
> > + __glibc_objsize (__dst), __dst, __src, __len);
>
> OK.
>
> > }
> >
> > -
> > extern size_t __wcstombs_chk (char *__restrict __dst,
> > const wchar_t *__restrict __src,
> > size_t __len, size_t __dstlen) __THROW
> > diff --git a/stdlib/testmb.c b/stdlib/testmb.c
> > index 45dae7db61..6ac4dfd21d 100644
> > --- a/stdlib/testmb.c
> > +++ b/stdlib/testmb.c
> > @@ -16,6 +16,13 @@ main (int argc, char *argv[])
> > lose = 1;
> > }
> >
> > + i = mbstowcs (NULL, "bar", 4);
> > + if (!(i == 3 && w[1] == 'a'))
> > + {
> > + puts ("mbstowcs FAILED2!");
> > + lose = 1;
> > + }
> > +
> > mbstowcs (w, "blah", 5);
> > i = wcstombs (c, w, 10);
> > if (i != 4)
>
> OK.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265]
2022-06-22 15:24 ` [PATCH v2] " Noah Goldstein
@ 2022-06-22 15:30 ` Siddhesh Poyarekar
0 siblings, 0 replies; 36+ messages in thread
From: Siddhesh Poyarekar @ 2022-06-22 15:30 UTC (permalink / raw)
To: Noah Goldstein, libc-alpha
On 22/06/2022 20:54, Noah Goldstein via Libc-alpha wrote:
> mbstows is defined if dst is NULL and is defined to special cased if
> dst is NULL so the fortify objsize check if incorrect in that case.
>
> Tested on x86-64 linux.
> ---
> stdlib/Makefile | 3 +++
> stdlib/bits/stdlib.h | 16 +++++++++++-----
> stdlib/testmb.c | 7 +++++++
> 3 files changed, 21 insertions(+), 5 deletions(-)
LGTM.
Reviewed-by: Siddhesh Poyarekar <siddhesh@sourceware.org>
>
> diff --git a/stdlib/Makefile b/stdlib/Makefile
> index 60fc59c12c..6ef725ef74 100644
> --- a/stdlib/Makefile
> +++ b/stdlib/Makefile
> @@ -373,6 +373,9 @@ CFLAGS-tst-qsort.c += $(stack-align-test-flags)
> CFLAGS-tst-makecontext.c += -funwind-tables
> CFLAGS-tst-makecontext2.c += $(stack-align-test-flags)
>
> +CFLAGS-testmb.c += -D_FORTIFY_SOURCE=2 -Wall -Werror
> +
> +
> # Run a test on the header files we use.
> tests-special += $(objpfx)isomac.out
>
> diff --git a/stdlib/bits/stdlib.h b/stdlib/bits/stdlib.h
> index 277d099e22..d9c2d822a5 100644
> --- a/stdlib/bits/stdlib.h
> +++ b/stdlib/bits/stdlib.h
> @@ -96,6 +96,11 @@ extern size_t __mbstowcs_chk (wchar_t *__restrict __dst,
> const char *__restrict __src,
> size_t __len, size_t __dstlen) __THROW
> __attr_access ((__write_only__, 1, 3)) __attr_access ((__read_only__, 2));
> +extern size_t __REDIRECT_NTH (__mbstowcs_chk_nulldst,
> + (wchar_t *__restrict __dst,
> + const char *__restrict __src,
> + size_t __len), mbstowcs_chk)
> + __attr_access ((__read_only__, 2));
> extern size_t __REDIRECT_NTH (__mbstowcs_alias,
> (wchar_t *__restrict __dst,
> const char *__restrict __src,
> @@ -108,16 +113,17 @@ extern size_t __REDIRECT_NTH (__mbstowcs_chk_warn,
> __warnattr ("mbstowcs called with dst buffer smaller than len "
> "* sizeof (wchar_t)");
>
> -__fortify_function size_t
> +__always_inline __fortify_function size_t
> __NTH (mbstowcs (wchar_t *__restrict __dst, const char *__restrict __src,
> size_t __len))
> {
> - return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
> - __glibc_objsize (__dst),
> - __dst, __src, __len);
> + if (__builtin_constant_p (__dst == NULL) && __dst == NULL)
> + return __mbstowcs_chk_nulldst (__dst, __src, __len);
> + else
> + return __glibc_fortify_n (mbstowcs, __len, sizeof (wchar_t),
> + __glibc_objsize (__dst), __dst, __src, __len);
> }
>
> -
> extern size_t __wcstombs_chk (char *__restrict __dst,
> const wchar_t *__restrict __src,
> size_t __len, size_t __dstlen) __THROW
> diff --git a/stdlib/testmb.c b/stdlib/testmb.c
> index 45dae7db61..6ac4dfd21d 100644
> --- a/stdlib/testmb.c
> +++ b/stdlib/testmb.c
> @@ -16,6 +16,13 @@ main (int argc, char *argv[])
> lose = 1;
> }
>
> + i = mbstowcs (NULL, "bar", 4);
> + if (!(i == 3 && w[1] == 'a'))
> + {
> + puts ("mbstowcs FAILED2!");
> + lose = 1;
> + }
> +
> mbstowcs (w, "blah", 5);
> i = wcstombs (c, w, 10);
> if (i != 4)
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
2022-06-22 7:09 ` Siddhesh Poyarekar
2022-06-22 15:24 ` [PATCH v2] " Noah Goldstein
@ 2022-06-22 17:11 ` Noah Goldstein
2022-06-22 17:12 ` [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 17:14 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 18:11 ` [PATCH v9 " Noah Goldstein
` (5 subsequent siblings)
8 siblings, 2 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 17:11 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 95 +++++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++----
sysdeps/x86/isa-level.h | 99 +++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++++
5 files changed, 251 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..e48fa986d7
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,95 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (
+ __unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..21366b3132
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,99 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 17:11 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 17:12 ` Noah Goldstein
2022-06-22 17:50 ` H.J. Lu
2022-06-22 17:14 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 17:12 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 31 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 773 insertions(+), 607 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..a2f854b98d 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
+
+/* TODO: Look into using the ISA build level to remove some/all of the
+ feature checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -44,12 +48,19 @@ IFUNC_SELECTOR (void)
return OPTIMIZE (evex);
}
+ X86_ERROR_IF_REACHABLE_V4 ();
+
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..691662f0fb 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..10ed0434ae 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..acd5c15e22 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..73f4fa9589 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 17:11 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 17:12 ` [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 17:14 ` H.J. Lu
1 sibling, 0 replies; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 17:14 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 10:12 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86/init-arch.h | 4 +-
> sysdeps/x86/isa-ifunc-macros.h | 95 +++++++++++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++----
> sysdeps/x86/isa-level.h | 99 +++++++++++++++++++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++++
> 5 files changed, 251 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a2886a2532 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,9 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..e48fa986d7
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,95 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +#include <stdlib.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +
> +#ifndef X86_IFUNC_IMPL_ADD_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 4
> +__errordecl (
> + __unreachable_isa_above_4,
> + "This code should be unreachable if ISA level >= 4 build ");
> +# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V4()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 3
> +__errordecl (__unreachable_isa_above_3,
> + "This code should be unreachable if ISA level >= 3 build");
> +# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V3()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 2
> +__errordecl (__unreachable_isa_above_2,
> + "This code should be unreachable if ISA level >= 2 build");
> +# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V2()
> +#endif
No need for X86_ERROR_IF_REACHABLE_VN. Linker error
is sufficient.
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> +
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..21366b3132
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,99 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +
> +/*
> + * CPU Features that are hard coded as enabled depending on ISA build
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..34634668e5
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupported ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 17:12 ` [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 17:50 ` H.J. Lu
2022-06-22 18:10 ` Noah Goldstein
0 siblings, 1 reply; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 17:50 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 10:12 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Refactor files so that all implementations for in the multiarch
> directory.
> - Essentially moved sse2 {raw|w}memchr.S implementation to
> multiarch/{raw|w}memchr-sse2.S
>
> - The non-multiarch {raw|w}memchr.S file now only includes one of
> the implementations in the multiarch directory based on the
> compiled ISA level (only used for non-multiarch builds.
> Otherwise we go through the ifunc selector).
>
> 2. Add ISA level build guards to different implementations.
> - I.e memchr-avx2.S which is ISA level 3 will only build if
> compiled ISA level <= 3. Otherwise there is no reason to include
> it as we will always use one of the ISA level 4
> implementations (memchr-evex{-rtm}.S).
>
> 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> non-multiarch {raw}memchr.S which will in turn select the best
> implementation based on the compiled ISA level.
>
> 4. Refactor the ifunc selector and ifunc implementation list to use
> the ISA level aware wrapper macros that allow functions below the
> compiled ISA level (with a guranteed replacement) to be skipped.
> - Guranteed replacement essentially means that for any ISA level
> build there must be a function that the baseline of the ISA
> supports. So for {raw|w}memchr.S since there is not ISA level 2
> function, the ISA level 2 build still includes the ISA level
> 1 (sse2) function. Once we reach the ISA level 3 build, however,
> {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86_64/memchr.S | 355 +----------------
> sysdeps/x86_64/multiarch/ifunc-evex.h | 31 +-
> sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
> sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
> sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
> sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
> sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
> sysdeps/x86_64/rawmemchr.S | 186 +--------
> sysdeps/x86_64/wmemchr.S | 24 ++
> 20 files changed, 773 insertions(+), 607 deletions(-)
> create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> create mode 100644 sysdeps/x86_64/wmemchr.S
>
> diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> index a160fd9b00..018bb06f04 100644
> --- a/sysdeps/x86_64/memchr.S
> +++ b/sysdeps/x86_64/memchr.S
> @@ -15,358 +15,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define MEMCHR memchr
>
> -#ifdef USE_AS_WMEMCHR
> -# define MEMCHR wmemchr
> -# define PCMPEQ pcmpeqd
> -# define CHAR_PER_VEC 4
> -#else
> -# define MEMCHR memchr
> -# define PCMPEQ pcmpeqb
> -# define CHAR_PER_VEC 16
> -#endif
> +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
>
> -/* fast SSE2 version with using pmaxub and 64 byte loop */
> +#include "isa-default-impl.h"
>
> - .text
> -ENTRY(MEMCHR)
> - movd %esi, %xmm1
> - mov %edi, %ecx
> -
> -#ifdef __ILP32__
> - /* Clear the upper 32 bits. */
> - movl %edx, %edx
> -#endif
> -#ifdef USE_AS_WMEMCHR
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> -#else
> - punpcklbw %xmm1, %xmm1
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> - punpcklbw %xmm1, %xmm1
> -#endif
> -
> - and $63, %ecx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %ecx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - and $15, %ecx
> - and $-16, %rdi
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %ecx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - PCMPEQ %xmm1, %xmm0
> - /* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - /* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> - /* Check which byte is a match. */
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> - possible addition overflow. */
> - neg %rcx
> - add $16, %rcx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - sub %rcx, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - PCMPEQ %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - mov %rdi, %rcx
> - and $-64, %rdi
> - and $63, %ecx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> -
> - .p2align 4
> -L(align64_loop):
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - PCMPEQ %xmm1, %xmm0
> - PCMPEQ %xmm1, %xmm2
> - PCMPEQ %xmm1, %xmm3
> - PCMPEQ %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(exit_loop):
> - add $(CHAR_PER_VEC * 2), %edx
> - jle L(exit_loop_32)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32_1)
> - sub $CHAR_PER_VEC, %edx
> - jle L(return_null)
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches48_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(exit_loop_32):
> - add $(CHAR_PER_VEC * 2), %edx
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %edx
> - jbe L(return_null)
> -
> - PCMPEQ 16(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches16_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 16(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches32_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 32(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches48_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(return_null):
> - xor %eax, %eax
> - ret
> -END(MEMCHR)
> -
> -#ifndef USE_AS_WMEMCHR
> strong_alias (memchr, __memchr)
> libc_hidden_builtin_def(memchr)
> -#endif
> diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> index b8f7a12ea2..a2f854b98d 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> @@ -19,24 +19,28 @@
>
> #include <init-arch.h>
>
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
>
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
>
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
Unrelated changes.
> +/* TODO: Look into using the ISA build level to remove some/all of the
> + feature checks. */
This comment should be removed.
> static inline void *
> IFUNC_SELECTOR (void)
> {
> - const struct cpu_features* cpu_features = __get_cpu_features ();
> + const struct cpu_features *cpu_features = __get_cpu_features ();
>
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + AVX_Fast_Unaligned_Load))
> {
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (evex_rtm);
> @@ -44,12 +48,19 @@ IFUNC_SELECTOR (void)
> return OPTIMIZE (evex);
> }
>
> + X86_ERROR_IF_REACHABLE_V4 ();
> +
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (avx2_rtm);
>
> - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + Prefer_No_VZEROUPPER))
> return OPTIMIZE (avx2);
> }
>
> + X86_ERROR_IF_REACHABLE_V3 ();
> +
> + /* This is unreachable (compile time checked) if ISA level >= 3
> + so no need for a robust fallback here. */
> return OPTIMIZE (sse2);
> }
> diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> index 883362f63d..bf52cf96d0 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> @@ -25,7 +25,8 @@
>
> /* Fill ARRAY of MAX elements with IFUNC implementations for function
> NAME supported on target machine and return the number of valid
> - entries. */
> + entries. Each set of implementations for a given function is sorted in
> + descending order by ISA level. */
>
> size_t
> __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/memchr.c. */
> IFUNC_IMPL (i, name, memchr,
> - IFUNC_IMPL_ADD (array, i, memchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __memchr_avx2)
> - IFUNC_IMPL_ADD (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __memchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __memchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __memchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> + 1,
> + __memchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> IFUNC_IMPL (i, name, memcmp,
> @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> IFUNC_IMPL (i, name, rawmemchr,
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __rawmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __rawmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __rawmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __rawmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> + 1,
> + __rawmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/strlen.c. */
> IFUNC_IMPL (i, name, strlen,
> @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> IFUNC_IMPL (i, name, wmemchr,
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __wmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __wmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __wmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __wmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> + 1,
> + __wmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> IFUNC_IMPL (i, name, wmemcmp,
> diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> index c5a256eb37..691662f0fb 100644
> --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> @@ -16,7 +16,15 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
Where is IS_MULTIARCH defined?
> +# error "Multiarch build should never default include!"
> +#endif
> +
> +#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
>
> # include <sysdep.h>
>
> diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> index 0fd11b7632..10ed0434ae 100644
> --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> @@ -16,7 +16,15 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> +#endif
> +
> +#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
>
> # include <sysdep.h>
>
> diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> index 2c6fdd41d6..acd5c15e22 100644
> --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> @@ -16,13 +16,367 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> -# define memchr __memchr_sse2
> +#include <isa-level.h>
>
> -# undef strong_alias
> -# define strong_alias(memchr, __memchr)
> -# undef libc_hidden_builtin_def
> -# define libc_hidden_builtin_def(memchr)
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> #endif
>
> -#include "../memchr.S"
> +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> + need this to build for ISA V2 builds. */
> +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
> +
> +# include <sysdep.h>
> +
> +# ifndef MEMCHR
> +# define MEMCHR __memchr_sse2
> +# endif
> +# ifdef USE_AS_WMEMCHR
> +# define PCMPEQ pcmpeqd
> +# define CHAR_PER_VEC 4
> +# else
> +# define PCMPEQ pcmpeqb
> +# define CHAR_PER_VEC 16
> +# endif
> +
> +/* fast SSE2 version with using pmaxub and 64 byte loop */
> +
> + .text
> +ENTRY(MEMCHR)
> + movd %esi, %xmm1
> + mov %edi, %ecx
> +
> +# ifdef __ILP32__
> + /* Clear the upper 32 bits. */
> + movl %edx, %edx
> +# endif
> +# ifdef USE_AS_WMEMCHR
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> +# else
> + punpcklbw %xmm1, %xmm1
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> + punpcklbw %xmm1, %xmm1
> +# endif
> +
> + and $63, %ecx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %ecx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + and $15, %ecx
> + and $-16, %rdi
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %ecx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + PCMPEQ %xmm1, %xmm0
> + /* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + /* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> + /* Check which byte is a match. */
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> + possible addition overflow. */
> + neg %rcx
> + add $16, %rcx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + sub %rcx, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + PCMPEQ %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + mov %rdi, %rcx
> + and $-64, %rdi
> + and $63, %ecx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> +
> + .p2align 4
> +L(align64_loop):
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + PCMPEQ %xmm1, %xmm0
> + PCMPEQ %xmm1, %xmm2
> + PCMPEQ %xmm1, %xmm3
> + PCMPEQ %xmm1, %xmm4
> +
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(exit_loop):
> + add $(CHAR_PER_VEC * 2), %edx
> + jle L(exit_loop_32)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32_1)
> + sub $CHAR_PER_VEC, %edx
> + jle L(return_null)
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches48_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(exit_loop_32):
> + add $(CHAR_PER_VEC * 2), %edx
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %edx
> + jbe L(return_null)
> +
> + PCMPEQ 16(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches16_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 16(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches32_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 32(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches48_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(return_null):
> + xor %eax, %eax
> + ret
> +END(MEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> index acc5f6e2fb..5c1dcd3ca7 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2_rtm
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2_rtm
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> index 128f9ea637..d6bff28757 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> index deda1ca395..8ff7f27c9c 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> @@ -1,3 +1,7 @@
> -#define MEMCHR __rawmemchr_evex_rtm
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex_rtm
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
> +
> #include "memchr-evex-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> index ec942b77ba..dc1c450699 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_evex
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> index 3841c14c34..73f4fa9589 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> @@ -16,14 +16,199 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -/* Define multiple versions only for the definition in libc. */
> -#if IS_IN (libc)
> -# define __rawmemchr __rawmemchr_sse2
> -
> -# undef weak_alias
> -# define weak_alias(__rawmemchr, rawmemchr)
> -# undef libc_hidden_def
> -# define libc_hidden_def(__rawmemchr)
> +#include <isa-level.h>
> +
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> #endif
>
> -#include "../rawmemchr.S"
> +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> + need this to build for ISA V2 builds. */
> +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
> +
> +# include <sysdep.h>
> +
> +# ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_sse2
> +# endif
> +
> + .text
> +ENTRY (RAWMEMCHR)
> + movd %rsi, %xmm1
> + mov %rdi, %rcx
> +
> + punpcklbw %xmm1, %xmm1
> + punpcklbw %xmm1, %xmm1
> +
> + and $63, %rcx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %rcx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches)
> + add $16, %rdi
> + and $-16, %rdi
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %rcx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> +/* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> +/* Check which byte is a match. */
> + bsf %eax, %eax
> +
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + add $16, %rdi
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + pcmpeqb %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + and $-64, %rdi
> +
> + .p2align 4
> +L(align64_loop):
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + pcmpeqb %xmm1, %xmm0
> + pcmpeqb %xmm1, %xmm2
> + pcmpeqb %xmm1, %xmm3
> + pcmpeqb %xmm1, %xmm4
> +
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> +
> + pcmpeqb 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> +END (RAWMEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> new file mode 100644
> index 0000000000..a14b192bed
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../memchr.S"
> diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> new file mode 100644
> index 0000000000..5d4110a052
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../rawmemchr.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> index 58ed21db01..2a1cff5b05 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2_rtm
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2_rtm
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> index 282854f1a1..2bf93fd84b 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> index a346cd35a1..c67309e8a1 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> @@ -1,3 +1,7 @@
> -#define MEMCHR __wmemchr_evex_rtm
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex_rtm
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
> +
> #include "memchr-evex-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> index 06cd0f9f5a..5512d5cdc3 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_evex
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> index 70a965d552..3081fb6821 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> @@ -1,4 +1,25 @@
> -#define USE_AS_WMEMCHR 1
> -#define wmemchr __wmemchr_sse2
> +/* wmemchr optimized with SSE2
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
>
> -#include "../memchr.S"
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_sse2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
> +
> +#include "memchr-sse2.S"
> diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> index 4c1a3383b9..e401a2ac53 100644
> --- a/sysdeps/x86_64/rawmemchr.S
> +++ b/sysdeps/x86_64/rawmemchr.S
> @@ -17,185 +17,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define RAWMEMCHR rawmemchr
>
> - .text
> -ENTRY (__rawmemchr)
> - movd %rsi, %xmm1
> - mov %rdi, %rcx
> +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
>
> - punpcklbw %xmm1, %xmm1
> - punpcklbw %xmm1, %xmm1
> +#include "isa-default-impl.h"
>
> - and $63, %rcx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %rcx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches)
> - add $16, %rdi
> - and $-16, %rdi
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %rcx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> -/* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> -/* Check which byte is a match. */
> - bsf %eax, %eax
> -
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - add $16, %rdi
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - pcmpeqb %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - and $-64, %rdi
> -
> - .p2align 4
> -L(align64_loop):
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - pcmpeqb %xmm1, %xmm0
> - pcmpeqb %xmm1, %xmm2
> - pcmpeqb %xmm1, %xmm3
> - pcmpeqb %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> -
> - pcmpeqb 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> -END (__rawmemchr)
> -
> -weak_alias (__rawmemchr, rawmemchr)
> -libc_hidden_builtin_def (__rawmemchr)
> +strong_alias (rawmemchr, __rawmemchr)
> +libc_hidden_builtin_def (rawmemchr)
> diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> new file mode 100644
> index 0000000000..dd0490f86b
> --- /dev/null
> +++ b/sysdeps/x86_64/wmemchr.S
> @@ -0,0 +1,24 @@
> +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#define WMEMCHR wmemchr
> +
> +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> +
> +#include "isa-default-impl.h"
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 17:50 ` H.J. Lu
@ 2022-06-22 18:10 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 18:10 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 10:50 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 10:12 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Refactor files so that all implementations for in the multiarch
> > directory.
> > - Essentially moved sse2 {raw|w}memchr.S implementation to
> > multiarch/{raw|w}memchr-sse2.S
> >
> > - The non-multiarch {raw|w}memchr.S file now only includes one of
> > the implementations in the multiarch directory based on the
> > compiled ISA level (only used for non-multiarch builds.
> > Otherwise we go through the ifunc selector).
> >
> > 2. Add ISA level build guards to different implementations.
> > - I.e memchr-avx2.S which is ISA level 3 will only build if
> > compiled ISA level <= 3. Otherwise there is no reason to include
> > it as we will always use one of the ISA level 4
> > implementations (memchr-evex{-rtm}.S).
> >
> > 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> > non-multiarch {raw}memchr.S which will in turn select the best
> > implementation based on the compiled ISA level.
> >
> > 4. Refactor the ifunc selector and ifunc implementation list to use
> > the ISA level aware wrapper macros that allow functions below the
> > compiled ISA level (with a guranteed replacement) to be skipped.
> > - Guranteed replacement essentially means that for any ISA level
> > build there must be a function that the baseline of the ISA
> > supports. So for {raw|w}memchr.S since there is not ISA level 2
> > function, the ISA level 2 build still includes the ISA level
> > 1 (sse2) function. Once we reach the ISA level 3 build, however,
> > {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> > level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/x86_64/memchr.S | 355 +----------------
> > sysdeps/x86_64/multiarch/ifunc-evex.h | 31 +-
> > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> > sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
> > sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
> > sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
> > sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> > sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> > sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
> > sysdeps/x86_64/rawmemchr.S | 186 +--------
> > sysdeps/x86_64/wmemchr.S | 24 ++
> > 20 files changed, 773 insertions(+), 607 deletions(-)
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > create mode 100644 sysdeps/x86_64/wmemchr.S
> >
> > diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> > index a160fd9b00..018bb06f04 100644
> > --- a/sysdeps/x86_64/memchr.S
> > +++ b/sysdeps/x86_64/memchr.S
> > @@ -15,358 +15,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define MEMCHR memchr
> >
> > -#ifdef USE_AS_WMEMCHR
> > -# define MEMCHR wmemchr
> > -# define PCMPEQ pcmpeqd
> > -# define CHAR_PER_VEC 4
> > -#else
> > -# define MEMCHR memchr
> > -# define PCMPEQ pcmpeqb
> > -# define CHAR_PER_VEC 16
> > -#endif
> > +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
> >
> > -/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +#include "isa-default-impl.h"
> >
> > - .text
> > -ENTRY(MEMCHR)
> > - movd %esi, %xmm1
> > - mov %edi, %ecx
> > -
> > -#ifdef __ILP32__
> > - /* Clear the upper 32 bits. */
> > - movl %edx, %edx
> > -#endif
> > -#ifdef USE_AS_WMEMCHR
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > -#else
> > - punpcklbw %xmm1, %xmm1
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > - punpcklbw %xmm1, %xmm1
> > -#endif
> > -
> > - and $63, %ecx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %ecx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - and $15, %ecx
> > - and $-16, %rdi
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %ecx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - /* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - /* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > - /* Check which byte is a match. */
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > - possible addition overflow. */
> > - neg %rcx
> > - add $16, %rcx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - sub %rcx, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - PCMPEQ %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - mov %rdi, %rcx
> > - and $-64, %rdi
> > - and $63, %ecx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - PCMPEQ %xmm1, %xmm2
> > - PCMPEQ %xmm1, %xmm3
> > - PCMPEQ %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - jle L(exit_loop_32)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jle L(return_null)
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches48_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop_32):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jbe L(return_null)
> > -
> > - PCMPEQ 16(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches16_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 16(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 32(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches48_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(return_null):
> > - xor %eax, %eax
> > - ret
> > -END(MEMCHR)
> > -
> > -#ifndef USE_AS_WMEMCHR
> > strong_alias (memchr, __memchr)
> > libc_hidden_builtin_def(memchr)
> > -#endif
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > index b8f7a12ea2..a2f854b98d 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> > +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > @@ -19,24 +19,28 @@
> >
> > #include <init-arch.h>
> >
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
> >
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> >
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
>
> Unrelated changes.
They are now sorted / seperated by ISA level. Makes clearer.
>
> > +/* TODO: Look into using the ISA build level to remove some/all of the
> > + feature checks. */
>
> This comment should be removed.
>
> > static inline void *
> > IFUNC_SELECTOR (void)
> > {
> > - const struct cpu_features* cpu_features = __get_cpu_features ();
> > + const struct cpu_features *cpu_features = __get_cpu_features ();
> >
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + AVX_Fast_Unaligned_Load))
> > {
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > {
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (evex_rtm);
> > @@ -44,12 +48,19 @@ IFUNC_SELECTOR (void)
> > return OPTIMIZE (evex);
> > }
> >
> > + X86_ERROR_IF_REACHABLE_V4 ();
> > +
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (avx2_rtm);
> >
> > - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> > + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + Prefer_No_VZEROUPPER))
> > return OPTIMIZE (avx2);
> > }
> >
> > + X86_ERROR_IF_REACHABLE_V3 ();
> > +
> > + /* This is unreachable (compile time checked) if ISA level >= 3
> > + so no need for a robust fallback here. */
> > return OPTIMIZE (sse2);
> > }
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > index 883362f63d..bf52cf96d0 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > @@ -25,7 +25,8 @@
> >
> > /* Fill ARRAY of MAX elements with IFUNC implementations for function
> > NAME supported on target machine and return the number of valid
> > - entries. */
> > + entries. Each set of implementations for a given function is sorted in
> > + descending order by ISA level. */
> >
> > size_t
> > __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/memchr.c. */
> > IFUNC_IMPL (i, name, memchr,
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __memchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __memchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __memchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __memchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> > + 1,
> > + __memchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> > IFUNC_IMPL (i, name, memcmp,
> > @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> > IFUNC_IMPL (i, name, rawmemchr,
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __rawmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __rawmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __rawmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __rawmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> > + 1,
> > + __rawmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/strlen.c. */
> > IFUNC_IMPL (i, name, strlen,
> > @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> > IFUNC_IMPL (i, name, wmemchr,
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __wmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __wmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __wmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __wmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> > + 1,
> > + __wmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> > IFUNC_IMPL (i, name, wmemcmp,
> > diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > index c5a256eb37..691662f0fb 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > @@ -16,7 +16,15 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
>
> Where is IS_MULTIARCH defined?
>
>
> > +# error "Multiarch build should never default include!"
> > +#endif
> > +
> > +#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> >
> > # include <sysdep.h>
> >
> > diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> > index 0fd11b7632..10ed0434ae 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> > @@ -16,7 +16,15 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > +#endif
> > +
> > +#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> >
> > # include <sysdep.h>
> >
> > diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > index 2c6fdd41d6..acd5c15e22 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > @@ -16,13 +16,367 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > -# define memchr __memchr_sse2
> > +#include <isa-level.h>
> >
> > -# undef strong_alias
> > -# define strong_alias(memchr, __memchr)
> > -# undef libc_hidden_builtin_def
> > -# define libc_hidden_builtin_def(memchr)
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > #endif
> >
> > -#include "../memchr.S"
> > +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> > + need this to build for ISA V2 builds. */
> > +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> > +
> > +# include <sysdep.h>
> > +
> > +# ifndef MEMCHR
> > +# define MEMCHR __memchr_sse2
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > +# define PCMPEQ pcmpeqd
> > +# define CHAR_PER_VEC 4
> > +# else
> > +# define PCMPEQ pcmpeqb
> > +# define CHAR_PER_VEC 16
> > +# endif
> > +
> > +/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +
> > + .text
> > +ENTRY(MEMCHR)
> > + movd %esi, %xmm1
> > + mov %edi, %ecx
> > +
> > +# ifdef __ILP32__
> > + /* Clear the upper 32 bits. */
> > + movl %edx, %edx
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > +# else
> > + punpcklbw %xmm1, %xmm1
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > + punpcklbw %xmm1, %xmm1
> > +# endif
> > +
> > + and $63, %ecx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %ecx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + and $15, %ecx
> > + and $-16, %rdi
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %ecx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + /* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + /* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > + /* Check which byte is a match. */
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > + possible addition overflow. */
> > + neg %rcx
> > + add $16, %rcx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + sub %rcx, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + PCMPEQ %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + mov %rdi, %rcx
> > + and $-64, %rdi
> > + and $63, %ecx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + PCMPEQ %xmm1, %xmm2
> > + PCMPEQ %xmm1, %xmm3
> > + PCMPEQ %xmm1, %xmm4
> > +
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + jle L(exit_loop_32)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jle L(return_null)
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches48_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop_32):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jbe L(return_null)
> > +
> > + PCMPEQ 16(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches16_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 16(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 32(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches48_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(return_null):
> > + xor %eax, %eax
> > + ret
> > +END(MEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > index acc5f6e2fb..5c1dcd3ca7 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > index 128f9ea637..d6bff28757 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > index deda1ca395..8ff7f27c9c 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> > +
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > index ec942b77ba..dc1c450699 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > index 3841c14c34..73f4fa9589 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > @@ -16,14 +16,199 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -/* Define multiple versions only for the definition in libc. */
> > -#if IS_IN (libc)
> > -# define __rawmemchr __rawmemchr_sse2
> > -
> > -# undef weak_alias
> > -# define weak_alias(__rawmemchr, rawmemchr)
> > -# undef libc_hidden_def
> > -# define libc_hidden_def(__rawmemchr)
> > +#include <isa-level.h>
> > +
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > #endif
> >
> > -#include "../rawmemchr.S"
> > +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> > + need this to build for ISA V2 builds. */
> > +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> > +
> > +# include <sysdep.h>
> > +
> > +# ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_sse2
> > +# endif
> > +
> > + .text
> > +ENTRY (RAWMEMCHR)
> > + movd %rsi, %xmm1
> > + mov %rdi, %rcx
> > +
> > + punpcklbw %xmm1, %xmm1
> > + punpcklbw %xmm1, %xmm1
> > +
> > + and $63, %rcx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %rcx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches)
> > + add $16, %rdi
> > + and $-16, %rdi
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %rcx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > +/* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > +/* Check which byte is a match. */
> > + bsf %eax, %eax
> > +
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + add $16, %rdi
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + pcmpeqb %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + and $-64, %rdi
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + pcmpeqb %xmm1, %xmm0
> > + pcmpeqb %xmm1, %xmm2
> > + pcmpeqb %xmm1, %xmm3
> > + pcmpeqb %xmm1, %xmm4
> > +
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > +
> > + pcmpeqb 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > +END (RAWMEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > new file mode 100644
> > index 0000000000..a14b192bed
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../memchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > new file mode 100644
> > index 0000000000..5d4110a052
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../rawmemchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > index 58ed21db01..2a1cff5b05 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > index 282854f1a1..2bf93fd84b 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > index a346cd35a1..c67309e8a1 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __wmemchr_evex_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> > +
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > index 06cd0f9f5a..5512d5cdc3 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_evex
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > index 70a965d552..3081fb6821 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > @@ -1,4 +1,25 @@
> > -#define USE_AS_WMEMCHR 1
> > -#define wmemchr __wmemchr_sse2
> > +/* wmemchr optimized with SSE2
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> >
> > -#include "../memchr.S"
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_sse2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> > +
> > +#include "memchr-sse2.S"
> > diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> > index 4c1a3383b9..e401a2ac53 100644
> > --- a/sysdeps/x86_64/rawmemchr.S
> > +++ b/sysdeps/x86_64/rawmemchr.S
> > @@ -17,185 +17,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define RAWMEMCHR rawmemchr
> >
> > - .text
> > -ENTRY (__rawmemchr)
> > - movd %rsi, %xmm1
> > - mov %rdi, %rcx
> > +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
> >
> > - punpcklbw %xmm1, %xmm1
> > - punpcklbw %xmm1, %xmm1
> > +#include "isa-default-impl.h"
> >
> > - and $63, %rcx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %rcx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches)
> > - add $16, %rdi
> > - and $-16, %rdi
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %rcx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > -/* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > -/* Check which byte is a match. */
> > - bsf %eax, %eax
> > -
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - add $16, %rdi
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - pcmpeqb %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - and $-64, %rdi
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - pcmpeqb %xmm1, %xmm0
> > - pcmpeqb %xmm1, %xmm2
> > - pcmpeqb %xmm1, %xmm3
> > - pcmpeqb %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > -
> > - pcmpeqb 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > -END (__rawmemchr)
> > -
> > -weak_alias (__rawmemchr, rawmemchr)
> > -libc_hidden_builtin_def (__rawmemchr)
> > +strong_alias (rawmemchr, __rawmemchr)
> > +libc_hidden_builtin_def (rawmemchr)
> > diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> > new file mode 100644
> > index 0000000000..dd0490f86b
> > --- /dev/null
> > +++ b/sysdeps/x86_64/wmemchr.S
> > @@ -0,0 +1,24 @@
> > +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#define WMEMCHR wmemchr
> > +
> > +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> > +
> > +#include "isa-default-impl.h"
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v9 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
` (2 preceding siblings ...)
2022-06-22 17:11 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 18:11 ` Noah Goldstein
2022-06-22 18:11 ` [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 20:58 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (4 subsequent siblings)
8 siblings, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 18:11 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++----
sysdeps/x86/isa-level.h | 99 +++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++++
5 files changed, 226 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..ba6826d518
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,70 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..21366b3132
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,99 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 18:11 ` [PATCH v9 " Noah Goldstein
@ 2022-06-22 18:11 ` Noah Goldstein
2022-06-22 18:38 ` H.J. Lu
0 siblings, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 18:11 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 770 insertions(+), 608 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..856c6261f8 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
-
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ const struct cpu_features *cpu_features = __get_cpu_features ();
+
+ /* NB: The X86_ISA_* feature check macros are evaluated at
+ compile time. */
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..691662f0fb 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..10ed0434ae 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..acd5c15e22 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..73f4fa9589 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 18:11 ` [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 18:38 ` H.J. Lu
2022-06-22 18:50 ` Noah Goldstein
0 siblings, 1 reply; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 18:38 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 11:11 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Refactor files so that all implementations for in the multiarch
> directory.
> - Essentially moved sse2 {raw|w}memchr.S implementation to
> multiarch/{raw|w}memchr-sse2.S
>
> - The non-multiarch {raw|w}memchr.S file now only includes one of
> the implementations in the multiarch directory based on the
> compiled ISA level (only used for non-multiarch builds.
> Otherwise we go through the ifunc selector).
>
> 2. Add ISA level build guards to different implementations.
> - I.e memchr-avx2.S which is ISA level 3 will only build if
> compiled ISA level <= 3. Otherwise there is no reason to include
> it as we will always use one of the ISA level 4
> implementations (memchr-evex{-rtm}.S).
>
> 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> non-multiarch {raw}memchr.S which will in turn select the best
> implementation based on the compiled ISA level.
>
> 4. Refactor the ifunc selector and ifunc implementation list to use
> the ISA level aware wrapper macros that allow functions below the
> compiled ISA level (with a guranteed replacement) to be skipped.
> - Guranteed replacement essentially means that for any ISA level
> build there must be a function that the baseline of the ISA
> supports. So for {raw|w}memchr.S since there is not ISA level 2
> function, the ISA level 2 build still includes the ISA level
> 1 (sse2) function. Once we reach the ISA level 3 build, however,
> {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86_64/memchr.S | 355 +----------------
> sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
> sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
> sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
> sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
> sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
> sysdeps/x86_64/rawmemchr.S | 186 +--------
> sysdeps/x86_64/wmemchr.S | 24 ++
> 20 files changed, 770 insertions(+), 608 deletions(-)
> create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> create mode 100644 sysdeps/x86_64/wmemchr.S
>
> diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> index a160fd9b00..018bb06f04 100644
> --- a/sysdeps/x86_64/memchr.S
> +++ b/sysdeps/x86_64/memchr.S
> @@ -15,358 +15,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define MEMCHR memchr
>
> -#ifdef USE_AS_WMEMCHR
> -# define MEMCHR wmemchr
> -# define PCMPEQ pcmpeqd
> -# define CHAR_PER_VEC 4
> -#else
> -# define MEMCHR memchr
> -# define PCMPEQ pcmpeqb
> -# define CHAR_PER_VEC 16
> -#endif
> +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
>
> -/* fast SSE2 version with using pmaxub and 64 byte loop */
> +#include "isa-default-impl.h"
>
> - .text
> -ENTRY(MEMCHR)
> - movd %esi, %xmm1
> - mov %edi, %ecx
> -
> -#ifdef __ILP32__
> - /* Clear the upper 32 bits. */
> - movl %edx, %edx
> -#endif
> -#ifdef USE_AS_WMEMCHR
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> -#else
> - punpcklbw %xmm1, %xmm1
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> - punpcklbw %xmm1, %xmm1
> -#endif
> -
> - and $63, %ecx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %ecx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - and $15, %ecx
> - and $-16, %rdi
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %ecx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - PCMPEQ %xmm1, %xmm0
> - /* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - /* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> - /* Check which byte is a match. */
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> - possible addition overflow. */
> - neg %rcx
> - add $16, %rcx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - sub %rcx, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - PCMPEQ %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - mov %rdi, %rcx
> - and $-64, %rdi
> - and $63, %ecx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> -
> - .p2align 4
> -L(align64_loop):
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - PCMPEQ %xmm1, %xmm0
> - PCMPEQ %xmm1, %xmm2
> - PCMPEQ %xmm1, %xmm3
> - PCMPEQ %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(exit_loop):
> - add $(CHAR_PER_VEC * 2), %edx
> - jle L(exit_loop_32)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32_1)
> - sub $CHAR_PER_VEC, %edx
> - jle L(return_null)
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches48_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(exit_loop_32):
> - add $(CHAR_PER_VEC * 2), %edx
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %edx
> - jbe L(return_null)
> -
> - PCMPEQ 16(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches16_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 16(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches32_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 32(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches48_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(return_null):
> - xor %eax, %eax
> - ret
> -END(MEMCHR)
> -
> -#ifndef USE_AS_WMEMCHR
> strong_alias (memchr, __memchr)
> libc_hidden_builtin_def(memchr)
> -#endif
> diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> index b8f7a12ea2..856c6261f8 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> @@ -19,24 +19,28 @@
>
> #include <init-arch.h>
>
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
>
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> +
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
>
> static inline void *
> IFUNC_SELECTOR (void)
> {
> - const struct cpu_features* cpu_features = __get_cpu_features ();
> -
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> + const struct cpu_features *cpu_features = __get_cpu_features ();
> +
> + /* NB: The X86_ISA_* feature check macros are evaluated at
> + compile time. */
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + AVX_Fast_Unaligned_Load))
> {
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (evex_rtm);
> @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (avx2_rtm);
>
> - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + Prefer_No_VZEROUPPER))
> return OPTIMIZE (avx2);
> }
>
> + /* This is unreachable (compile time checked) if ISA level >= 3
> + so no need for a robust fallback here. */
> return OPTIMIZE (sse2);
> }
> diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> index 883362f63d..bf52cf96d0 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> @@ -25,7 +25,8 @@
>
> /* Fill ARRAY of MAX elements with IFUNC implementations for function
> NAME supported on target machine and return the number of valid
> - entries. */
> + entries. Each set of implementations for a given function is sorted in
> + descending order by ISA level. */
>
> size_t
> __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/memchr.c. */
> IFUNC_IMPL (i, name, memchr,
> - IFUNC_IMPL_ADD (array, i, memchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __memchr_avx2)
> - IFUNC_IMPL_ADD (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __memchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __memchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __memchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> + 1,
> + __memchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> IFUNC_IMPL (i, name, memcmp,
> @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> IFUNC_IMPL (i, name, rawmemchr,
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __rawmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __rawmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __rawmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __rawmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> + 1,
> + __rawmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/strlen.c. */
> IFUNC_IMPL (i, name, strlen,
> @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> IFUNC_IMPL (i, name, wmemchr,
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __wmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __wmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __wmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __wmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> + 1,
> + __wmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> IFUNC_IMPL (i, name, wmemcmp,
> diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> index c5a256eb37..691662f0fb 100644
> --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> @@ -16,7 +16,15 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> +#endif
> +
> +#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
>
> # include <sysdep.h>
>
> diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> index 0fd11b7632..10ed0434ae 100644
> --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> @@ -16,7 +16,15 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> +#endif
> +
> +#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
>
> # include <sysdep.h>
>
> diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> index 2c6fdd41d6..acd5c15e22 100644
> --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> @@ -16,13 +16,367 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> -# define memchr __memchr_sse2
> +#include <isa-level.h>
>
> -# undef strong_alias
> -# define strong_alias(memchr, __memchr)
> -# undef libc_hidden_builtin_def
> -# define libc_hidden_builtin_def(memchr)
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> #endif
>
> -#include "../memchr.S"
> +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> + need this to build for ISA V2 builds. */
> +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
> +
> +# include <sysdep.h>
> +
> +# ifndef MEMCHR
> +# define MEMCHR __memchr_sse2
> +# endif
> +# ifdef USE_AS_WMEMCHR
> +# define PCMPEQ pcmpeqd
> +# define CHAR_PER_VEC 4
> +# else
> +# define PCMPEQ pcmpeqb
> +# define CHAR_PER_VEC 16
> +# endif
> +
> +/* fast SSE2 version with using pmaxub and 64 byte loop */
> +
> + .text
> +ENTRY(MEMCHR)
> + movd %esi, %xmm1
> + mov %edi, %ecx
> +
> +# ifdef __ILP32__
> + /* Clear the upper 32 bits. */
> + movl %edx, %edx
> +# endif
> +# ifdef USE_AS_WMEMCHR
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> +# else
> + punpcklbw %xmm1, %xmm1
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> + punpcklbw %xmm1, %xmm1
> +# endif
> +
> + and $63, %ecx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %ecx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + and $15, %ecx
> + and $-16, %rdi
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %ecx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + PCMPEQ %xmm1, %xmm0
> + /* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + /* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> + /* Check which byte is a match. */
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> + possible addition overflow. */
> + neg %rcx
> + add $16, %rcx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + sub %rcx, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + PCMPEQ %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + mov %rdi, %rcx
> + and $-64, %rdi
> + and $63, %ecx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> +
> + .p2align 4
> +L(align64_loop):
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + PCMPEQ %xmm1, %xmm0
> + PCMPEQ %xmm1, %xmm2
> + PCMPEQ %xmm1, %xmm3
> + PCMPEQ %xmm1, %xmm4
> +
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(exit_loop):
> + add $(CHAR_PER_VEC * 2), %edx
> + jle L(exit_loop_32)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32_1)
> + sub $CHAR_PER_VEC, %edx
> + jle L(return_null)
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches48_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(exit_loop_32):
> + add $(CHAR_PER_VEC * 2), %edx
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %edx
> + jbe L(return_null)
> +
> + PCMPEQ 16(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches16_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 16(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches32_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 32(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches48_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(return_null):
> + xor %eax, %eax
> + ret
> +END(MEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> index acc5f6e2fb..5c1dcd3ca7 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2_rtm
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2_rtm
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> index 128f9ea637..d6bff28757 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> index deda1ca395..8ff7f27c9c 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> @@ -1,3 +1,7 @@
> -#define MEMCHR __rawmemchr_evex_rtm
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex_rtm
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
> +
> #include "memchr-evex-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> index ec942b77ba..dc1c450699 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_evex
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> index 3841c14c34..73f4fa9589 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> @@ -16,14 +16,199 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -/* Define multiple versions only for the definition in libc. */
> -#if IS_IN (libc)
> -# define __rawmemchr __rawmemchr_sse2
> -
> -# undef weak_alias
> -# define weak_alias(__rawmemchr, rawmemchr)
> -# undef libc_hidden_def
> -# define libc_hidden_def(__rawmemchr)
> +#include <isa-level.h>
> +
> +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> +# error "Multiarch build should never default include!"
> #endif
>
> -#include "../rawmemchr.S"
> +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> + need this to build for ISA V2 builds. */
> +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
> +
> +# include <sysdep.h>
> +
> +# ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_sse2
> +# endif
> +
> + .text
> +ENTRY (RAWMEMCHR)
> + movd %rsi, %xmm1
> + mov %rdi, %rcx
> +
> + punpcklbw %xmm1, %xmm1
> + punpcklbw %xmm1, %xmm1
> +
> + and $63, %rcx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %rcx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches)
> + add $16, %rdi
> + and $-16, %rdi
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %rcx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> +/* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> +/* Check which byte is a match. */
> + bsf %eax, %eax
> +
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + add $16, %rdi
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + pcmpeqb %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + and $-64, %rdi
> +
> + .p2align 4
> +L(align64_loop):
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + pcmpeqb %xmm1, %xmm0
> + pcmpeqb %xmm1, %xmm2
> + pcmpeqb %xmm1, %xmm3
> + pcmpeqb %xmm1, %xmm4
> +
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> +
> + pcmpeqb 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> +END (RAWMEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> new file mode 100644
> index 0000000000..a14b192bed
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../memchr.S"
> diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> new file mode 100644
> index 0000000000..5d4110a052
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../rawmemchr.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> index 58ed21db01..2a1cff5b05 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2_rtm
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2_rtm
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> index 282854f1a1..2bf93fd84b 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> index a346cd35a1..c67309e8a1 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> @@ -1,3 +1,7 @@
> -#define MEMCHR __wmemchr_evex_rtm
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex_rtm
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
> +
> #include "memchr-evex-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> index 06cd0f9f5a..5512d5cdc3 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_evex
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> index 70a965d552..3081fb6821 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> @@ -1,4 +1,25 @@
> -#define USE_AS_WMEMCHR 1
> -#define wmemchr __wmemchr_sse2
> +/* wmemchr optimized with SSE2
> + Copyright (C) 2022 Free Software Foundation, Inc.
This isn't a new file. Please leave out the copy right change.
> + This file is part of the GNU C Library.
>
> -#include "../memchr.S"
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_sse2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
> +
> +#include "memchr-sse2.S"
> diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> index 4c1a3383b9..e401a2ac53 100644
> --- a/sysdeps/x86_64/rawmemchr.S
> +++ b/sysdeps/x86_64/rawmemchr.S
> @@ -17,185 +17,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define RAWMEMCHR rawmemchr
>
> - .text
> -ENTRY (__rawmemchr)
> - movd %rsi, %xmm1
> - mov %rdi, %rcx
> +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
>
> - punpcklbw %xmm1, %xmm1
> - punpcklbw %xmm1, %xmm1
> +#include "isa-default-impl.h"
>
> - and $63, %rcx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %rcx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches)
> - add $16, %rdi
> - and $-16, %rdi
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %rcx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> -/* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> -/* Check which byte is a match. */
> - bsf %eax, %eax
> -
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - add $16, %rdi
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - pcmpeqb %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - and $-64, %rdi
> -
> - .p2align 4
> -L(align64_loop):
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - pcmpeqb %xmm1, %xmm0
> - pcmpeqb %xmm1, %xmm2
> - pcmpeqb %xmm1, %xmm3
> - pcmpeqb %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> -
> - pcmpeqb 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
.> - lea 32(%rax, %rdi), %rax/
bu> - ret
> -
> -END (__rawmemchr)
> -
> -weak_alias (__rawmemchr, rawmemchr)
> -libc_hidden_builtin_def (__rawmemchr)
> +strong_alias (rawmemchr, __rawmemchr)
> +libc_hidden_builtin_def (rawmemchr)
Why these changes?
> diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> new file mode 100644
> index 0000000000..dd0490f86b
> --- /dev/null
> +++ b/sysdeps/x86_64/wmemchr.S
> @@ -0,0 +1,24 @@
> +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#define WMEMCHR wmemchr
#define WMEMCHR __wmemchr
> +
> +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> +
> +#include "isa-default-impl.h"
> --
> 2.34.1
>
This should provide the same symbol as wcsmbs/wmemchr.c.
Have you tried --disable-multi-arch builds with different ISA levels?
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 18:38 ` H.J. Lu
@ 2022-06-22 18:50 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 18:50 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 11:38 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 11:11 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Refactor files so that all implementations for in the multiarch
> > directory.
> > - Essentially moved sse2 {raw|w}memchr.S implementation to
> > multiarch/{raw|w}memchr-sse2.S
> >
> > - The non-multiarch {raw|w}memchr.S file now only includes one of
> > the implementations in the multiarch directory based on the
> > compiled ISA level (only used for non-multiarch builds.
> > Otherwise we go through the ifunc selector).
> >
> > 2. Add ISA level build guards to different implementations.
> > - I.e memchr-avx2.S which is ISA level 3 will only build if
> > compiled ISA level <= 3. Otherwise there is no reason to include
> > it as we will always use one of the ISA level 4
> > implementations (memchr-evex{-rtm}.S).
> >
> > 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> > non-multiarch {raw}memchr.S which will in turn select the best
> > implementation based on the compiled ISA level.
> >
> > 4. Refactor the ifunc selector and ifunc implementation list to use
> > the ISA level aware wrapper macros that allow functions below the
> > compiled ISA level (with a guranteed replacement) to be skipped.
> > - Guranteed replacement essentially means that for any ISA level
> > build there must be a function that the baseline of the ISA
> > supports. So for {raw|w}memchr.S since there is not ISA level 2
> > function, the ISA level 2 build still includes the ISA level
> > 1 (sse2) function. Once we reach the ISA level 3 build, however,
> > {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> > level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/x86_64/memchr.S | 355 +----------------
> > sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> > sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
> > sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
> > sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
> > sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> > sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> > sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
> > sysdeps/x86_64/rawmemchr.S | 186 +--------
> > sysdeps/x86_64/wmemchr.S | 24 ++
> > 20 files changed, 770 insertions(+), 608 deletions(-)
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > create mode 100644 sysdeps/x86_64/wmemchr.S
> >
> > diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> > index a160fd9b00..018bb06f04 100644
> > --- a/sysdeps/x86_64/memchr.S
> > +++ b/sysdeps/x86_64/memchr.S
> > @@ -15,358 +15,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define MEMCHR memchr
> >
> > -#ifdef USE_AS_WMEMCHR
> > -# define MEMCHR wmemchr
> > -# define PCMPEQ pcmpeqd
> > -# define CHAR_PER_VEC 4
> > -#else
> > -# define MEMCHR memchr
> > -# define PCMPEQ pcmpeqb
> > -# define CHAR_PER_VEC 16
> > -#endif
> > +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
> >
> > -/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +#include "isa-default-impl.h"
> >
> > - .text
> > -ENTRY(MEMCHR)
> > - movd %esi, %xmm1
> > - mov %edi, %ecx
> > -
> > -#ifdef __ILP32__
> > - /* Clear the upper 32 bits. */
> > - movl %edx, %edx
> > -#endif
> > -#ifdef USE_AS_WMEMCHR
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > -#else
> > - punpcklbw %xmm1, %xmm1
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > - punpcklbw %xmm1, %xmm1
> > -#endif
> > -
> > - and $63, %ecx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %ecx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - and $15, %ecx
> > - and $-16, %rdi
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %ecx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - /* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - /* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > - /* Check which byte is a match. */
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > - possible addition overflow. */
> > - neg %rcx
> > - add $16, %rcx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - sub %rcx, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - PCMPEQ %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - mov %rdi, %rcx
> > - and $-64, %rdi
> > - and $63, %ecx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - PCMPEQ %xmm1, %xmm2
> > - PCMPEQ %xmm1, %xmm3
> > - PCMPEQ %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - jle L(exit_loop_32)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jle L(return_null)
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches48_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop_32):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jbe L(return_null)
> > -
> > - PCMPEQ 16(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches16_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 16(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 32(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches48_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(return_null):
> > - xor %eax, %eax
> > - ret
> > -END(MEMCHR)
> > -
> > -#ifndef USE_AS_WMEMCHR
> > strong_alias (memchr, __memchr)
> > libc_hidden_builtin_def(memchr)
> > -#endif
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > index b8f7a12ea2..856c6261f8 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> > +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > @@ -19,24 +19,28 @@
> >
> > #include <init-arch.h>
> >
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
> >
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > +
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> >
> > static inline void *
> > IFUNC_SELECTOR (void)
> > {
> > - const struct cpu_features* cpu_features = __get_cpu_features ();
> > -
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> > + const struct cpu_features *cpu_features = __get_cpu_features ();
> > +
> > + /* NB: The X86_ISA_* feature check macros are evaluated at
> > + compile time. */
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + AVX_Fast_Unaligned_Load))
> > {
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > {
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (evex_rtm);
> > @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (avx2_rtm);
> >
> > - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> > + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + Prefer_No_VZEROUPPER))
> > return OPTIMIZE (avx2);
> > }
> >
> > + /* This is unreachable (compile time checked) if ISA level >= 3
> > + so no need for a robust fallback here. */
> > return OPTIMIZE (sse2);
> > }
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > index 883362f63d..bf52cf96d0 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > @@ -25,7 +25,8 @@
> >
> > /* Fill ARRAY of MAX elements with IFUNC implementations for function
> > NAME supported on target machine and return the number of valid
> > - entries. */
> > + entries. Each set of implementations for a given function is sorted in
> > + descending order by ISA level. */
> >
> > size_t
> > __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/memchr.c. */
> > IFUNC_IMPL (i, name, memchr,
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __memchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __memchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __memchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __memchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> > + 1,
> > + __memchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> > IFUNC_IMPL (i, name, memcmp,
> > @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> > IFUNC_IMPL (i, name, rawmemchr,
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __rawmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __rawmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __rawmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __rawmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> > + 1,
> > + __rawmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/strlen.c. */
> > IFUNC_IMPL (i, name, strlen,
> > @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> > IFUNC_IMPL (i, name, wmemchr,
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __wmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __wmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __wmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __wmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> > + 1,
> > + __wmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> > IFUNC_IMPL (i, name, wmemcmp,
> > diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > index c5a256eb37..691662f0fb 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > @@ -16,7 +16,15 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > +#endif
> > +
> > +#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> >
> > # include <sysdep.h>
> >
> > diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> > index 0fd11b7632..10ed0434ae 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> > @@ -16,7 +16,15 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > +#endif
> > +
> > +#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> >
> > # include <sysdep.h>
> >
> > diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > index 2c6fdd41d6..acd5c15e22 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > @@ -16,13 +16,367 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > -# define memchr __memchr_sse2
> > +#include <isa-level.h>
> >
> > -# undef strong_alias
> > -# define strong_alias(memchr, __memchr)
> > -# undef libc_hidden_builtin_def
> > -# define libc_hidden_builtin_def(memchr)
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > #endif
> >
> > -#include "../memchr.S"
> > +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> > + need this to build for ISA V2 builds. */
> > +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> > +
> > +# include <sysdep.h>
> > +
> > +# ifndef MEMCHR
> > +# define MEMCHR __memchr_sse2
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > +# define PCMPEQ pcmpeqd
> > +# define CHAR_PER_VEC 4
> > +# else
> > +# define PCMPEQ pcmpeqb
> > +# define CHAR_PER_VEC 16
> > +# endif
> > +
> > +/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +
> > + .text
> > +ENTRY(MEMCHR)
> > + movd %esi, %xmm1
> > + mov %edi, %ecx
> > +
> > +# ifdef __ILP32__
> > + /* Clear the upper 32 bits. */
> > + movl %edx, %edx
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > +# else
> > + punpcklbw %xmm1, %xmm1
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > + punpcklbw %xmm1, %xmm1
> > +# endif
> > +
> > + and $63, %ecx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %ecx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + and $15, %ecx
> > + and $-16, %rdi
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %ecx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + /* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + /* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > + /* Check which byte is a match. */
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > + possible addition overflow. */
> > + neg %rcx
> > + add $16, %rcx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + sub %rcx, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + PCMPEQ %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + mov %rdi, %rcx
> > + and $-64, %rdi
> > + and $63, %ecx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + PCMPEQ %xmm1, %xmm2
> > + PCMPEQ %xmm1, %xmm3
> > + PCMPEQ %xmm1, %xmm4
> > +
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + jle L(exit_loop_32)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jle L(return_null)
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches48_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop_32):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jbe L(return_null)
> > +
> > + PCMPEQ 16(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches16_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 16(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 32(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches48_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(return_null):
> > + xor %eax, %eax
> > + ret
> > +END(MEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > index acc5f6e2fb..5c1dcd3ca7 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > index 128f9ea637..d6bff28757 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > index deda1ca395..8ff7f27c9c 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> > +
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > index ec942b77ba..dc1c450699 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > index 3841c14c34..73f4fa9589 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > @@ -16,14 +16,199 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -/* Define multiple versions only for the definition in libc. */
> > -#if IS_IN (libc)
> > -# define __rawmemchr __rawmemchr_sse2
> > -
> > -# undef weak_alias
> > -# define weak_alias(__rawmemchr, rawmemchr)
> > -# undef libc_hidden_def
> > -# define libc_hidden_def(__rawmemchr)
> > +#include <isa-level.h>
> > +
> > +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
> > +# error "Multiarch build should never default include!"
> > #endif
> >
> > -#include "../rawmemchr.S"
> > +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
> > + need this to build for ISA V2 builds. */
> > +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
> > +
> > +
> > +# include <sysdep.h>
> > +
> > +# ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_sse2
> > +# endif
> > +
> > + .text
> > +ENTRY (RAWMEMCHR)
> > + movd %rsi, %xmm1
> > + mov %rdi, %rcx
> > +
> > + punpcklbw %xmm1, %xmm1
> > + punpcklbw %xmm1, %xmm1
> > +
> > + and $63, %rcx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %rcx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches)
> > + add $16, %rdi
> > + and $-16, %rdi
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %rcx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > +/* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > +/* Check which byte is a match. */
> > + bsf %eax, %eax
> > +
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + add $16, %rdi
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + pcmpeqb %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + and $-64, %rdi
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + pcmpeqb %xmm1, %xmm0
> > + pcmpeqb %xmm1, %xmm2
> > + pcmpeqb %xmm1, %xmm3
> > + pcmpeqb %xmm1, %xmm4
> > +
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > +
> > + pcmpeqb 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > +END (RAWMEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > new file mode 100644
> > index 0000000000..a14b192bed
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../memchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > new file mode 100644
> > index 0000000000..5d4110a052
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../rawmemchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > index 58ed21db01..2a1cff5b05 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > index 282854f1a1..2bf93fd84b 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > index a346cd35a1..c67309e8a1 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __wmemchr_evex_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> > +
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > index 06cd0f9f5a..5512d5cdc3 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_evex
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > index 70a965d552..3081fb6821 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > @@ -1,4 +1,25 @@
> > -#define USE_AS_WMEMCHR 1
> > -#define wmemchr __wmemchr_sse2
> > +/* wmemchr optimized with SSE2
> > + Copyright (C) 2022 Free Software Foundation, Inc.
>
> This isn't a new file. Please leave out the copy right change.
>
> > + This file is part of the GNU C Library.
> >
> > -#include "../memchr.S"
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_sse2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> > +
> > +#include "memchr-sse2.S"
> > diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> > index 4c1a3383b9..e401a2ac53 100644
> > --- a/sysdeps/x86_64/rawmemchr.S
> > +++ b/sysdeps/x86_64/rawmemchr.S
> > @@ -17,185 +17,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define RAWMEMCHR rawmemchr
> >
> > - .text
> > -ENTRY (__rawmemchr)
> > - movd %rsi, %xmm1
> > - mov %rdi, %rcx
> > +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
> >
> > - punpcklbw %xmm1, %xmm1
> > - punpcklbw %xmm1, %xmm1
> > +#include "isa-default-impl.h"
> >
> > - and $63, %rcx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %rcx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches)
> > - add $16, %rdi
> > - and $-16, %rdi
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %rcx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > -/* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > -/* Check which byte is a match. */
> > - bsf %eax, %eax
> > -
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - add $16, %rdi
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - pcmpeqb %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - and $-64, %rdi
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - pcmpeqb %xmm1, %xmm0
> > - pcmpeqb %xmm1, %xmm2
> > - pcmpeqb %xmm1, %xmm3
> > - pcmpeqb %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > -
> > - pcmpeqb 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> .> - lea 32(%rax, %rdi), %rax/
> bu> - ret
> > -
> > -END (__rawmemchr)
> > -
> > -weak_alias (__rawmemchr, rawmemchr)
> > -libc_hidden_builtin_def (__rawmemchr)
> > +strong_alias (rawmemchr, __rawmemchr)
> > +libc_hidden_builtin_def (rawmemchr)
>
> Why these changes?
>
> > diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> > new file mode 100644
> > index 0000000000..dd0490f86b
> > --- /dev/null
> > +++ b/sysdeps/x86_64/wmemchr.S
> > @@ -0,0 +1,24 @@
> > +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#define WMEMCHR wmemchr
>
> #define WMEMCHR __wmemchr
>
> > +
> > +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> > +
> > +#include "isa-default-impl.h"
> > --
> > 2.34.1
> >
>
> This should provide the same symbol as wcsmbs/wmemchr.c.
> Have you tried --disable-multi-arch builds with different ISA levels?
It does. Both provide __wmemchr.
I have.
Test are:
with and without multiarch for all isa levels + m32
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
` (3 preceding siblings ...)
2022-06-22 18:11 ` [PATCH v9 " Noah Goldstein
@ 2022-06-22 20:58 ` Noah Goldstein
2022-06-22 20:58 ` [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 21:38 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 21:48 ` [PATCH v11 " Noah Goldstein
` (3 subsequent siblings)
8 siblings, 2 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 20:58 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++---
sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
5 files changed, 229 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..ba6826d518
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,70 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..67006e24e8
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,102 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+#define ISA_SHOULD_BUILD(isa_build_level) \
+ (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 20:58 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 20:58 ` Noah Goldstein
2022-06-22 21:51 ` H.J. Lu
2022-06-22 21:38 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 20:58 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86_64/isa-default-impl.h | 8 +
sysdeps/x86_64/memchr.S | 357 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
sysdeps/x86_64/rawmemchr.S | 184 +--------
sysdeps/x86_64/wmemchr.S | 28 ++
21 files changed, 740 insertions(+), 612 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
index 34634668e5..b374a38b8b 100644
--- a/sysdeps/x86_64/isa-default-impl.h
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -46,4 +46,12 @@
# error "Unsupported ISA Level!"
#endif
+#if IS_IN(rtld) && !defined USE_MULTIARCH
+# error "RTLD version should only exist in multiarch build"
+#endif
+
+#if defined USE_MULTIARCH && !IS_IN(rtld)
+# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
+#endif
+
#include ISA_DEFAULT_IMPL
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..20b43508c4 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR __memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
-strong_alias (memchr, __memchr)
+weak_alias (__memchr, memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..856c6261f8 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
-
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ const struct cpu_features *cpu_features = __get_cpu_features ();
+
+ /* NB: The X86_ISA_* feature check macros are evaluated at
+ compile time. */
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..39be5f7083 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (3)
# ifndef MEMCHR
# define MEMCHR __memchr_avx2
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..0dd4f1dcce 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (4)
# ifndef MEMCHR
# define MEMCHR __memchr_evex
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..8c561cd687 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,360 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
+#include <sysdep.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
-#endif
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
-#include "../memchr.S"
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..e2c2e20d85 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,192 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
-#endif
+#include <isa-level.h>
+#include <sysdep.h>
+
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
-#include "../rawmemchr.S"
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..b675a070d4 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,7 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
-#include "../memchr.S"
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..ba7e5202e6 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR __rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
-
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
+#include "isa-default-impl.h"
weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+libc_hidden_def (__rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..eef91e556b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,28 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR __wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
+
+libc_hidden_def (__wmemchr)
+weak_alias (__wmemchr, wmemchr)
+libc_hidden_weak (wmemchr)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 20:58 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 20:58 ` [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 21:38 ` H.J. Lu
2022-06-22 21:51 ` Noah Goldstein
1 sibling, 1 reply; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 21:38 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 1:58 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86/init-arch.h | 4 +-
> sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++---
> sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
> 5 files changed, 229 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a2886a2532 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,9 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..ba6826d518
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,70 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +#include <stdlib.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +
> +#ifndef X86_IFUNC_IMPL_ADD_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +#endif
> +
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> +
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..67006e24e8
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,102 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +
> +/*
> + * CPU Features that are hard coded as enabled depending on ISA build
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +#define ISA_SHOULD_BUILD(isa_build_level) \
> + (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
Please align || with (MINIMUM_X86_ISA_LEVEL.
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..34634668e5
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupported ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v11 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
` (4 preceding siblings ...)
2022-06-22 20:58 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 21:48 ` Noah Goldstein
2022-06-22 21:48 ` [PATCH v11 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 21:54 ` [PATCH v11 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 22:16 ` [PATCH v12 " Noah Goldstein
` (2 subsequent siblings)
8 siblings, 2 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 21:48 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++---
sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
5 files changed, 229 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..ba6826d518
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,70 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..7cae11c228
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,102 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+#define ISA_SHOULD_BUILD(isa_build_level) \
+ (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v11 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 21:48 ` [PATCH v11 " Noah Goldstein
@ 2022-06-22 21:48 ` Noah Goldstein
2022-06-22 21:54 ` [PATCH v11 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 21:48 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86_64/isa-default-impl.h | 8 +
sysdeps/x86_64/memchr.S | 357 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
sysdeps/x86_64/rawmemchr.S | 184 +--------
sysdeps/x86_64/wmemchr.S | 28 ++
21 files changed, 740 insertions(+), 612 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
index 34634668e5..b374a38b8b 100644
--- a/sysdeps/x86_64/isa-default-impl.h
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -46,4 +46,12 @@
# error "Unsupported ISA Level!"
#endif
+#if IS_IN(rtld) && !defined USE_MULTIARCH
+# error "RTLD version should only exist in multiarch build"
+#endif
+
+#if defined USE_MULTIARCH && !IS_IN(rtld)
+# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
+#endif
+
#include ISA_DEFAULT_IMPL
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..20b43508c4 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR __memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
-strong_alias (memchr, __memchr)
+weak_alias (__memchr, memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..856c6261f8 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
-
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ const struct cpu_features *cpu_features = __get_cpu_features ();
+
+ /* NB: The X86_ISA_* feature check macros are evaluated at
+ compile time. */
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..39be5f7083 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (3)
# ifndef MEMCHR
# define MEMCHR __memchr_avx2
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..0dd4f1dcce 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (4)
# ifndef MEMCHR
# define MEMCHR __memchr_evex
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..8c561cd687 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,360 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
+#include <sysdep.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
-#endif
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
-#include "../memchr.S"
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..e2c2e20d85 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,192 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
-#endif
+#include <isa-level.h>
+#include <sysdep.h>
+
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
-#include "../rawmemchr.S"
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..b675a070d4 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,7 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
-#include "../memchr.S"
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..ba7e5202e6 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR __rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
-
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
+#include "isa-default-impl.h"
weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+libc_hidden_def (__rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..eef91e556b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,28 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR __wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
+
+libc_hidden_def (__wmemchr)
+weak_alias (__wmemchr, wmemchr)
+libc_hidden_weak (wmemchr)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 21:38 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
@ 2022-06-22 21:51 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 21:51 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 2:39 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 1:58 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Factor out some of the ISA level defines in isa-level.c to
> > standalone header isa-level.h
> >
> > 2. Add new headers with ISA level dependent macros for handling
> > ifuncs.
> >
> > Note, this file does not change any code.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/x86/init-arch.h | 4 +-
> > sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
> > sysdeps/x86/isa-level.c | 17 ++---
> > sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
> > sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
> > 5 files changed, 229 insertions(+), 13 deletions(-)
> > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > create mode 100644 sysdeps/x86/isa-level.h
> > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> >
> > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > index 277c15f116..a2886a2532 100644
> > --- a/sysdeps/x86/init-arch.h
> > +++ b/sysdeps/x86/init-arch.h
> > @@ -19,7 +19,9 @@
> > #include <ifunc-init.h>
> > #include <isa.h>
> >
> > -#ifndef __x86_64__
> > +#ifdef __x86_64__
> > +# include <isa-ifunc-macros.h>
> > +#else
> > /* Due to the reordering and the other nifty extensions in i686, it is
> > not really good to use heavily i586 optimized code on an i686. It's
> > better to use i486 code if it isn't an i586. */
> > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > new file mode 100644
> > index 0000000000..ba6826d518
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > @@ -0,0 +1,70 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_IFUNC_MACROS_H
> > +#define _ISA_IFUNC_MACROS_H 1
> > +
> > +#include <isa-level.h>
> > +#include <sys/cdefs.h>
> > +#include <stdlib.h>
> > +
> > +/* Only include at the level of the minimum build ISA or higher. I.e
> > + if built with ISA=V1, then include all implementations. On the
> > + other hand if built with ISA=V3 only include V3/V4
> > + implementations. If there is no implementation at or above the
> > + minimum build ISA level, then include the highest ISA level
> > + implementation. */
> > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +#endif
> > +
> > +#ifndef X86_IFUNC_IMPL_ADD_V4
> > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > +#endif
> > +#ifndef X86_IFUNC_IMPL_ADD_V3
> > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > +#endif
> > +#ifndef X86_IFUNC_IMPL_ADD_V2
> > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > +#endif
> > +#ifndef X86_IFUNC_IMPL_ADD_V1
> > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > +#endif
> > +
> > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> > +
> > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURE_USABLE_P (ptr, name))
> > +
> > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURES_ARCH_P (ptr, name))
> > +
> > +#endif
> > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > index 09cd72ab20..5b7a2da870 100644
> > --- a/sysdeps/x86/isa-level.c
> > +++ b/sysdeps/x86/isa-level.c
> > @@ -26,38 +26,31 @@
> > <https://www.gnu.org/licenses/>. */
> >
> > #include <elf.h>
> > -
> > +#include <sysdeps/x86/isa-level.h>
> > /* ELF program property for x86 ISA level. */
> > #ifdef INCLUDE_X86_ISA_LEVEL
> > -# if defined __SSE__ && defined __SSE2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > # else
> > # define ISA_BASELINE 0
> > # endif
> >
> > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > - && defined __SSE4_2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > # else
> > # define ISA_V2 0
> > # endif
> >
> > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > - && defined __BMI__ && defined __BMI2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > # else
> > # define ISA_V3 0
> > # endif
> >
> > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > - && defined __AVX512VL__
> > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > # else
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > new file mode 100644
> > index 0000000000..67006e24e8
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -0,0 +1,102 @@
> > +/* Header defining the minimum x86 ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + In addition to the permissions in the GNU Lesser General Public
> > + License, the Free Software Foundation gives you unlimited
> > + permission to link the compiled version of this file with other
> > + programs, and to distribute those programs without any restriction
> > + coming from the use of this file. (The Lesser General Public
> > + License restrictions do apply in other respects; for example, they
> > + cover modification of the file, and distribution when not linked
> > + into another program.)
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_LEVEL_H
> > +#define _ISA_LEVEL_H
> > +
> > +#if defined __SSE__ && defined __SSE2__
> > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > +# define __X86_ISA_V1 1
> > +#else
> > +# define __X86_ISA_V1 0
> > +#endif
> > +
> > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > +# define __X86_ISA_V2 1
> > +#else
> > +# define __X86_ISA_V2 0
> > +#endif
> > +
> > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > + && defined __BMI__ && defined __BMI2__
> > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > +# define __X86_ISA_V3 1
> > +#else
> > +# define __X86_ISA_V3 0
> > +#endif
> > +
> > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > +# define __X86_ISA_V4 1
> > +#else
> > +# define __X86_ISA_V4 0
> > +#endif
> > +
> > +#define MINIMUM_X86_ISA_LEVEL \
> > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > +
> > +
> > +/*
> > + * CPU Features that are hard coded as enabled depending on ISA build
> > + * level.
> > + * - Values > 0 features are always ENABLED if:
> > + * Value >= MINIMUM_X86_ISA_LEVEL
> > + */
> > +
> > +
> > +/* ISA level >= 4 guaranteed includes. */
> > +#define AVX512VL_X86_ISA_LEVEL 4
> > +#define AVX512BW_X86_ISA_LEVEL 4
> > +
> > +/* ISA level >= 3 guaranteed includes. */
> > +#define AVX2_X86_ISA_LEVEL 3
> > +#define BMI2_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * NB: This may not be fully assumable for ISA level >= 3. From
> > + * looking over the architectures supported in cpu-features.h the
> > + * following CPUs may have an issue with this being default set:
> > + * - AMD Excavator
> > + */
> > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > + * builds with ISA V1 so this shouldn't harm any architectures.
> > + */
> > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > +
> > +#define ISA_SHOULD_BUILD(isa_build_level) \
> > + (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
> > + || defined ISA_DEFAULT_IMPL
>
> Please align || with (MINIMUM_X86_ISA_LEVEL.
Fixed in V11.
>
> > +
> > +#endif
> > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > new file mode 100644
> > index 0000000000..34634668e5
> > --- /dev/null
> > +++ b/sysdeps/x86_64/isa-default-impl.h
> > @@ -0,0 +1,49 @@
> > +/* Utility for including proper default function based on ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include <isa-level.h>
> > +
> > +#ifndef DEFAULT_IMPL_V1
> > +# error "Must have at least ISA V1 Version"
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V2
> > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V3
> > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V4
> > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL == 1
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > +#else
> > +# error "Unsupported ISA Level!"
> > +#endif
> > +
> > +#include ISA_DEFAULT_IMPL
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 20:58 ` [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 21:51 ` H.J. Lu
2022-06-22 22:04 ` Noah Goldstein
2022-06-22 22:16 ` Noah Goldstein
0 siblings, 2 replies; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 21:51 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 1:58 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Refactor files so that all implementations for in the multiarch
> directory.
> - Essentially moved sse2 {raw|w}memchr.S implementation to
> multiarch/{raw|w}memchr-sse2.S
>
> - The non-multiarch {raw|w}memchr.S file now only includes one of
> the implementations in the multiarch directory based on the
> compiled ISA level (only used for non-multiarch builds.
> Otherwise we go through the ifunc selector).
>
> 2. Add ISA level build guards to different implementations.
> - I.e memchr-avx2.S which is ISA level 3 will only build if
> compiled ISA level <= 3. Otherwise there is no reason to include
> it as we will always use one of the ISA level 4
> implementations (memchr-evex{-rtm}.S).
>
> 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> non-multiarch {raw}memchr.S which will in turn select the best
> implementation based on the compiled ISA level.
>
> 4. Refactor the ifunc selector and ifunc implementation list to use
> the ISA level aware wrapper macros that allow functions below the
> compiled ISA level (with a guranteed replacement) to be skipped.
> - Guranteed replacement essentially means that for any ISA level
> build there must be a function that the baseline of the ISA
> supports. So for {raw|w}memchr.S since there is not ISA level 2
> function, the ISA level 2 build still includes the ISA level
> 1 (sse2) function. Once we reach the ISA level 3 build, however,
> {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
>
> And m32 with and without multiarch.
> ---
> sysdeps/x86_64/isa-default-impl.h | 8 +
> sysdeps/x86_64/memchr.S | 357 +----------------
> sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
> sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
> sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
> sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
> sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
> sysdeps/x86_64/rawmemchr.S | 184 +--------
> sysdeps/x86_64/wmemchr.S | 28 ++
> 21 files changed, 740 insertions(+), 612 deletions(-)
> create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> create mode 100644 sysdeps/x86_64/wmemchr.S
>
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> index 34634668e5..b374a38b8b 100644
> --- a/sysdeps/x86_64/isa-default-impl.h
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -46,4 +46,12 @@
> # error "Unsupported ISA Level!"
> #endif
>
> +#if IS_IN(rtld) && !defined USE_MULTIARCH
> +# error "RTLD version should only exist in multiarch build"
> +#endif
> +
> +#if defined USE_MULTIARCH && !IS_IN(rtld)
> +# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
> +#endif
Please do
#if IS_IN (rtld)
#else
#endif
> #include ISA_DEFAULT_IMPL
> diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> index a160fd9b00..20b43508c4 100644
> --- a/sysdeps/x86_64/memchr.S
> +++ b/sysdeps/x86_64/memchr.S
> @@ -15,358 +15,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define MEMCHR __memchr
>
> -#ifdef USE_AS_WMEMCHR
> -# define MEMCHR wmemchr
> -# define PCMPEQ pcmpeqd
> -# define CHAR_PER_VEC 4
> -#else
> -# define MEMCHR memchr
> -# define PCMPEQ pcmpeqb
> -# define CHAR_PER_VEC 16
> -#endif
> +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
>
> -/* fast SSE2 version with using pmaxub and 64 byte loop */
> +#include "isa-default-impl.h"
>
> - .text
> -ENTRY(MEMCHR)
> - movd %esi, %xmm1
> - mov %edi, %ecx
> -
> -#ifdef __ILP32__
> - /* Clear the upper 32 bits. */
> - movl %edx, %edx
> -#endif
> -#ifdef USE_AS_WMEMCHR
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> -#else
> - punpcklbw %xmm1, %xmm1
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> - punpcklbw %xmm1, %xmm1
> -#endif
> -
> - and $63, %ecx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %ecx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - and $15, %ecx
> - and $-16, %rdi
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %ecx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - PCMPEQ %xmm1, %xmm0
> - /* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - /* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> - /* Check which byte is a match. */
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> - possible addition overflow. */
> - neg %rcx
> - add $16, %rcx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - sub %rcx, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - PCMPEQ %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - mov %rdi, %rcx
> - and $-64, %rdi
> - and $63, %ecx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> -
> - .p2align 4
> -L(align64_loop):
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - PCMPEQ %xmm1, %xmm0
> - PCMPEQ %xmm1, %xmm2
> - PCMPEQ %xmm1, %xmm3
> - PCMPEQ %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(exit_loop):
> - add $(CHAR_PER_VEC * 2), %edx
> - jle L(exit_loop_32)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32_1)
> - sub $CHAR_PER_VEC, %edx
> - jle L(return_null)
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches48_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(exit_loop_32):
> - add $(CHAR_PER_VEC * 2), %edx
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %edx
> - jbe L(return_null)
> -
> - PCMPEQ 16(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches16_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 16(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches32_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 32(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches48_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(return_null):
> - xor %eax, %eax
> - ret
> -END(MEMCHR)
> -
> -#ifndef USE_AS_WMEMCHR
> -strong_alias (memchr, __memchr)
> +weak_alias (__memchr, memchr)
> libc_hidden_builtin_def(memchr)
> -#endif
> diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> index b8f7a12ea2..856c6261f8 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> @@ -19,24 +19,28 @@
>
> #include <init-arch.h>
>
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
>
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> +
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
>
> static inline void *
> IFUNC_SELECTOR (void)
> {
> - const struct cpu_features* cpu_features = __get_cpu_features ();
> -
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> + const struct cpu_features *cpu_features = __get_cpu_features ();
> +
> + /* NB: The X86_ISA_* feature check macros are evaluated at
> + compile time. */
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + AVX_Fast_Unaligned_Load))
> {
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (evex_rtm);
> @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (avx2_rtm);
>
> - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + Prefer_No_VZEROUPPER))
> return OPTIMIZE (avx2);
> }
>
> + /* This is unreachable (compile time checked) if ISA level >= 3
> + so no need for a robust fallback here. */
> return OPTIMIZE (sse2);
> }
> diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> index 883362f63d..bf52cf96d0 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> @@ -25,7 +25,8 @@
>
> /* Fill ARRAY of MAX elements with IFUNC implementations for function
> NAME supported on target machine and return the number of valid
> - entries. */
> + entries. Each set of implementations for a given function is sorted in
> + descending order by ISA level. */
>
> size_t
> __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/memchr.c. */
> IFUNC_IMPL (i, name, memchr,
> - IFUNC_IMPL_ADD (array, i, memchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __memchr_avx2)
> - IFUNC_IMPL_ADD (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __memchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __memchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __memchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> + 1,
> + __memchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> IFUNC_IMPL (i, name, memcmp,
> @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> IFUNC_IMPL (i, name, rawmemchr,
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __rawmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __rawmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __rawmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __rawmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> + 1,
> + __rawmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/strlen.c. */
> IFUNC_IMPL (i, name, strlen,
> @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> IFUNC_IMPL (i, name, wmemchr,
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __wmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __wmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __wmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __wmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> + 1,
> + __wmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> IFUNC_IMPL (i, name, wmemcmp,
> diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> index c5a256eb37..39be5f7083 100644
> --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> @@ -16,9 +16,10 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +#include <sysdep.h>
>
> -# include <sysdep.h>
> +#if ISA_SHOULD_BUILD (3)
>
> # ifndef MEMCHR
> # define MEMCHR __memchr_avx2
> diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> index 0fd11b7632..0dd4f1dcce 100644
> --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> @@ -16,9 +16,10 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +#include <sysdep.h>
>
> -# include <sysdep.h>
> +#if ISA_SHOULD_BUILD (4)
>
> # ifndef MEMCHR
> # define MEMCHR __memchr_evex
> diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> index 2c6fdd41d6..8c561cd687 100644
> --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> @@ -16,13 +16,360 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> -# define memchr __memchr_sse2
> +#include <isa-level.h>
> +#include <sysdep.h>
>
> -# undef strong_alias
> -# define strong_alias(memchr, __memchr)
> -# undef libc_hidden_builtin_def
> -# define libc_hidden_builtin_def(memchr)
> -#endif
> +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> + so we need this to build for ISA V2 builds. */
> +#if ISA_SHOULD_BUILD (2)
> +
> +# ifndef MEMCHR
> +# define MEMCHR __memchr_sse2
> +# endif
> +# ifdef USE_AS_WMEMCHR
> +# define PCMPEQ pcmpeqd
> +# define CHAR_PER_VEC 4
> +# else
> +# define PCMPEQ pcmpeqb
> +# define CHAR_PER_VEC 16
> +# endif
> +
> +/* fast SSE2 version with using pmaxub and 64 byte loop */
> +
> + .text
> +ENTRY(MEMCHR)
> + movd %esi, %xmm1
> + mov %edi, %ecx
> +
> +# ifdef __ILP32__
> + /* Clear the upper 32 bits. */
> + movl %edx, %edx
> +# endif
> +# ifdef USE_AS_WMEMCHR
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> +# else
> + punpcklbw %xmm1, %xmm1
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> + punpcklbw %xmm1, %xmm1
> +# endif
> +
> + and $63, %ecx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %ecx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + and $15, %ecx
> + and $-16, %rdi
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %ecx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + PCMPEQ %xmm1, %xmm0
> + /* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + /* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> + /* Check which byte is a match. */
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> + possible addition overflow. */
> + neg %rcx
> + add $16, %rcx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + sub %rcx, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + PCMPEQ %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + mov %rdi, %rcx
> + and $-64, %rdi
> + and $63, %ecx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> +
> + .p2align 4
> +L(align64_loop):
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + PCMPEQ %xmm1, %xmm0
> + PCMPEQ %xmm1, %xmm2
> + PCMPEQ %xmm1, %xmm3
> + PCMPEQ %xmm1, %xmm4
>
> -#include "../memchr.S"
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(exit_loop):
> + add $(CHAR_PER_VEC * 2), %edx
> + jle L(exit_loop_32)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32_1)
> + sub $CHAR_PER_VEC, %edx
> + jle L(return_null)
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches48_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(exit_loop_32):
> + add $(CHAR_PER_VEC * 2), %edx
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %edx
> + jbe L(return_null)
> +
> + PCMPEQ 16(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches16_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 16(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches32_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 32(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches48_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(return_null):
> + xor %eax, %eax
> + ret
> +END(MEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> index acc5f6e2fb..5c1dcd3ca7 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2_rtm
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2_rtm
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2-rtm.S"
Will we ever use the RTM version as the default?
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> index 128f9ea637..d6bff28757 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> index deda1ca395..8ff7f27c9c 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> @@ -1,3 +1,7 @@
> -#define MEMCHR __rawmemchr_evex_rtm
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex_rtm
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
> +
Will we ever use the RTM version as the default?
> #include "memchr-evex-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> index ec942b77ba..dc1c450699 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_evex
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> index 3841c14c34..e2c2e20d85 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> @@ -16,14 +16,192 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -/* Define multiple versions only for the definition in libc. */
> -#if IS_IN (libc)
> -# define __rawmemchr __rawmemchr_sse2
> -
> -# undef weak_alias
> -# define weak_alias(__rawmemchr, rawmemchr)
> -# undef libc_hidden_def
> -# define libc_hidden_def(__rawmemchr)
> -#endif
> +#include <isa-level.h>
> +#include <sysdep.h>
> +
> +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> + so we need this to build for ISA V2 builds. */
> +#if ISA_SHOULD_BUILD (2)
> +
> +# ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_sse2
> +# endif
> +
> + .text
> +ENTRY (RAWMEMCHR)
> + movd %rsi, %xmm1
> + mov %rdi, %rcx
> +
> + punpcklbw %xmm1, %xmm1
> + punpcklbw %xmm1, %xmm1
> +
> + and $63, %rcx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %rcx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches)
> + add $16, %rdi
> + and $-16, %rdi
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %rcx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> +/* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> +/* Check which byte is a match. */
> + bsf %eax, %eax
> +
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + add $16, %rdi
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + pcmpeqb %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
>
> -#include "../rawmemchr.S"
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + and $-64, %rdi
> +
> + .p2align 4
> +L(align64_loop):
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + pcmpeqb %xmm1, %xmm0
> + pcmpeqb %xmm1, %xmm2
> + pcmpeqb %xmm1, %xmm3
> + pcmpeqb %xmm1, %xmm4
> +
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> +
> + pcmpeqb 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> +END (RAWMEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> new file mode 100644
> index 0000000000..a14b192bed
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../memchr.S"
> diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> new file mode 100644
> index 0000000000..5d4110a052
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../rawmemchr.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> index 58ed21db01..2a1cff5b05 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2_rtm
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2_rtm
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> index 282854f1a1..2bf93fd84b 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> index a346cd35a1..c67309e8a1 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> @@ -1,3 +1,7 @@
> -#define MEMCHR __wmemchr_evex_rtm
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex_rtm
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
> +
> #include "memchr-evex-rtm.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> index 06cd0f9f5a..5512d5cdc3 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_evex
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> index 70a965d552..b675a070d4 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> @@ -1,4 +1,7 @@
> -#define USE_AS_WMEMCHR 1
> -#define wmemchr __wmemchr_sse2
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_sse2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> -#include "../memchr.S"
> +#include "memchr-sse2.S"
> diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> index 4c1a3383b9..ba7e5202e6 100644
> --- a/sysdeps/x86_64/rawmemchr.S
> +++ b/sysdeps/x86_64/rawmemchr.S
> @@ -17,185 +17,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define RAWMEMCHR __rawmemchr
>
> - .text
> -ENTRY (__rawmemchr)
> - movd %rsi, %xmm1
> - mov %rdi, %rcx
> +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
>
> - punpcklbw %xmm1, %xmm1
> - punpcklbw %xmm1, %xmm1
> -
> - and $63, %rcx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %rcx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches)
> - add $16, %rdi
> - and $-16, %rdi
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %rcx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> -/* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> -/* Check which byte is a match. */
> - bsf %eax, %eax
> -
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - add $16, %rdi
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - pcmpeqb %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - and $-64, %rdi
> -
> - .p2align 4
> -L(align64_loop):
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - pcmpeqb %xmm1, %xmm0
> - pcmpeqb %xmm1, %xmm2
> - pcmpeqb %xmm1, %xmm3
> - pcmpeqb %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> -
> - pcmpeqb 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> -END (__rawmemchr)
> +#include "isa-default-impl.h"
>
> weak_alias (__rawmemchr, rawmemchr)
> -libc_hidden_builtin_def (__rawmemchr)
> +libc_hidden_def (__rawmemchr)
> diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> new file mode 100644
> index 0000000000..eef91e556b
> --- /dev/null
> +++ b/sysdeps/x86_64/wmemchr.S
> @@ -0,0 +1,28 @@
> +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#define WMEMCHR __wmemchr
> +
> +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> +
> +#include "isa-default-impl.h"
> +
> +libc_hidden_def (__wmemchr)
> +weak_alias (__wmemchr, wmemchr)
> +libc_hidden_weak (wmemchr)
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v11 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 21:48 ` [PATCH v11 " Noah Goldstein
2022-06-22 21:48 ` [PATCH v11 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 21:54 ` H.J. Lu
1 sibling, 0 replies; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 21:54 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 2:48 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
>
> And m32 with and without multiarch.
> ---
> sysdeps/x86/init-arch.h | 4 +-
> sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++---
> sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
> 5 files changed, 229 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a2886a2532 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,9 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..ba6826d518
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,70 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +#include <stdlib.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +
> +#ifndef X86_IFUNC_IMPL_ADD_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +#endif
> +
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> +
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..7cae11c228
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,102 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +
> +/*
> + * CPU Features that are hard coded as enabled depending on ISA build
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +#define ISA_SHOULD_BUILD(isa_build_level) \
> + (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..34634668e5
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupported ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
LGTM.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 21:51 ` H.J. Lu
@ 2022-06-22 22:04 ` Noah Goldstein
2022-06-22 22:14 ` H.J. Lu
2022-06-22 22:16 ` Noah Goldstein
1 sibling, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 22:04 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 2:52 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 1:58 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Refactor files so that all implementations for in the multiarch
> > directory.
> > - Essentially moved sse2 {raw|w}memchr.S implementation to
> > multiarch/{raw|w}memchr-sse2.S
> >
> > - The non-multiarch {raw|w}memchr.S file now only includes one of
> > the implementations in the multiarch directory based on the
> > compiled ISA level (only used for non-multiarch builds.
> > Otherwise we go through the ifunc selector).
> >
> > 2. Add ISA level build guards to different implementations.
> > - I.e memchr-avx2.S which is ISA level 3 will only build if
> > compiled ISA level <= 3. Otherwise there is no reason to include
> > it as we will always use one of the ISA level 4
> > implementations (memchr-evex{-rtm}.S).
> >
> > 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> > non-multiarch {raw}memchr.S which will in turn select the best
> > implementation based on the compiled ISA level.
> >
> > 4. Refactor the ifunc selector and ifunc implementation list to use
> > the ISA level aware wrapper macros that allow functions below the
> > compiled ISA level (with a guranteed replacement) to be skipped.
> > - Guranteed replacement essentially means that for any ISA level
> > build there must be a function that the baseline of the ISA
> > supports. So for {raw|w}memchr.S since there is not ISA level 2
> > function, the ISA level 2 build still includes the ISA level
> > 1 (sse2) function. Once we reach the ISA level 3 build, however,
> > {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> > level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> >
> > And m32 with and without multiarch.
> > ---
> > sysdeps/x86_64/isa-default-impl.h | 8 +
> > sysdeps/x86_64/memchr.S | 357 +----------------
> > sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> > sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
> > sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
> > sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
> > sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> > sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> > sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
> > sysdeps/x86_64/rawmemchr.S | 184 +--------
> > sysdeps/x86_64/wmemchr.S | 28 ++
> > 21 files changed, 740 insertions(+), 612 deletions(-)
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > create mode 100644 sysdeps/x86_64/wmemchr.S
> >
> > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > index 34634668e5..b374a38b8b 100644
> > --- a/sysdeps/x86_64/isa-default-impl.h
> > +++ b/sysdeps/x86_64/isa-default-impl.h
> > @@ -46,4 +46,12 @@
> > # error "Unsupported ISA Level!"
> > #endif
> >
> > +#if IS_IN(rtld) && !defined USE_MULTIARCH
> > +# error "RTLD version should only exist in multiarch build"
> > +#endif
> > +
> > +#if defined USE_MULTIARCH && !IS_IN(rtld)
> > +# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
> > +#endif
>
> Please do
>
> #if IS_IN (rtld)
> #else
> #endif
>
> > #include ISA_DEFAULT_IMPL
> > diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> > index a160fd9b00..20b43508c4 100644
> > --- a/sysdeps/x86_64/memchr.S
> > +++ b/sysdeps/x86_64/memchr.S
> > @@ -15,358 +15,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define MEMCHR __memchr
> >
> > -#ifdef USE_AS_WMEMCHR
> > -# define MEMCHR wmemchr
> > -# define PCMPEQ pcmpeqd
> > -# define CHAR_PER_VEC 4
> > -#else
> > -# define MEMCHR memchr
> > -# define PCMPEQ pcmpeqb
> > -# define CHAR_PER_VEC 16
> > -#endif
> > +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
> >
> > -/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +#include "isa-default-impl.h"
> >
> > - .text
> > -ENTRY(MEMCHR)
> > - movd %esi, %xmm1
> > - mov %edi, %ecx
> > -
> > -#ifdef __ILP32__
> > - /* Clear the upper 32 bits. */
> > - movl %edx, %edx
> > -#endif
> > -#ifdef USE_AS_WMEMCHR
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > -#else
> > - punpcklbw %xmm1, %xmm1
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > - punpcklbw %xmm1, %xmm1
> > -#endif
> > -
> > - and $63, %ecx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %ecx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - and $15, %ecx
> > - and $-16, %rdi
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %ecx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - /* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - /* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > - /* Check which byte is a match. */
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > - possible addition overflow. */
> > - neg %rcx
> > - add $16, %rcx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - sub %rcx, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - PCMPEQ %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - mov %rdi, %rcx
> > - and $-64, %rdi
> > - and $63, %ecx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - PCMPEQ %xmm1, %xmm2
> > - PCMPEQ %xmm1, %xmm3
> > - PCMPEQ %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - jle L(exit_loop_32)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jle L(return_null)
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches48_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop_32):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jbe L(return_null)
> > -
> > - PCMPEQ 16(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches16_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 16(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 32(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches48_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(return_null):
> > - xor %eax, %eax
> > - ret
> > -END(MEMCHR)
> > -
> > -#ifndef USE_AS_WMEMCHR
> > -strong_alias (memchr, __memchr)
> > +weak_alias (__memchr, memchr)
> > libc_hidden_builtin_def(memchr)
> > -#endif
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > index b8f7a12ea2..856c6261f8 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> > +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > @@ -19,24 +19,28 @@
> >
> > #include <init-arch.h>
> >
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
> >
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > +
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> >
> > static inline void *
> > IFUNC_SELECTOR (void)
> > {
> > - const struct cpu_features* cpu_features = __get_cpu_features ();
> > -
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> > + const struct cpu_features *cpu_features = __get_cpu_features ();
> > +
> > + /* NB: The X86_ISA_* feature check macros are evaluated at
> > + compile time. */
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + AVX_Fast_Unaligned_Load))
> > {
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > {
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (evex_rtm);
> > @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (avx2_rtm);
> >
> > - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> > + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + Prefer_No_VZEROUPPER))
> > return OPTIMIZE (avx2);
> > }
> >
> > + /* This is unreachable (compile time checked) if ISA level >= 3
> > + so no need for a robust fallback here. */
> > return OPTIMIZE (sse2);
> > }
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > index 883362f63d..bf52cf96d0 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > @@ -25,7 +25,8 @@
> >
> > /* Fill ARRAY of MAX elements with IFUNC implementations for function
> > NAME supported on target machine and return the number of valid
> > - entries. */
> > + entries. Each set of implementations for a given function is sorted in
> > + descending order by ISA level. */
> >
> > size_t
> > __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/memchr.c. */
> > IFUNC_IMPL (i, name, memchr,
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __memchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __memchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __memchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __memchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> > + 1,
> > + __memchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> > IFUNC_IMPL (i, name, memcmp,
> > @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> > IFUNC_IMPL (i, name, rawmemchr,
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __rawmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __rawmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __rawmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __rawmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> > + 1,
> > + __rawmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/strlen.c. */
> > IFUNC_IMPL (i, name, strlen,
> > @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> > IFUNC_IMPL (i, name, wmemchr,
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __wmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __wmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __wmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __wmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> > + 1,
> > + __wmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> > IFUNC_IMPL (i, name, wmemcmp,
> > diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > index c5a256eb37..39be5f7083 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > @@ -16,9 +16,10 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> >
> > -# include <sysdep.h>
> > +#if ISA_SHOULD_BUILD (3)
> >
> > # ifndef MEMCHR
> > # define MEMCHR __memchr_avx2
> > diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> > index 0fd11b7632..0dd4f1dcce 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> > @@ -16,9 +16,10 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> >
> > -# include <sysdep.h>
> > +#if ISA_SHOULD_BUILD (4)
> >
> > # ifndef MEMCHR
> > # define MEMCHR __memchr_evex
> > diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > index 2c6fdd41d6..8c561cd687 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > @@ -16,13 +16,360 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > -# define memchr __memchr_sse2
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> >
> > -# undef strong_alias
> > -# define strong_alias(memchr, __memchr)
> > -# undef libc_hidden_builtin_def
> > -# define libc_hidden_builtin_def(memchr)
> > -#endif
> > +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> > + so we need this to build for ISA V2 builds. */
> > +#if ISA_SHOULD_BUILD (2)
> > +
> > +# ifndef MEMCHR
> > +# define MEMCHR __memchr_sse2
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > +# define PCMPEQ pcmpeqd
> > +# define CHAR_PER_VEC 4
> > +# else
> > +# define PCMPEQ pcmpeqb
> > +# define CHAR_PER_VEC 16
> > +# endif
> > +
> > +/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +
> > + .text
> > +ENTRY(MEMCHR)
> > + movd %esi, %xmm1
> > + mov %edi, %ecx
> > +
> > +# ifdef __ILP32__
> > + /* Clear the upper 32 bits. */
> > + movl %edx, %edx
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > +# else
> > + punpcklbw %xmm1, %xmm1
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > + punpcklbw %xmm1, %xmm1
> > +# endif
> > +
> > + and $63, %ecx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %ecx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + and $15, %ecx
> > + and $-16, %rdi
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %ecx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + /* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + /* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > + /* Check which byte is a match. */
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > + possible addition overflow. */
> > + neg %rcx
> > + add $16, %rcx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + sub %rcx, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + PCMPEQ %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + mov %rdi, %rcx
> > + and $-64, %rdi
> > + and $63, %ecx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + PCMPEQ %xmm1, %xmm2
> > + PCMPEQ %xmm1, %xmm3
> > + PCMPEQ %xmm1, %xmm4
> >
> > -#include "../memchr.S"
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + jle L(exit_loop_32)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jle L(return_null)
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches48_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop_32):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jbe L(return_null)
> > +
> > + PCMPEQ 16(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches16_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 16(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 32(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches48_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(return_null):
> > + xor %eax, %eax
> > + ret
> > +END(MEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > index acc5f6e2fb..5c1dcd3ca7 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
>
> Will we ever use the RTM version as the default?
We had talked about it and agreed not to. I think we can
safely say we don't need it for the RTLD default because
we know no transactions.
As for the non-multiarch build selection it's a bit more ambiguous.
>
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > index 128f9ea637..d6bff28757 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > index deda1ca395..8ff7f27c9c 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> > +
>
> Will we ever use the RTM version as the default?
>
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > index ec942b77ba..dc1c450699 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > index 3841c14c34..e2c2e20d85 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > @@ -16,14 +16,192 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -/* Define multiple versions only for the definition in libc. */
> > -#if IS_IN (libc)
> > -# define __rawmemchr __rawmemchr_sse2
> > -
> > -# undef weak_alias
> > -# define weak_alias(__rawmemchr, rawmemchr)
> > -# undef libc_hidden_def
> > -# define libc_hidden_def(__rawmemchr)
> > -#endif
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> > +
> > +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> > + so we need this to build for ISA V2 builds. */
> > +#if ISA_SHOULD_BUILD (2)
> > +
> > +# ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_sse2
> > +# endif
> > +
> > + .text
> > +ENTRY (RAWMEMCHR)
> > + movd %rsi, %xmm1
> > + mov %rdi, %rcx
> > +
> > + punpcklbw %xmm1, %xmm1
> > + punpcklbw %xmm1, %xmm1
> > +
> > + and $63, %rcx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %rcx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches)
> > + add $16, %rdi
> > + and $-16, %rdi
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %rcx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > +/* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > +/* Check which byte is a match. */
> > + bsf %eax, %eax
> > +
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + add $16, %rdi
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + pcmpeqb %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> >
> > -#include "../rawmemchr.S"
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + and $-64, %rdi
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + pcmpeqb %xmm1, %xmm0
> > + pcmpeqb %xmm1, %xmm2
> > + pcmpeqb %xmm1, %xmm3
> > + pcmpeqb %xmm1, %xmm4
> > +
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > +
> > + pcmpeqb 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > +END (RAWMEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > new file mode 100644
> > index 0000000000..a14b192bed
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../memchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > new file mode 100644
> > index 0000000000..5d4110a052
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../rawmemchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > index 58ed21db01..2a1cff5b05 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > index 282854f1a1..2bf93fd84b 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > index a346cd35a1..c67309e8a1 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __wmemchr_evex_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> > +
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > index 06cd0f9f5a..5512d5cdc3 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_evex
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > index 70a965d552..b675a070d4 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > @@ -1,4 +1,7 @@
> > -#define USE_AS_WMEMCHR 1
> > -#define wmemchr __wmemchr_sse2
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_sse2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > -#include "../memchr.S"
> > +#include "memchr-sse2.S"
> > diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> > index 4c1a3383b9..ba7e5202e6 100644
> > --- a/sysdeps/x86_64/rawmemchr.S
> > +++ b/sysdeps/x86_64/rawmemchr.S
> > @@ -17,185 +17,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define RAWMEMCHR __rawmemchr
> >
> > - .text
> > -ENTRY (__rawmemchr)
> > - movd %rsi, %xmm1
> > - mov %rdi, %rcx
> > +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
> >
> > - punpcklbw %xmm1, %xmm1
> > - punpcklbw %xmm1, %xmm1
> > -
> > - and $63, %rcx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %rcx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches)
> > - add $16, %rdi
> > - and $-16, %rdi
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %rcx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > -/* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > -/* Check which byte is a match. */
> > - bsf %eax, %eax
> > -
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - add $16, %rdi
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - pcmpeqb %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - and $-64, %rdi
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - pcmpeqb %xmm1, %xmm0
> > - pcmpeqb %xmm1, %xmm2
> > - pcmpeqb %xmm1, %xmm3
> > - pcmpeqb %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > -
> > - pcmpeqb 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > -END (__rawmemchr)
> > +#include "isa-default-impl.h"
> >
> > weak_alias (__rawmemchr, rawmemchr)
> > -libc_hidden_builtin_def (__rawmemchr)
> > +libc_hidden_def (__rawmemchr)
> > diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> > new file mode 100644
> > index 0000000000..eef91e556b
> > --- /dev/null
> > +++ b/sysdeps/x86_64/wmemchr.S
> > @@ -0,0 +1,28 @@
> > +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#define WMEMCHR __wmemchr
> > +
> > +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> > +
> > +#include "isa-default-impl.h"
> > +
> > +libc_hidden_def (__wmemchr)
> > +weak_alias (__wmemchr, wmemchr)
> > +libc_hidden_weak (wmemchr)
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 22:04 ` Noah Goldstein
@ 2022-06-22 22:14 ` H.J. Lu
0 siblings, 0 replies; 36+ messages in thread
From: H.J. Lu @ 2022-06-22 22:14 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 3:04 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 2:52 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Wed, Jun 22, 2022 at 1:58 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > 1. Refactor files so that all implementations for in the multiarch
> > > directory.
> > > - Essentially moved sse2 {raw|w}memchr.S implementation to
> > > multiarch/{raw|w}memchr-sse2.S
> > >
> > > - The non-multiarch {raw|w}memchr.S file now only includes one of
> > > the implementations in the multiarch directory based on the
> > > compiled ISA level (only used for non-multiarch builds.
> > > Otherwise we go through the ifunc selector).
> > >
> > > 2. Add ISA level build guards to different implementations.
> > > - I.e memchr-avx2.S which is ISA level 3 will only build if
> > > compiled ISA level <= 3. Otherwise there is no reason to include
> > > it as we will always use one of the ISA level 4
> > > implementations (memchr-evex{-rtm}.S).
> > >
> > > 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> > > non-multiarch {raw}memchr.S which will in turn select the best
> > > implementation based on the compiled ISA level.
> > >
> > > 4. Refactor the ifunc selector and ifunc implementation list to use
> > > the ISA level aware wrapper macros that allow functions below the
> > > compiled ISA level (with a guranteed replacement) to be skipped.
> > > - Guranteed replacement essentially means that for any ISA level
> > > build there must be a function that the baseline of the ISA
> > > supports. So for {raw|w}memchr.S since there is not ISA level 2
> > > function, the ISA level 2 build still includes the ISA level
> > > 1 (sse2) function. Once we reach the ISA level 3 build, however,
> > > {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> > > level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
> > >
> > > Tested with and without multiarch on x86_64 for ISA levels:
> > > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > >
> > > And m32 with and without multiarch.
> > > ---
> > > sysdeps/x86_64/isa-default-impl.h | 8 +
> > > sysdeps/x86_64/memchr.S | 357 +----------------
> > > sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> > > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> > > sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
> > > sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
> > > sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
> > > sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> > > sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> > > sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> > > sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> > > sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
> > > sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> > > sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> > > sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> > > sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> > > sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> > > sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> > > sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
> > > sysdeps/x86_64/rawmemchr.S | 184 +--------
> > > sysdeps/x86_64/wmemchr.S | 28 ++
> > > 21 files changed, 740 insertions(+), 612 deletions(-)
> > > create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> > > create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > > create mode 100644 sysdeps/x86_64/wmemchr.S
> > >
> > > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > > index 34634668e5..b374a38b8b 100644
> > > --- a/sysdeps/x86_64/isa-default-impl.h
> > > +++ b/sysdeps/x86_64/isa-default-impl.h
> > > @@ -46,4 +46,12 @@
> > > # error "Unsupported ISA Level!"
> > > #endif
> > >
> > > +#if IS_IN(rtld) && !defined USE_MULTIARCH
> > > +# error "RTLD version should only exist in multiarch build"
> > > +#endif
> > > +
> > > +#if defined USE_MULTIARCH && !IS_IN(rtld)
> > > +# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
> > > +#endif
> >
> > Please do
> >
> > #if IS_IN (rtld)
> > #else
> > #endif
> >
> > > #include ISA_DEFAULT_IMPL
> > > diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> > > index a160fd9b00..20b43508c4 100644
> > > --- a/sysdeps/x86_64/memchr.S
> > > +++ b/sysdeps/x86_64/memchr.S
> > > @@ -15,358 +15,13 @@
> > > License along with the GNU C Library; if not, see
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > -#include <sysdep.h>
> > > +#define MEMCHR __memchr
> > >
> > > -#ifdef USE_AS_WMEMCHR
> > > -# define MEMCHR wmemchr
> > > -# define PCMPEQ pcmpeqd
> > > -# define CHAR_PER_VEC 4
> > > -#else
> > > -# define MEMCHR memchr
> > > -# define PCMPEQ pcmpeqb
> > > -# define CHAR_PER_VEC 16
> > > -#endif
> > > +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> > > +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> > > +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
> > >
> > > -/* fast SSE2 version with using pmaxub and 64 byte loop */
> > > +#include "isa-default-impl.h"
> > >
> > > - .text
> > > -ENTRY(MEMCHR)
> > > - movd %esi, %xmm1
> > > - mov %edi, %ecx
> > > -
> > > -#ifdef __ILP32__
> > > - /* Clear the upper 32 bits. */
> > > - movl %edx, %edx
> > > -#endif
> > > -#ifdef USE_AS_WMEMCHR
> > > - test %RDX_LP, %RDX_LP
> > > - jz L(return_null)
> > > -#else
> > > - punpcklbw %xmm1, %xmm1
> > > - test %RDX_LP, %RDX_LP
> > > - jz L(return_null)
> > > - punpcklbw %xmm1, %xmm1
> > > -#endif
> > > -
> > > - and $63, %ecx
> > > - pshufd $0, %xmm1, %xmm1
> > > -
> > > - cmp $48, %ecx
> > > - ja L(crosscache)
> > > -
> > > - movdqu (%rdi), %xmm0
> > > - PCMPEQ %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > -
> > > - jnz L(matches_1)
> > > - sub $CHAR_PER_VEC, %rdx
> > > - jbe L(return_null)
> > > - add $16, %rdi
> > > - and $15, %ecx
> > > - and $-16, %rdi
> > > -#ifdef USE_AS_WMEMCHR
> > > - shr $2, %ecx
> > > -#endif
> > > - add %rcx, %rdx
> > > - sub $(CHAR_PER_VEC * 4), %rdx
> > > - jbe L(exit_loop)
> > > - jmp L(loop_prolog)
> > > -
> > > - .p2align 4
> > > -L(crosscache):
> > > - and $15, %ecx
> > > - and $-16, %rdi
> > > - movdqa (%rdi), %xmm0
> > > -
> > > - PCMPEQ %xmm1, %xmm0
> > > - /* Check if there is a match. */
> > > - pmovmskb %xmm0, %eax
> > > - /* Remove the leading bytes. */
> > > - sar %cl, %eax
> > > - test %eax, %eax
> > > - je L(unaligned_no_match)
> > > - /* Check which byte is a match. */
> > > - bsf %eax, %eax
> > > -#ifdef USE_AS_WMEMCHR
> > > - mov %eax, %esi
> > > - shr $2, %esi
> > > - sub %rsi, %rdx
> > > -#else
> > > - sub %rax, %rdx
> > > -#endif
> > > - jbe L(return_null)
> > > - add %rdi, %rax
> > > - add %rcx, %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(unaligned_no_match):
> > > - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > > - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > > - possible addition overflow. */
> > > - neg %rcx
> > > - add $16, %rcx
> > > -#ifdef USE_AS_WMEMCHR
> > > - shr $2, %ecx
> > > -#endif
> > > - sub %rcx, %rdx
> > > - jbe L(return_null)
> > > - add $16, %rdi
> > > - sub $(CHAR_PER_VEC * 4), %rdx
> > > - jbe L(exit_loop)
> > > -
> > > - .p2align 4
> > > -L(loop_prolog):
> > > - movdqa (%rdi), %xmm0
> > > - PCMPEQ %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - movdqa 16(%rdi), %xmm2
> > > - PCMPEQ %xmm1, %xmm2
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - PCMPEQ %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32)
> > > -
> > > - movdqa 48(%rdi), %xmm4
> > > - PCMPEQ %xmm1, %xmm4
> > > - add $64, %rdi
> > > - pmovmskb %xmm4, %eax
> > > - test %eax, %eax
> > > - jnz L(matches0)
> > > -
> > > - test $0x3f, %rdi
> > > - jz L(align64_loop)
> > > -
> > > - sub $(CHAR_PER_VEC * 4), %rdx
> > > - jbe L(exit_loop)
> > > -
> > > - movdqa (%rdi), %xmm0
> > > - PCMPEQ %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - movdqa 16(%rdi), %xmm2
> > > - PCMPEQ %xmm1, %xmm2
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - PCMPEQ %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32)
> > > -
> > > - movdqa 48(%rdi), %xmm3
> > > - PCMPEQ %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > -
> > > - add $64, %rdi
> > > - test %eax, %eax
> > > - jnz L(matches0)
> > > -
> > > - mov %rdi, %rcx
> > > - and $-64, %rdi
> > > - and $63, %ecx
> > > -#ifdef USE_AS_WMEMCHR
> > > - shr $2, %ecx
> > > -#endif
> > > - add %rcx, %rdx
> > > -
> > > - .p2align 4
> > > -L(align64_loop):
> > > - sub $(CHAR_PER_VEC * 4), %rdx
> > > - jbe L(exit_loop)
> > > - movdqa (%rdi), %xmm0
> > > - movdqa 16(%rdi), %xmm2
> > > - movdqa 32(%rdi), %xmm3
> > > - movdqa 48(%rdi), %xmm4
> > > -
> > > - PCMPEQ %xmm1, %xmm0
> > > - PCMPEQ %xmm1, %xmm2
> > > - PCMPEQ %xmm1, %xmm3
> > > - PCMPEQ %xmm1, %xmm4
> > > -
> > > - pmaxub %xmm0, %xmm3
> > > - pmaxub %xmm2, %xmm4
> > > - pmaxub %xmm3, %xmm4
> > > - pmovmskb %xmm4, %eax
> > > -
> > > - add $64, %rdi
> > > -
> > > - test %eax, %eax
> > > - jz L(align64_loop)
> > > -
> > > - sub $64, %rdi
> > > -
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - PCMPEQ %xmm1, %xmm3
> > > -
> > > - PCMPEQ 48(%rdi), %xmm1
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32)
> > > -
> > > - pmovmskb %xmm1, %eax
> > > - bsf %eax, %eax
> > > - lea 48(%rdi, %rax), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(exit_loop):
> > > - add $(CHAR_PER_VEC * 2), %edx
> > > - jle L(exit_loop_32)
> > > -
> > > - movdqa (%rdi), %xmm0
> > > - PCMPEQ %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - movdqa 16(%rdi), %xmm2
> > > - PCMPEQ %xmm1, %xmm2
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - PCMPEQ %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32_1)
> > > - sub $CHAR_PER_VEC, %edx
> > > - jle L(return_null)
> > > -
> > > - PCMPEQ 48(%rdi), %xmm1
> > > - pmovmskb %xmm1, %eax
> > > - test %eax, %eax
> > > - jnz L(matches48_1)
> > > - xor %eax, %eax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(exit_loop_32):
> > > - add $(CHAR_PER_VEC * 2), %edx
> > > - movdqa (%rdi), %xmm0
> > > - PCMPEQ %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches_1)
> > > - sub $CHAR_PER_VEC, %edx
> > > - jbe L(return_null)
> > > -
> > > - PCMPEQ 16(%rdi), %xmm1
> > > - pmovmskb %xmm1, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16_1)
> > > - xor %eax, %eax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches0):
> > > - bsf %eax, %eax
> > > - lea -16(%rax, %rdi), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches):
> > > - bsf %eax, %eax
> > > - add %rdi, %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches16):
> > > - bsf %eax, %eax
> > > - lea 16(%rax, %rdi), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches32):
> > > - bsf %eax, %eax
> > > - lea 32(%rax, %rdi), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches_1):
> > > - bsf %eax, %eax
> > > -#ifdef USE_AS_WMEMCHR
> > > - mov %eax, %esi
> > > - shr $2, %esi
> > > - sub %rsi, %rdx
> > > -#else
> > > - sub %rax, %rdx
> > > -#endif
> > > - jbe L(return_null)
> > > - add %rdi, %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches16_1):
> > > - bsf %eax, %eax
> > > -#ifdef USE_AS_WMEMCHR
> > > - mov %eax, %esi
> > > - shr $2, %esi
> > > - sub %rsi, %rdx
> > > -#else
> > > - sub %rax, %rdx
> > > -#endif
> > > - jbe L(return_null)
> > > - lea 16(%rdi, %rax), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches32_1):
> > > - bsf %eax, %eax
> > > -#ifdef USE_AS_WMEMCHR
> > > - mov %eax, %esi
> > > - shr $2, %esi
> > > - sub %rsi, %rdx
> > > -#else
> > > - sub %rax, %rdx
> > > -#endif
> > > - jbe L(return_null)
> > > - lea 32(%rdi, %rax), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches48_1):
> > > - bsf %eax, %eax
> > > -#ifdef USE_AS_WMEMCHR
> > > - mov %eax, %esi
> > > - shr $2, %esi
> > > - sub %rsi, %rdx
> > > -#else
> > > - sub %rax, %rdx
> > > -#endif
> > > - jbe L(return_null)
> > > - lea 48(%rdi, %rax), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(return_null):
> > > - xor %eax, %eax
> > > - ret
> > > -END(MEMCHR)
> > > -
> > > -#ifndef USE_AS_WMEMCHR
> > > -strong_alias (memchr, __memchr)
> > > +weak_alias (__memchr, memchr)
> > > libc_hidden_builtin_def(memchr)
> > > -#endif
> > > diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > > index b8f7a12ea2..856c6261f8 100644
> > > --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> > > +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > > @@ -19,24 +19,28 @@
> > >
> > > #include <init-arch.h>
> > >
> > > -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> > > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> > > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
> > >
> > > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > > +
> > > +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> > >
> > > static inline void *
> > > IFUNC_SELECTOR (void)
> > > {
> > > - const struct cpu_features* cpu_features = __get_cpu_features ();
> > > -
> > > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > > - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > > - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> > > + const struct cpu_features *cpu_features = __get_cpu_features ();
> > > +
> > > + /* NB: The X86_ISA_* feature check macros are evaluated at
> > > + compile time. */
> > > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > > + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > > + AVX_Fast_Unaligned_Load))
> > > {
> > > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > > - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > > {
> > > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > > return OPTIMIZE (evex_rtm);
> > > @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> > > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > > return OPTIMIZE (avx2_rtm);
> > >
> > > - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> > > + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > > + Prefer_No_VZEROUPPER))
> > > return OPTIMIZE (avx2);
> > > }
> > >
> > > + /* This is unreachable (compile time checked) if ISA level >= 3
> > > + so no need for a robust fallback here. */
> > > return OPTIMIZE (sse2);
> > > }
> > > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > > index 883362f63d..bf52cf96d0 100644
> > > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > > @@ -25,7 +25,8 @@
> > >
> > > /* Fill ARRAY of MAX elements with IFUNC implementations for function
> > > NAME supported on target machine and return the number of valid
> > > - entries. */
> > > + entries. Each set of implementations for a given function is sorted in
> > > + descending order by ISA level. */
> > >
> > > size_t
> > > __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > > @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > >
> > > /* Support sysdeps/x86_64/multiarch/memchr.c. */
> > > IFUNC_IMPL (i, name, memchr,
> > > - IFUNC_IMPL_ADD (array, i, memchr,
> > > - CPU_FEATURE_USABLE (AVX2),
> > > - __memchr_avx2)
> > > - IFUNC_IMPL_ADD (array, i, memchr,
> > > - (CPU_FEATURE_USABLE (AVX2)
> > > - && CPU_FEATURE_USABLE (RTM)),
> > > - __memchr_avx2_rtm)
> > > - IFUNC_IMPL_ADD (array, i, memchr,
> > > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > > (CPU_FEATURE_USABLE (AVX512VL)
> > > && CPU_FEATURE_USABLE (AVX512BW)
> > > && CPU_FEATURE_USABLE (BMI2)),
> > > __memchr_evex)
> > > - IFUNC_IMPL_ADD (array, i, memchr,
> > > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > > (CPU_FEATURE_USABLE (AVX512VL)
> > > && CPU_FEATURE_USABLE (AVX512BW)
> > > && CPU_FEATURE_USABLE (BMI2)),
> > > __memchr_evex_rtm)
> > > - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> > > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > > + CPU_FEATURE_USABLE (AVX2),
> > > + __memchr_avx2)
> > > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > > + (CPU_FEATURE_USABLE (AVX2)
> > > + && CPU_FEATURE_USABLE (RTM)),
> > > + __memchr_avx2_rtm)
> > > + /* Can be lowered to V1 if a V2 implementation is added. */
> > > + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> > > + 1,
> > > + __memchr_sse2))
> > >
> > > /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> > > IFUNC_IMPL (i, name, memcmp,
> > > @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > >
> > > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> > > IFUNC_IMPL (i, name, rawmemchr,
> > > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > > - CPU_FEATURE_USABLE (AVX2),
> > > - __rawmemchr_avx2)
> > > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > > - (CPU_FEATURE_USABLE (AVX2)
> > > - && CPU_FEATURE_USABLE (RTM)),
> > > - __rawmemchr_avx2_rtm)
> > > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > > (CPU_FEATURE_USABLE (AVX512VL)
> > > && CPU_FEATURE_USABLE (AVX512BW)
> > > && CPU_FEATURE_USABLE (BMI2)),
> > > __rawmemchr_evex)
> > > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > > (CPU_FEATURE_USABLE (AVX512VL)
> > > && CPU_FEATURE_USABLE (AVX512BW)
> > > && CPU_FEATURE_USABLE (BMI2)),
> > > __rawmemchr_evex_rtm)
> > > - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> > > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > > + CPU_FEATURE_USABLE (AVX2),
> > > + __rawmemchr_avx2)
> > > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > > + (CPU_FEATURE_USABLE (AVX2)
> > > + && CPU_FEATURE_USABLE (RTM)),
> > > + __rawmemchr_avx2_rtm)
> > > + /* Can be lowered to V1 if a V2 implementation is added. */
> > > + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> > > + 1,
> > > + __rawmemchr_sse2))
> > >
> > > /* Support sysdeps/x86_64/multiarch/strlen.c. */
> > > IFUNC_IMPL (i, name, strlen,
> > > @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > >
> > > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> > > IFUNC_IMPL (i, name, wmemchr,
> > > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > > - CPU_FEATURE_USABLE (AVX2),
> > > - __wmemchr_avx2)
> > > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > > - (CPU_FEATURE_USABLE (AVX2)
> > > - && CPU_FEATURE_USABLE (RTM)),
> > > - __wmemchr_avx2_rtm)
> > > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > > (CPU_FEATURE_USABLE (AVX512VL)
> > > && CPU_FEATURE_USABLE (AVX512BW)
> > > && CPU_FEATURE_USABLE (BMI2)),
> > > __wmemchr_evex)
> > > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > > (CPU_FEATURE_USABLE (AVX512VL)
> > > && CPU_FEATURE_USABLE (AVX512BW)
> > > && CPU_FEATURE_USABLE (BMI2)),
> > > __wmemchr_evex_rtm)
> > > - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> > > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > > + CPU_FEATURE_USABLE (AVX2),
> > > + __wmemchr_avx2)
> > > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > > + (CPU_FEATURE_USABLE (AVX2)
> > > + && CPU_FEATURE_USABLE (RTM)),
> > > + __wmemchr_avx2_rtm)
> > > + /* Can be lowered to V1 if a V2 implementation is added. */
> > > + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> > > + 1,
> > > + __wmemchr_sse2))
> > >
> > > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> > > IFUNC_IMPL (i, name, wmemcmp,
> > > diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > > index c5a256eb37..39be5f7083 100644
> > > --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> > > +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > > @@ -16,9 +16,10 @@
> > > License along with the GNU C Library; if not, see
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > -#if IS_IN (libc)
> > > +#include <isa-level.h>
> > > +#include <sysdep.h>
> > >
> > > -# include <sysdep.h>
> > > +#if ISA_SHOULD_BUILD (3)
> > >
> > > # ifndef MEMCHR
> > > # define MEMCHR __memchr_avx2
> > > diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> > > index 0fd11b7632..0dd4f1dcce 100644
> > > --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> > > +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> > > @@ -16,9 +16,10 @@
> > > License along with the GNU C Library; if not, see
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > -#if IS_IN (libc)
> > > +#include <isa-level.h>
> > > +#include <sysdep.h>
> > >
> > > -# include <sysdep.h>
> > > +#if ISA_SHOULD_BUILD (4)
> > >
> > > # ifndef MEMCHR
> > > # define MEMCHR __memchr_evex
> > > diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > > index 2c6fdd41d6..8c561cd687 100644
> > > --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> > > +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > > @@ -16,13 +16,360 @@
> > > License along with the GNU C Library; if not, see
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > -#if IS_IN (libc)
> > > -# define memchr __memchr_sse2
> > > +#include <isa-level.h>
> > > +#include <sysdep.h>
> > >
> > > -# undef strong_alias
> > > -# define strong_alias(memchr, __memchr)
> > > -# undef libc_hidden_builtin_def
> > > -# define libc_hidden_builtin_def(memchr)
> > > -#endif
> > > +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> > > + so we need this to build for ISA V2 builds. */
> > > +#if ISA_SHOULD_BUILD (2)
> > > +
> > > +# ifndef MEMCHR
> > > +# define MEMCHR __memchr_sse2
> > > +# endif
> > > +# ifdef USE_AS_WMEMCHR
> > > +# define PCMPEQ pcmpeqd
> > > +# define CHAR_PER_VEC 4
> > > +# else
> > > +# define PCMPEQ pcmpeqb
> > > +# define CHAR_PER_VEC 16
> > > +# endif
> > > +
> > > +/* fast SSE2 version with using pmaxub and 64 byte loop */
> > > +
> > > + .text
> > > +ENTRY(MEMCHR)
> > > + movd %esi, %xmm1
> > > + mov %edi, %ecx
> > > +
> > > +# ifdef __ILP32__
> > > + /* Clear the upper 32 bits. */
> > > + movl %edx, %edx
> > > +# endif
> > > +# ifdef USE_AS_WMEMCHR
> > > + test %RDX_LP, %RDX_LP
> > > + jz L(return_null)
> > > +# else
> > > + punpcklbw %xmm1, %xmm1
> > > + test %RDX_LP, %RDX_LP
> > > + jz L(return_null)
> > > + punpcklbw %xmm1, %xmm1
> > > +# endif
> > > +
> > > + and $63, %ecx
> > > + pshufd $0, %xmm1, %xmm1
> > > +
> > > + cmp $48, %ecx
> > > + ja L(crosscache)
> > > +
> > > + movdqu (%rdi), %xmm0
> > > + PCMPEQ %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > +
> > > + jnz L(matches_1)
> > > + sub $CHAR_PER_VEC, %rdx
> > > + jbe L(return_null)
> > > + add $16, %rdi
> > > + and $15, %ecx
> > > + and $-16, %rdi
> > > +# ifdef USE_AS_WMEMCHR
> > > + shr $2, %ecx
> > > +# endif
> > > + add %rcx, %rdx
> > > + sub $(CHAR_PER_VEC * 4), %rdx
> > > + jbe L(exit_loop)
> > > + jmp L(loop_prolog)
> > > +
> > > + .p2align 4
> > > +L(crosscache):
> > > + and $15, %ecx
> > > + and $-16, %rdi
> > > + movdqa (%rdi), %xmm0
> > > +
> > > + PCMPEQ %xmm1, %xmm0
> > > + /* Check if there is a match. */
> > > + pmovmskb %xmm0, %eax
> > > + /* Remove the leading bytes. */
> > > + sar %cl, %eax
> > > + test %eax, %eax
> > > + je L(unaligned_no_match)
> > > + /* Check which byte is a match. */
> > > + bsf %eax, %eax
> > > +# ifdef USE_AS_WMEMCHR
> > > + mov %eax, %esi
> > > + shr $2, %esi
> > > + sub %rsi, %rdx
> > > +# else
> > > + sub %rax, %rdx
> > > +# endif
> > > + jbe L(return_null)
> > > + add %rdi, %rax
> > > + add %rcx, %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(unaligned_no_match):
> > > + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > > + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > > + possible addition overflow. */
> > > + neg %rcx
> > > + add $16, %rcx
> > > +# ifdef USE_AS_WMEMCHR
> > > + shr $2, %ecx
> > > +# endif
> > > + sub %rcx, %rdx
> > > + jbe L(return_null)
> > > + add $16, %rdi
> > > + sub $(CHAR_PER_VEC * 4), %rdx
> > > + jbe L(exit_loop)
> > > +
> > > + .p2align 4
> > > +L(loop_prolog):
> > > + movdqa (%rdi), %xmm0
> > > + PCMPEQ %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + movdqa 16(%rdi), %xmm2
> > > + PCMPEQ %xmm1, %xmm2
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > > +
> > > + movdqa 32(%rdi), %xmm3
> > > + PCMPEQ %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32)
> > > +
> > > + movdqa 48(%rdi), %xmm4
> > > + PCMPEQ %xmm1, %xmm4
> > > + add $64, %rdi
> > > + pmovmskb %xmm4, %eax
> > > + test %eax, %eax
> > > + jnz L(matches0)
> > > +
> > > + test $0x3f, %rdi
> > > + jz L(align64_loop)
> > > +
> > > + sub $(CHAR_PER_VEC * 4), %rdx
> > > + jbe L(exit_loop)
> > > +
> > > + movdqa (%rdi), %xmm0
> > > + PCMPEQ %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + movdqa 16(%rdi), %xmm2
> > > + PCMPEQ %xmm1, %xmm2
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > > +
> > > + movdqa 32(%rdi), %xmm3
> > > + PCMPEQ %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32)
> > > +
> > > + movdqa 48(%rdi), %xmm3
> > > + PCMPEQ %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > +
> > > + add $64, %rdi
> > > + test %eax, %eax
> > > + jnz L(matches0)
> > > +
> > > + mov %rdi, %rcx
> > > + and $-64, %rdi
> > > + and $63, %ecx
> > > +# ifdef USE_AS_WMEMCHR
> > > + shr $2, %ecx
> > > +# endif
> > > + add %rcx, %rdx
> > > +
> > > + .p2align 4
> > > +L(align64_loop):
> > > + sub $(CHAR_PER_VEC * 4), %rdx
> > > + jbe L(exit_loop)
> > > + movdqa (%rdi), %xmm0
> > > + movdqa 16(%rdi), %xmm2
> > > + movdqa 32(%rdi), %xmm3
> > > + movdqa 48(%rdi), %xmm4
> > > +
> > > + PCMPEQ %xmm1, %xmm0
> > > + PCMPEQ %xmm1, %xmm2
> > > + PCMPEQ %xmm1, %xmm3
> > > + PCMPEQ %xmm1, %xmm4
> > >
> > > -#include "../memchr.S"
> > > + pmaxub %xmm0, %xmm3
> > > + pmaxub %xmm2, %xmm4
> > > + pmaxub %xmm3, %xmm4
> > > + pmovmskb %xmm4, %eax
> > > +
> > > + add $64, %rdi
> > > +
> > > + test %eax, %eax
> > > + jz L(align64_loop)
> > > +
> > > + sub $64, %rdi
> > > +
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > > +
> > > + movdqa 32(%rdi), %xmm3
> > > + PCMPEQ %xmm1, %xmm3
> > > +
> > > + PCMPEQ 48(%rdi), %xmm1
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32)
> > > +
> > > + pmovmskb %xmm1, %eax
> > > + bsf %eax, %eax
> > > + lea 48(%rdi, %rax), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(exit_loop):
> > > + add $(CHAR_PER_VEC * 2), %edx
> > > + jle L(exit_loop_32)
> > > +
> > > + movdqa (%rdi), %xmm0
> > > + PCMPEQ %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + movdqa 16(%rdi), %xmm2
> > > + PCMPEQ %xmm1, %xmm2
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > > +
> > > + movdqa 32(%rdi), %xmm3
> > > + PCMPEQ %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32_1)
> > > + sub $CHAR_PER_VEC, %edx
> > > + jle L(return_null)
> > > +
> > > + PCMPEQ 48(%rdi), %xmm1
> > > + pmovmskb %xmm1, %eax
> > > + test %eax, %eax
> > > + jnz L(matches48_1)
> > > + xor %eax, %eax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(exit_loop_32):
> > > + add $(CHAR_PER_VEC * 2), %edx
> > > + movdqa (%rdi), %xmm0
> > > + PCMPEQ %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches_1)
> > > + sub $CHAR_PER_VEC, %edx
> > > + jbe L(return_null)
> > > +
> > > + PCMPEQ 16(%rdi), %xmm1
> > > + pmovmskb %xmm1, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16_1)
> > > + xor %eax, %eax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches0):
> > > + bsf %eax, %eax
> > > + lea -16(%rax, %rdi), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches):
> > > + bsf %eax, %eax
> > > + add %rdi, %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches16):
> > > + bsf %eax, %eax
> > > + lea 16(%rax, %rdi), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches32):
> > > + bsf %eax, %eax
> > > + lea 32(%rax, %rdi), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches_1):
> > > + bsf %eax, %eax
> > > +# ifdef USE_AS_WMEMCHR
> > > + mov %eax, %esi
> > > + shr $2, %esi
> > > + sub %rsi, %rdx
> > > +# else
> > > + sub %rax, %rdx
> > > +# endif
> > > + jbe L(return_null)
> > > + add %rdi, %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches16_1):
> > > + bsf %eax, %eax
> > > +# ifdef USE_AS_WMEMCHR
> > > + mov %eax, %esi
> > > + shr $2, %esi
> > > + sub %rsi, %rdx
> > > +# else
> > > + sub %rax, %rdx
> > > +# endif
> > > + jbe L(return_null)
> > > + lea 16(%rdi, %rax), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches32_1):
> > > + bsf %eax, %eax
> > > +# ifdef USE_AS_WMEMCHR
> > > + mov %eax, %esi
> > > + shr $2, %esi
> > > + sub %rsi, %rdx
> > > +# else
> > > + sub %rax, %rdx
> > > +# endif
> > > + jbe L(return_null)
> > > + lea 32(%rdi, %rax), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches48_1):
> > > + bsf %eax, %eax
> > > +# ifdef USE_AS_WMEMCHR
> > > + mov %eax, %esi
> > > + shr $2, %esi
> > > + sub %rsi, %rdx
> > > +# else
> > > + sub %rax, %rdx
> > > +# endif
> > > + jbe L(return_null)
> > > + lea 48(%rdi, %rax), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(return_null):
> > > + xor %eax, %eax
> > > + ret
> > > +END(MEMCHR)
> > > +#endif
> > > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > > index acc5f6e2fb..5c1dcd3ca7 100644
> > > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > > @@ -1,4 +1,7 @@
> > > -#define MEMCHR __rawmemchr_avx2_rtm
> > > -#define USE_AS_RAWMEMCHR 1
> > > +#ifndef RAWMEMCHR
> > > +# define RAWMEMCHR __rawmemchr_avx2_rtm
> > > +#endif
> > > +#define USE_AS_RAWMEMCHR 1
> > > +#define MEMCHR RAWMEMCHR
> > >
> > > #include "memchr-avx2-rtm.S"
> >
> > Will we ever use the RTM version as the default?
>
> We had talked about it and agreed not to. I think we can
> safely say we don't need it for the RTLD default because
> we know no transactions.
>
> As for the non-multiarch build selection it's a bit more ambiguous.
Since the RTM version isn't used for default, we should
leave the RTM .S files alone.
> >
> > > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > > index 128f9ea637..d6bff28757 100644
> > > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > > @@ -1,4 +1,7 @@
> > > -#define MEMCHR __rawmemchr_avx2
> > > -#define USE_AS_RAWMEMCHR 1
> > > +#ifndef RAWMEMCHR
> > > +# define RAWMEMCHR __rawmemchr_avx2
> > > +#endif
> > > +#define USE_AS_RAWMEMCHR 1
> > > +#define MEMCHR RAWMEMCHR
> > >
> > > #include "memchr-avx2.S"
> > > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > > index deda1ca395..8ff7f27c9c 100644
> > > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > > @@ -1,3 +1,7 @@
> > > -#define MEMCHR __rawmemchr_evex_rtm
> > > -#define USE_AS_RAWMEMCHR 1
> > > +#ifndef RAWMEMCHR
> > > +# define RAWMEMCHR __rawmemchr_evex_rtm
> > > +#endif
> > > +#define USE_AS_RAWMEMCHR 1
> > > +#define MEMCHR RAWMEMCHR
> > > +
> >
> > Will we ever use the RTM version as the default?
> >
> > > #include "memchr-evex-rtm.S"
> > > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > > index ec942b77ba..dc1c450699 100644
> > > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > > @@ -1,4 +1,7 @@
> > > -#define MEMCHR __rawmemchr_evex
> > > -#define USE_AS_RAWMEMCHR 1
> > > +#ifndef RAWMEMCHR
> > > +# define RAWMEMCHR __rawmemchr_evex
> > > +#endif
> > > +#define USE_AS_RAWMEMCHR 1
> > > +#define MEMCHR RAWMEMCHR
> > >
> > > #include "memchr-evex.S"
> > > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > > index 3841c14c34..e2c2e20d85 100644
> > > --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > > +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > > @@ -16,14 +16,192 @@
> > > License along with the GNU C Library; if not, see
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > -/* Define multiple versions only for the definition in libc. */
> > > -#if IS_IN (libc)
> > > -# define __rawmemchr __rawmemchr_sse2
> > > -
> > > -# undef weak_alias
> > > -# define weak_alias(__rawmemchr, rawmemchr)
> > > -# undef libc_hidden_def
> > > -# define libc_hidden_def(__rawmemchr)
> > > -#endif
> > > +#include <isa-level.h>
> > > +#include <sysdep.h>
> > > +
> > > +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> > > + so we need this to build for ISA V2 builds. */
> > > +#if ISA_SHOULD_BUILD (2)
> > > +
> > > +# ifndef RAWMEMCHR
> > > +# define RAWMEMCHR __rawmemchr_sse2
> > > +# endif
> > > +
> > > + .text
> > > +ENTRY (RAWMEMCHR)
> > > + movd %rsi, %xmm1
> > > + mov %rdi, %rcx
> > > +
> > > + punpcklbw %xmm1, %xmm1
> > > + punpcklbw %xmm1, %xmm1
> > > +
> > > + and $63, %rcx
> > > + pshufd $0, %xmm1, %xmm1
> > > +
> > > + cmp $48, %rcx
> > > + ja L(crosscache)
> > > +
> > > + movdqu (%rdi), %xmm0
> > > + pcmpeqb %xmm1, %xmm0
> > > +/* Check if there is a match. */
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > +
> > > + jnz L(matches)
> > > + add $16, %rdi
> > > + and $-16, %rdi
> > > + jmp L(loop_prolog)
> > > +
> > > + .p2align 4
> > > +L(crosscache):
> > > + and $15, %rcx
> > > + and $-16, %rdi
> > > + movdqa (%rdi), %xmm0
> > > +
> > > + pcmpeqb %xmm1, %xmm0
> > > +/* Check if there is a match. */
> > > + pmovmskb %xmm0, %eax
> > > +/* Remove the leading bytes. */
> > > + sar %cl, %eax
> > > + test %eax, %eax
> > > + je L(unaligned_no_match)
> > > +/* Check which byte is a match. */
> > > + bsf %eax, %eax
> > > +
> > > + add %rdi, %rax
> > > + add %rcx, %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(unaligned_no_match):
> > > + add $16, %rdi
> > > +
> > > + .p2align 4
> > > +L(loop_prolog):
> > > + movdqa (%rdi), %xmm0
> > > + pcmpeqb %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + movdqa 16(%rdi), %xmm2
> > > + pcmpeqb %xmm1, %xmm2
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > > +
> > > + movdqa 32(%rdi), %xmm3
> > > + pcmpeqb %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32)
> > > +
> > > + movdqa 48(%rdi), %xmm4
> > > + pcmpeqb %xmm1, %xmm4
> > > + add $64, %rdi
> > > + pmovmskb %xmm4, %eax
> > > + test %eax, %eax
> > > + jnz L(matches0)
> > > +
> > > + test $0x3f, %rdi
> > > + jz L(align64_loop)
> > > +
> > > + movdqa (%rdi), %xmm0
> > > + pcmpeqb %xmm1, %xmm0
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + movdqa 16(%rdi), %xmm2
> > > + pcmpeqb %xmm1, %xmm2
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > >
> > > -#include "../rawmemchr.S"
> > > + movdqa 32(%rdi), %xmm3
> > > + pcmpeqb %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32)
> > > +
> > > + movdqa 48(%rdi), %xmm3
> > > + pcmpeqb %xmm1, %xmm3
> > > + pmovmskb %xmm3, %eax
> > > +
> > > + add $64, %rdi
> > > + test %eax, %eax
> > > + jnz L(matches0)
> > > +
> > > + and $-64, %rdi
> > > +
> > > + .p2align 4
> > > +L(align64_loop):
> > > + movdqa (%rdi), %xmm0
> > > + movdqa 16(%rdi), %xmm2
> > > + movdqa 32(%rdi), %xmm3
> > > + movdqa 48(%rdi), %xmm4
> > > +
> > > + pcmpeqb %xmm1, %xmm0
> > > + pcmpeqb %xmm1, %xmm2
> > > + pcmpeqb %xmm1, %xmm3
> > > + pcmpeqb %xmm1, %xmm4
> > > +
> > > + pmaxub %xmm0, %xmm3
> > > + pmaxub %xmm2, %xmm4
> > > + pmaxub %xmm3, %xmm4
> > > + pmovmskb %xmm4, %eax
> > > +
> > > + add $64, %rdi
> > > +
> > > + test %eax, %eax
> > > + jz L(align64_loop)
> > > +
> > > + sub $64, %rdi
> > > +
> > > + pmovmskb %xmm0, %eax
> > > + test %eax, %eax
> > > + jnz L(matches)
> > > +
> > > + pmovmskb %xmm2, %eax
> > > + test %eax, %eax
> > > + jnz L(matches16)
> > > +
> > > + movdqa 32(%rdi), %xmm3
> > > + pcmpeqb %xmm1, %xmm3
> > > +
> > > + pcmpeqb 48(%rdi), %xmm1
> > > + pmovmskb %xmm3, %eax
> > > + test %eax, %eax
> > > + jnz L(matches32)
> > > +
> > > + pmovmskb %xmm1, %eax
> > > + bsf %eax, %eax
> > > + lea 48(%rdi, %rax), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches0):
> > > + bsf %eax, %eax
> > > + lea -16(%rax, %rdi), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches):
> > > + bsf %eax, %eax
> > > + add %rdi, %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches16):
> > > + bsf %eax, %eax
> > > + lea 16(%rax, %rdi), %rax
> > > + ret
> > > +
> > > + .p2align 4
> > > +L(matches32):
> > > + bsf %eax, %eax
> > > + lea 32(%rax, %rdi), %rax
> > > + ret
> > > +
> > > +END (RAWMEMCHR)
> > > +#endif
> > > diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > > new file mode 100644
> > > index 0000000000..a14b192bed
> > > --- /dev/null
> > > +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > > @@ -0,0 +1,18 @@
> > > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#include "../memchr.S"
> > > diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > > new file mode 100644
> > > index 0000000000..5d4110a052
> > > --- /dev/null
> > > +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > > @@ -0,0 +1,18 @@
> > > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#include "../rawmemchr.S"
> > > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > > index 58ed21db01..2a1cff5b05 100644
> > > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > > @@ -1,4 +1,7 @@
> > > -#define MEMCHR __wmemchr_avx2_rtm
> > > -#define USE_AS_WMEMCHR 1
> > > +#ifndef WMEMCHR
> > > +# define WMEMCHR __wmemchr_avx2_rtm
> > > +#endif
> > > +#define USE_AS_WMEMCHR 1
> > > +#define MEMCHR WMEMCHR
> > >
> > > #include "memchr-avx2-rtm.S"
> > > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > > index 282854f1a1..2bf93fd84b 100644
> > > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > > @@ -1,4 +1,7 @@
> > > -#define MEMCHR __wmemchr_avx2
> > > -#define USE_AS_WMEMCHR 1
> > > +#ifndef WMEMCHR
> > > +# define WMEMCHR __wmemchr_avx2
> > > +#endif
> > > +#define USE_AS_WMEMCHR 1
> > > +#define MEMCHR WMEMCHR
> > >
> > > #include "memchr-avx2.S"
> > > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > > index a346cd35a1..c67309e8a1 100644
> > > --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > > @@ -1,3 +1,7 @@
> > > -#define MEMCHR __wmemchr_evex_rtm
> > > -#define USE_AS_WMEMCHR 1
> > > +#ifndef WMEMCHR
> > > +# define WMEMCHR __wmemchr_evex_rtm
> > > +#endif
> > > +#define USE_AS_WMEMCHR 1
> > > +#define MEMCHR WMEMCHR
> > > +
> > > #include "memchr-evex-rtm.S"
> > > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > > index 06cd0f9f5a..5512d5cdc3 100644
> > > --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > > @@ -1,4 +1,7 @@
> > > -#define MEMCHR __wmemchr_evex
> > > -#define USE_AS_WMEMCHR 1
> > > +#ifndef WMEMCHR
> > > +# define WMEMCHR __wmemchr_evex
> > > +#endif
> > > +#define USE_AS_WMEMCHR 1
> > > +#define MEMCHR WMEMCHR
> > >
> > > #include "memchr-evex.S"
> > > diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > > index 70a965d552..b675a070d4 100644
> > > --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > > +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > > @@ -1,4 +1,7 @@
> > > -#define USE_AS_WMEMCHR 1
> > > -#define wmemchr __wmemchr_sse2
> > > +#ifndef WMEMCHR
> > > +# define WMEMCHR __wmemchr_sse2
> > > +#endif
> > > +#define USE_AS_WMEMCHR 1
> > > +#define MEMCHR WMEMCHR
> > >
> > > -#include "../memchr.S"
> > > +#include "memchr-sse2.S"
> > > diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> > > index 4c1a3383b9..ba7e5202e6 100644
> > > --- a/sysdeps/x86_64/rawmemchr.S
> > > +++ b/sysdeps/x86_64/rawmemchr.S
> > > @@ -17,185 +17,13 @@
> > > License along with the GNU C Library; if not, see
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > -#include <sysdep.h>
> > > +#define RAWMEMCHR __rawmemchr
> > >
> > > - .text
> > > -ENTRY (__rawmemchr)
> > > - movd %rsi, %xmm1
> > > - mov %rdi, %rcx
> > > +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> > > +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> > > +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
> > >
> > > - punpcklbw %xmm1, %xmm1
> > > - punpcklbw %xmm1, %xmm1
> > > -
> > > - and $63, %rcx
> > > - pshufd $0, %xmm1, %xmm1
> > > -
> > > - cmp $48, %rcx
> > > - ja L(crosscache)
> > > -
> > > - movdqu (%rdi), %xmm0
> > > - pcmpeqb %xmm1, %xmm0
> > > -/* Check if there is a match. */
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > -
> > > - jnz L(matches)
> > > - add $16, %rdi
> > > - and $-16, %rdi
> > > - jmp L(loop_prolog)
> > > -
> > > - .p2align 4
> > > -L(crosscache):
> > > - and $15, %rcx
> > > - and $-16, %rdi
> > > - movdqa (%rdi), %xmm0
> > > -
> > > - pcmpeqb %xmm1, %xmm0
> > > -/* Check if there is a match. */
> > > - pmovmskb %xmm0, %eax
> > > -/* Remove the leading bytes. */
> > > - sar %cl, %eax
> > > - test %eax, %eax
> > > - je L(unaligned_no_match)
> > > -/* Check which byte is a match. */
> > > - bsf %eax, %eax
> > > -
> > > - add %rdi, %rax
> > > - add %rcx, %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(unaligned_no_match):
> > > - add $16, %rdi
> > > -
> > > - .p2align 4
> > > -L(loop_prolog):
> > > - movdqa (%rdi), %xmm0
> > > - pcmpeqb %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - movdqa 16(%rdi), %xmm2
> > > - pcmpeqb %xmm1, %xmm2
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - pcmpeqb %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32)
> > > -
> > > - movdqa 48(%rdi), %xmm4
> > > - pcmpeqb %xmm1, %xmm4
> > > - add $64, %rdi
> > > - pmovmskb %xmm4, %eax
> > > - test %eax, %eax
> > > - jnz L(matches0)
> > > -
> > > - test $0x3f, %rdi
> > > - jz L(align64_loop)
> > > -
> > > - movdqa (%rdi), %xmm0
> > > - pcmpeqb %xmm1, %xmm0
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - movdqa 16(%rdi), %xmm2
> > > - pcmpeqb %xmm1, %xmm2
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - pcmpeqb %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32)
> > > -
> > > - movdqa 48(%rdi), %xmm3
> > > - pcmpeqb %xmm1, %xmm3
> > > - pmovmskb %xmm3, %eax
> > > -
> > > - add $64, %rdi
> > > - test %eax, %eax
> > > - jnz L(matches0)
> > > -
> > > - and $-64, %rdi
> > > -
> > > - .p2align 4
> > > -L(align64_loop):
> > > - movdqa (%rdi), %xmm0
> > > - movdqa 16(%rdi), %xmm2
> > > - movdqa 32(%rdi), %xmm3
> > > - movdqa 48(%rdi), %xmm4
> > > -
> > > - pcmpeqb %xmm1, %xmm0
> > > - pcmpeqb %xmm1, %xmm2
> > > - pcmpeqb %xmm1, %xmm3
> > > - pcmpeqb %xmm1, %xmm4
> > > -
> > > - pmaxub %xmm0, %xmm3
> > > - pmaxub %xmm2, %xmm4
> > > - pmaxub %xmm3, %xmm4
> > > - pmovmskb %xmm4, %eax
> > > -
> > > - add $64, %rdi
> > > -
> > > - test %eax, %eax
> > > - jz L(align64_loop)
> > > -
> > > - sub $64, %rdi
> > > -
> > > - pmovmskb %xmm0, %eax
> > > - test %eax, %eax
> > > - jnz L(matches)
> > > -
> > > - pmovmskb %xmm2, %eax
> > > - test %eax, %eax
> > > - jnz L(matches16)
> > > -
> > > - movdqa 32(%rdi), %xmm3
> > > - pcmpeqb %xmm1, %xmm3
> > > -
> > > - pcmpeqb 48(%rdi), %xmm1
> > > - pmovmskb %xmm3, %eax
> > > - test %eax, %eax
> > > - jnz L(matches32)
> > > -
> > > - pmovmskb %xmm1, %eax
> > > - bsf %eax, %eax
> > > - lea 48(%rdi, %rax), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches0):
> > > - bsf %eax, %eax
> > > - lea -16(%rax, %rdi), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches):
> > > - bsf %eax, %eax
> > > - add %rdi, %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches16):
> > > - bsf %eax, %eax
> > > - lea 16(%rax, %rdi), %rax
> > > - ret
> > > -
> > > - .p2align 4
> > > -L(matches32):
> > > - bsf %eax, %eax
> > > - lea 32(%rax, %rdi), %rax
> > > - ret
> > > -
> > > -END (__rawmemchr)
> > > +#include "isa-default-impl.h"
> > >
> > > weak_alias (__rawmemchr, rawmemchr)
> > > -libc_hidden_builtin_def (__rawmemchr)
> > > +libc_hidden_def (__rawmemchr)
> > > diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> > > new file mode 100644
> > > index 0000000000..eef91e556b
> > > --- /dev/null
> > > +++ b/sysdeps/x86_64/wmemchr.S
> > > @@ -0,0 +1,28 @@
> > > +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#define WMEMCHR __wmemchr
> > > +
> > > +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> > > +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> > > +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> > > +
> > > +#include "isa-default-impl.h"
> > > +
> > > +libc_hidden_def (__wmemchr)
> > > +weak_alias (__wmemchr, wmemchr)
> > > +libc_hidden_weak (wmemchr)
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > H.J.
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
` (5 preceding siblings ...)
2022-06-22 21:48 ` [PATCH v11 " Noah Goldstein
@ 2022-06-22 22:16 ` Noah Goldstein
2022-06-22 22:16 ` [PATCH v12 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 22:54 ` [PATCH v13 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 23:51 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
8 siblings, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 22:16 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++---
sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
5 files changed, 229 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..ba6826d518
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,70 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..7cae11c228
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,102 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+#define ISA_SHOULD_BUILD(isa_build_level) \
+ (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v12 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 22:16 ` [PATCH v12 " Noah Goldstein
@ 2022-06-22 22:16 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 22:16 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86_64/isa-default-impl.h | 10 +
sysdeps/x86_64/memchr.S | 357 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
sysdeps/x86_64/rawmemchr.S | 184 +--------
sysdeps/x86_64/wmemchr.S | 28 ++
21 files changed, 742 insertions(+), 612 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
index 34634668e5..7d7832b1f5 100644
--- a/sysdeps/x86_64/isa-default-impl.h
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -46,4 +46,14 @@
# error "Unsupported ISA Level!"
#endif
+#if IS_IN(rtld)
+# if !defined USE_MULTIARCH
+# error "RTLD version should only exist in multiarch build"
+# endif
+#else
+# if defined USE_MULTIARCH
+# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
+# endif
+#endif
+
#include ISA_DEFAULT_IMPL
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..20b43508c4 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR __memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
-strong_alias (memchr, __memchr)
+weak_alias (__memchr, memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..856c6261f8 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
-
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ const struct cpu_features *cpu_features = __get_cpu_features ();
+
+ /* NB: The X86_ISA_* feature check macros are evaluated at
+ compile time. */
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..39be5f7083 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (3)
# ifndef MEMCHR
# define MEMCHR __memchr_avx2
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..0dd4f1dcce 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (4)
# ifndef MEMCHR
# define MEMCHR __memchr_evex
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..8c561cd687 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,360 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
+#include <sysdep.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
-#endif
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
-#include "../memchr.S"
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..e2c2e20d85 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,192 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
-#endif
+#include <isa-level.h>
+#include <sysdep.h>
+
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
-#include "../rawmemchr.S"
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..b675a070d4 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,7 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
-#include "../memchr.S"
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..ba7e5202e6 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR __rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
-
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
+#include "isa-default-impl.h"
weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+libc_hidden_def (__rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..eef91e556b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,28 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR __wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
+
+libc_hidden_def (__wmemchr)
+weak_alias (__wmemchr, wmemchr)
+libc_hidden_weak (wmemchr)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 21:51 ` H.J. Lu
2022-06-22 22:04 ` Noah Goldstein
@ 2022-06-22 22:16 ` Noah Goldstein
1 sibling, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 22:16 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 2:52 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 1:58 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Refactor files so that all implementations for in the multiarch
> > directory.
> > - Essentially moved sse2 {raw|w}memchr.S implementation to
> > multiarch/{raw|w}memchr-sse2.S
> >
> > - The non-multiarch {raw|w}memchr.S file now only includes one of
> > the implementations in the multiarch directory based on the
> > compiled ISA level (only used for non-multiarch builds.
> > Otherwise we go through the ifunc selector).
> >
> > 2. Add ISA level build guards to different implementations.
> > - I.e memchr-avx2.S which is ISA level 3 will only build if
> > compiled ISA level <= 3. Otherwise there is no reason to include
> > it as we will always use one of the ISA level 4
> > implementations (memchr-evex{-rtm}.S).
> >
> > 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> > non-multiarch {raw}memchr.S which will in turn select the best
> > implementation based on the compiled ISA level.
> >
> > 4. Refactor the ifunc selector and ifunc implementation list to use
> > the ISA level aware wrapper macros that allow functions below the
> > compiled ISA level (with a guranteed replacement) to be skipped.
> > - Guranteed replacement essentially means that for any ISA level
> > build there must be a function that the baseline of the ISA
> > supports. So for {raw|w}memchr.S since there is not ISA level 2
> > function, the ISA level 2 build still includes the ISA level
> > 1 (sse2) function. Once we reach the ISA level 3 build, however,
> > {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> > level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> >
> > And m32 with and without multiarch.
> > ---
> > sysdeps/x86_64/isa-default-impl.h | 8 +
> > sysdeps/x86_64/memchr.S | 357 +----------------
> > sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> > sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
> > sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
> > sysdeps/x86_64/multiarch/memchr-sse2.S | 363 +++++++++++++++++-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 +++++++++-
> > sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> > sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> > sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
> > sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> > sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
> > sysdeps/x86_64/rawmemchr.S | 184 +--------
> > sysdeps/x86_64/wmemchr.S | 28 ++
> > 21 files changed, 740 insertions(+), 612 deletions(-)
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> > create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > create mode 100644 sysdeps/x86_64/wmemchr.S
> >
> > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > index 34634668e5..b374a38b8b 100644
> > --- a/sysdeps/x86_64/isa-default-impl.h
> > +++ b/sysdeps/x86_64/isa-default-impl.h
> > @@ -46,4 +46,12 @@
> > # error "Unsupported ISA Level!"
> > #endif
> >
> > +#if IS_IN(rtld) && !defined USE_MULTIARCH
> > +# error "RTLD version should only exist in multiarch build"
> > +#endif
> > +
> > +#if defined USE_MULTIARCH && !IS_IN(rtld)
> > +# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
> > +#endif
>
> Please do
>
> #if IS_IN (rtld)
Fixed in v12.
> #else
> #endif
>
> > #include ISA_DEFAULT_IMPL
> > diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> > index a160fd9b00..20b43508c4 100644
> > --- a/sysdeps/x86_64/memchr.S
> > +++ b/sysdeps/x86_64/memchr.S
> > @@ -15,358 +15,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define MEMCHR __memchr
> >
> > -#ifdef USE_AS_WMEMCHR
> > -# define MEMCHR wmemchr
> > -# define PCMPEQ pcmpeqd
> > -# define CHAR_PER_VEC 4
> > -#else
> > -# define MEMCHR memchr
> > -# define PCMPEQ pcmpeqb
> > -# define CHAR_PER_VEC 16
> > -#endif
> > +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
> >
> > -/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +#include "isa-default-impl.h"
> >
> > - .text
> > -ENTRY(MEMCHR)
> > - movd %esi, %xmm1
> > - mov %edi, %ecx
> > -
> > -#ifdef __ILP32__
> > - /* Clear the upper 32 bits. */
> > - movl %edx, %edx
> > -#endif
> > -#ifdef USE_AS_WMEMCHR
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > -#else
> > - punpcklbw %xmm1, %xmm1
> > - test %RDX_LP, %RDX_LP
> > - jz L(return_null)
> > - punpcklbw %xmm1, %xmm1
> > -#endif
> > -
> > - and $63, %ecx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %ecx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - and $15, %ecx
> > - and $-16, %rdi
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %ecx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - /* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - /* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > - /* Check which byte is a match. */
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > - possible addition overflow. */
> > - neg %rcx
> > - add $16, %rcx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - sub %rcx, %rdx
> > - jbe L(return_null)
> > - add $16, %rdi
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - PCMPEQ %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - mov %rdi, %rcx
> > - and $-64, %rdi
> > - and $63, %ecx
> > -#ifdef USE_AS_WMEMCHR
> > - shr $2, %ecx
> > -#endif
> > - add %rcx, %rdx
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - sub $(CHAR_PER_VEC * 4), %rdx
> > - jbe L(exit_loop)
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - PCMPEQ %xmm1, %xmm0
> > - PCMPEQ %xmm1, %xmm2
> > - PCMPEQ %xmm1, %xmm3
> > - PCMPEQ %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - jle L(exit_loop_32)
> > -
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - PCMPEQ %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - PCMPEQ %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jle L(return_null)
> > -
> > - PCMPEQ 48(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches48_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(exit_loop_32):
> > - add $(CHAR_PER_VEC * 2), %edx
> > - movdqa (%rdi), %xmm0
> > - PCMPEQ %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches_1)
> > - sub $CHAR_PER_VEC, %edx
> > - jbe L(return_null)
> > -
> > - PCMPEQ 16(%rdi), %xmm1
> > - pmovmskb %xmm1, %eax
> > - test %eax, %eax
> > - jnz L(matches16_1)
> > - xor %eax, %eax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 16(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 32(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches48_1):
> > - bsf %eax, %eax
> > -#ifdef USE_AS_WMEMCHR
> > - mov %eax, %esi
> > - shr $2, %esi
> > - sub %rsi, %rdx
> > -#else
> > - sub %rax, %rdx
> > -#endif
> > - jbe L(return_null)
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(return_null):
> > - xor %eax, %eax
> > - ret
> > -END(MEMCHR)
> > -
> > -#ifndef USE_AS_WMEMCHR
> > -strong_alias (memchr, __memchr)
> > +weak_alias (__memchr, memchr)
> > libc_hidden_builtin_def(memchr)
> > -#endif
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > index b8f7a12ea2..856c6261f8 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> > +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> > @@ -19,24 +19,28 @@
> >
> > #include <init-arch.h>
> >
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> > extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
> >
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> > +
> > +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> >
> > static inline void *
> > IFUNC_SELECTOR (void)
> > {
> > - const struct cpu_features* cpu_features = __get_cpu_features ();
> > -
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> > + const struct cpu_features *cpu_features = __get_cpu_features ();
> > +
> > + /* NB: The X86_ISA_* feature check macros are evaluated at
> > + compile time. */
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + AVX_Fast_Unaligned_Load))
> > {
> > - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> > {
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (evex_rtm);
> > @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> > if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> > return OPTIMIZE (avx2_rtm);
> >
> > - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> > + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > + Prefer_No_VZEROUPPER))
> > return OPTIMIZE (avx2);
> > }
> >
> > + /* This is unreachable (compile time checked) if ISA level >= 3
> > + so no need for a robust fallback here. */
> > return OPTIMIZE (sse2);
> > }
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > index 883362f63d..bf52cf96d0 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > @@ -25,7 +25,8 @@
> >
> > /* Fill ARRAY of MAX elements with IFUNC implementations for function
> > NAME supported on target machine and return the number of valid
> > - entries. */
> > + entries. Each set of implementations for a given function is sorted in
> > + descending order by ISA level. */
> >
> > size_t
> > __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/memchr.c. */
> > IFUNC_IMPL (i, name, memchr,
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __memchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __memchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex)
> > - IFUNC_IMPL_ADD (array, i, memchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __memchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __memchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __memchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> > + 1,
> > + __memchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> > IFUNC_IMPL (i, name, memcmp,
> > @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> > IFUNC_IMPL (i, name, rawmemchr,
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __rawmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __rawmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __rawmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __rawmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __rawmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> > + 1,
> > + __rawmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/strlen.c. */
> > IFUNC_IMPL (i, name, strlen,
> > @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> >
> > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> > IFUNC_IMPL (i, name, wmemchr,
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __wmemchr_avx2)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __wmemchr_avx2_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex)
> > - IFUNC_IMPL_ADD (array, i, wmemchr,
> > + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > && CPU_FEATURE_USABLE (AVX512BW)
> > && CPU_FEATURE_USABLE (BMI2)),
> > __wmemchr_evex_rtm)
> > - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + CPU_FEATURE_USABLE (AVX2),
> > + __wmemchr_avx2)
> > + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __wmemchr_avx2_rtm)
> > + /* Can be lowered to V1 if a V2 implementation is added. */
> > + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> > + 1,
> > + __wmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> > IFUNC_IMPL (i, name, wmemcmp,
> > diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > index c5a256eb37..39be5f7083 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> > @@ -16,9 +16,10 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> >
> > -# include <sysdep.h>
> > +#if ISA_SHOULD_BUILD (3)
> >
> > # ifndef MEMCHR
> > # define MEMCHR __memchr_avx2
> > diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> > index 0fd11b7632..0dd4f1dcce 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> > @@ -16,9 +16,10 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> >
> > -# include <sysdep.h>
> > +#if ISA_SHOULD_BUILD (4)
> >
> > # ifndef MEMCHR
> > # define MEMCHR __memchr_evex
> > diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > index 2c6fdd41d6..8c561cd687 100644
> > --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> > @@ -16,13 +16,360 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#if IS_IN (libc)
> > -# define memchr __memchr_sse2
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> >
> > -# undef strong_alias
> > -# define strong_alias(memchr, __memchr)
> > -# undef libc_hidden_builtin_def
> > -# define libc_hidden_builtin_def(memchr)
> > -#endif
> > +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> > + so we need this to build for ISA V2 builds. */
> > +#if ISA_SHOULD_BUILD (2)
> > +
> > +# ifndef MEMCHR
> > +# define MEMCHR __memchr_sse2
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > +# define PCMPEQ pcmpeqd
> > +# define CHAR_PER_VEC 4
> > +# else
> > +# define PCMPEQ pcmpeqb
> > +# define CHAR_PER_VEC 16
> > +# endif
> > +
> > +/* fast SSE2 version with using pmaxub and 64 byte loop */
> > +
> > + .text
> > +ENTRY(MEMCHR)
> > + movd %esi, %xmm1
> > + mov %edi, %ecx
> > +
> > +# ifdef __ILP32__
> > + /* Clear the upper 32 bits. */
> > + movl %edx, %edx
> > +# endif
> > +# ifdef USE_AS_WMEMCHR
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > +# else
> > + punpcklbw %xmm1, %xmm1
> > + test %RDX_LP, %RDX_LP
> > + jz L(return_null)
> > + punpcklbw %xmm1, %xmm1
> > +# endif
> > +
> > + and $63, %ecx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %ecx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + and $15, %ecx
> > + and $-16, %rdi
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %ecx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + /* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + /* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > + /* Check which byte is a match. */
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> > + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> > + possible addition overflow. */
> > + neg %rcx
> > + add $16, %rcx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + sub %rcx, %rdx
> > + jbe L(return_null)
> > + add $16, %rdi
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + PCMPEQ %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + mov %rdi, %rcx
> > + and $-64, %rdi
> > + and $63, %ecx
> > +# ifdef USE_AS_WMEMCHR
> > + shr $2, %ecx
> > +# endif
> > + add %rcx, %rdx
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + sub $(CHAR_PER_VEC * 4), %rdx
> > + jbe L(exit_loop)
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + PCMPEQ %xmm1, %xmm0
> > + PCMPEQ %xmm1, %xmm2
> > + PCMPEQ %xmm1, %xmm3
> > + PCMPEQ %xmm1, %xmm4
> >
> > -#include "../memchr.S"
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + jle L(exit_loop_32)
> > +
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + PCMPEQ %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + PCMPEQ %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jle L(return_null)
> > +
> > + PCMPEQ 48(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches48_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(exit_loop_32):
> > + add $(CHAR_PER_VEC * 2), %edx
> > + movdqa (%rdi), %xmm0
> > + PCMPEQ %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches_1)
> > + sub $CHAR_PER_VEC, %edx
> > + jbe L(return_null)
> > +
> > + PCMPEQ 16(%rdi), %xmm1
> > + pmovmskb %xmm1, %eax
> > + test %eax, %eax
> > + jnz L(matches16_1)
> > + xor %eax, %eax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 16(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 32(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches48_1):
> > + bsf %eax, %eax
> > +# ifdef USE_AS_WMEMCHR
> > + mov %eax, %esi
> > + shr $2, %esi
> > + sub %rsi, %rdx
> > +# else
> > + sub %rax, %rdx
> > +# endif
> > + jbe L(return_null)
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(return_null):
> > + xor %eax, %eax
> > + ret
> > +END(MEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > index acc5f6e2fb..5c1dcd3ca7 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
>
> Will we ever use the RTM version as the default?
>
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > index 128f9ea637..d6bff28757 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_avx2
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_avx2
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > index deda1ca395..8ff7f27c9c 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex_rtm
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> > +
>
> Will we ever use the RTM version as the default?
>
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > index ec942b77ba..dc1c450699 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __rawmemchr_evex
> > -#define USE_AS_RAWMEMCHR 1
> > +#ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_evex
> > +#endif
> > +#define USE_AS_RAWMEMCHR 1
> > +#define MEMCHR RAWMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > index 3841c14c34..e2c2e20d85 100644
> > --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> > @@ -16,14 +16,192 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -/* Define multiple versions only for the definition in libc. */
> > -#if IS_IN (libc)
> > -# define __rawmemchr __rawmemchr_sse2
> > -
> > -# undef weak_alias
> > -# define weak_alias(__rawmemchr, rawmemchr)
> > -# undef libc_hidden_def
> > -# define libc_hidden_def(__rawmemchr)
> > -#endif
> > +#include <isa-level.h>
> > +#include <sysdep.h>
> > +
> > +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> > + so we need this to build for ISA V2 builds. */
> > +#if ISA_SHOULD_BUILD (2)
> > +
> > +# ifndef RAWMEMCHR
> > +# define RAWMEMCHR __rawmemchr_sse2
> > +# endif
> > +
> > + .text
> > +ENTRY (RAWMEMCHR)
> > + movd %rsi, %xmm1
> > + mov %rdi, %rcx
> > +
> > + punpcklbw %xmm1, %xmm1
> > + punpcklbw %xmm1, %xmm1
> > +
> > + and $63, %rcx
> > + pshufd $0, %xmm1, %xmm1
> > +
> > + cmp $48, %rcx
> > + ja L(crosscache)
> > +
> > + movdqu (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > +
> > + jnz L(matches)
> > + add $16, %rdi
> > + and $-16, %rdi
> > + jmp L(loop_prolog)
> > +
> > + .p2align 4
> > +L(crosscache):
> > + and $15, %rcx
> > + and $-16, %rdi
> > + movdqa (%rdi), %xmm0
> > +
> > + pcmpeqb %xmm1, %xmm0
> > +/* Check if there is a match. */
> > + pmovmskb %xmm0, %eax
> > +/* Remove the leading bytes. */
> > + sar %cl, %eax
> > + test %eax, %eax
> > + je L(unaligned_no_match)
> > +/* Check which byte is a match. */
> > + bsf %eax, %eax
> > +
> > + add %rdi, %rax
> > + add %rcx, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(unaligned_no_match):
> > + add $16, %rdi
> > +
> > + .p2align 4
> > +L(loop_prolog):
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm4
> > + pcmpeqb %xmm1, %xmm4
> > + add $64, %rdi
> > + pmovmskb %xmm4, %eax
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + test $0x3f, %rdi
> > + jz L(align64_loop)
> > +
> > + movdqa (%rdi), %xmm0
> > + pcmpeqb %xmm1, %xmm0
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + movdqa 16(%rdi), %xmm2
> > + pcmpeqb %xmm1, %xmm2
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> >
> > -#include "../rawmemchr.S"
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + movdqa 48(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > + pmovmskb %xmm3, %eax
> > +
> > + add $64, %rdi
> > + test %eax, %eax
> > + jnz L(matches0)
> > +
> > + and $-64, %rdi
> > +
> > + .p2align 4
> > +L(align64_loop):
> > + movdqa (%rdi), %xmm0
> > + movdqa 16(%rdi), %xmm2
> > + movdqa 32(%rdi), %xmm3
> > + movdqa 48(%rdi), %xmm4
> > +
> > + pcmpeqb %xmm1, %xmm0
> > + pcmpeqb %xmm1, %xmm2
> > + pcmpeqb %xmm1, %xmm3
> > + pcmpeqb %xmm1, %xmm4
> > +
> > + pmaxub %xmm0, %xmm3
> > + pmaxub %xmm2, %xmm4
> > + pmaxub %xmm3, %xmm4
> > + pmovmskb %xmm4, %eax
> > +
> > + add $64, %rdi
> > +
> > + test %eax, %eax
> > + jz L(align64_loop)
> > +
> > + sub $64, %rdi
> > +
> > + pmovmskb %xmm0, %eax
> > + test %eax, %eax
> > + jnz L(matches)
> > +
> > + pmovmskb %xmm2, %eax
> > + test %eax, %eax
> > + jnz L(matches16)
> > +
> > + movdqa 32(%rdi), %xmm3
> > + pcmpeqb %xmm1, %xmm3
> > +
> > + pcmpeqb 48(%rdi), %xmm1
> > + pmovmskb %xmm3, %eax
> > + test %eax, %eax
> > + jnz L(matches32)
> > +
> > + pmovmskb %xmm1, %eax
> > + bsf %eax, %eax
> > + lea 48(%rdi, %rax), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches0):
> > + bsf %eax, %eax
> > + lea -16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches):
> > + bsf %eax, %eax
> > + add %rdi, %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches16):
> > + bsf %eax, %eax
> > + lea 16(%rax, %rdi), %rax
> > + ret
> > +
> > + .p2align 4
> > +L(matches32):
> > + bsf %eax, %eax
> > + lea 32(%rax, %rdi), %rax
> > + ret
> > +
> > +END (RAWMEMCHR)
> > +#endif
> > diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > new file mode 100644
> > index 0000000000..a14b192bed
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../memchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > new file mode 100644
> > index 0000000000..5d4110a052
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> > @@ -0,0 +1,18 @@
> > +/* Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include "../rawmemchr.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > index 58ed21db01..2a1cff5b05 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > index 282854f1a1..2bf93fd84b 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_avx2
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_avx2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-avx2.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > index a346cd35a1..c67309e8a1 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
> > @@ -1,3 +1,7 @@
> > -#define MEMCHR __wmemchr_evex_rtm
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex_rtm
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> > +
> > #include "memchr-evex-rtm.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > index 06cd0f9f5a..5512d5cdc3 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> > @@ -1,4 +1,7 @@
> > -#define MEMCHR __wmemchr_evex
> > -#define USE_AS_WMEMCHR 1
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_evex
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > #include "memchr-evex.S"
> > diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > index 70a965d552..b675a070d4 100644
> > --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> > @@ -1,4 +1,7 @@
> > -#define USE_AS_WMEMCHR 1
> > -#define wmemchr __wmemchr_sse2
> > +#ifndef WMEMCHR
> > +# define WMEMCHR __wmemchr_sse2
> > +#endif
> > +#define USE_AS_WMEMCHR 1
> > +#define MEMCHR WMEMCHR
> >
> > -#include "../memchr.S"
> > +#include "memchr-sse2.S"
> > diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> > index 4c1a3383b9..ba7e5202e6 100644
> > --- a/sysdeps/x86_64/rawmemchr.S
> > +++ b/sysdeps/x86_64/rawmemchr.S
> > @@ -17,185 +17,13 @@
> > License along with the GNU C Library; if not, see
> > <https://www.gnu.org/licenses/>. */
> >
> > -#include <sysdep.h>
> > +#define RAWMEMCHR __rawmemchr
> >
> > - .text
> > -ENTRY (__rawmemchr)
> > - movd %rsi, %xmm1
> > - mov %rdi, %rcx
> > +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
> >
> > - punpcklbw %xmm1, %xmm1
> > - punpcklbw %xmm1, %xmm1
> > -
> > - and $63, %rcx
> > - pshufd $0, %xmm1, %xmm1
> > -
> > - cmp $48, %rcx
> > - ja L(crosscache)
> > -
> > - movdqu (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > -
> > - jnz L(matches)
> > - add $16, %rdi
> > - and $-16, %rdi
> > - jmp L(loop_prolog)
> > -
> > - .p2align 4
> > -L(crosscache):
> > - and $15, %rcx
> > - and $-16, %rdi
> > - movdqa (%rdi), %xmm0
> > -
> > - pcmpeqb %xmm1, %xmm0
> > -/* Check if there is a match. */
> > - pmovmskb %xmm0, %eax
> > -/* Remove the leading bytes. */
> > - sar %cl, %eax
> > - test %eax, %eax
> > - je L(unaligned_no_match)
> > -/* Check which byte is a match. */
> > - bsf %eax, %eax
> > -
> > - add %rdi, %rax
> > - add %rcx, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(unaligned_no_match):
> > - add $16, %rdi
> > -
> > - .p2align 4
> > -L(loop_prolog):
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm4
> > - pcmpeqb %xmm1, %xmm4
> > - add $64, %rdi
> > - pmovmskb %xmm4, %eax
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - test $0x3f, %rdi
> > - jz L(align64_loop)
> > -
> > - movdqa (%rdi), %xmm0
> > - pcmpeqb %xmm1, %xmm0
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - movdqa 16(%rdi), %xmm2
> > - pcmpeqb %xmm1, %xmm2
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - movdqa 48(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > - pmovmskb %xmm3, %eax
> > -
> > - add $64, %rdi
> > - test %eax, %eax
> > - jnz L(matches0)
> > -
> > - and $-64, %rdi
> > -
> > - .p2align 4
> > -L(align64_loop):
> > - movdqa (%rdi), %xmm0
> > - movdqa 16(%rdi), %xmm2
> > - movdqa 32(%rdi), %xmm3
> > - movdqa 48(%rdi), %xmm4
> > -
> > - pcmpeqb %xmm1, %xmm0
> > - pcmpeqb %xmm1, %xmm2
> > - pcmpeqb %xmm1, %xmm3
> > - pcmpeqb %xmm1, %xmm4
> > -
> > - pmaxub %xmm0, %xmm3
> > - pmaxub %xmm2, %xmm4
> > - pmaxub %xmm3, %xmm4
> > - pmovmskb %xmm4, %eax
> > -
> > - add $64, %rdi
> > -
> > - test %eax, %eax
> > - jz L(align64_loop)
> > -
> > - sub $64, %rdi
> > -
> > - pmovmskb %xmm0, %eax
> > - test %eax, %eax
> > - jnz L(matches)
> > -
> > - pmovmskb %xmm2, %eax
> > - test %eax, %eax
> > - jnz L(matches16)
> > -
> > - movdqa 32(%rdi), %xmm3
> > - pcmpeqb %xmm1, %xmm3
> > -
> > - pcmpeqb 48(%rdi), %xmm1
> > - pmovmskb %xmm3, %eax
> > - test %eax, %eax
> > - jnz L(matches32)
> > -
> > - pmovmskb %xmm1, %eax
> > - bsf %eax, %eax
> > - lea 48(%rdi, %rax), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches0):
> > - bsf %eax, %eax
> > - lea -16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches):
> > - bsf %eax, %eax
> > - add %rdi, %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches16):
> > - bsf %eax, %eax
> > - lea 16(%rax, %rdi), %rax
> > - ret
> > -
> > - .p2align 4
> > -L(matches32):
> > - bsf %eax, %eax
> > - lea 32(%rax, %rdi), %rax
> > - ret
> > -
> > -END (__rawmemchr)
> > +#include "isa-default-impl.h"
> >
> > weak_alias (__rawmemchr, rawmemchr)
> > -libc_hidden_builtin_def (__rawmemchr)
> > +libc_hidden_def (__rawmemchr)
> > diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> > new file mode 100644
> > index 0000000000..eef91e556b
> > --- /dev/null
> > +++ b/sysdeps/x86_64/wmemchr.S
> > @@ -0,0 +1,28 @@
> > +/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#define WMEMCHR __wmemchr
> > +
> > +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> > +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> > +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> > +
> > +#include "isa-default-impl.h"
> > +
> > +libc_hidden_def (__wmemchr)
> > +weak_alias (__wmemchr, wmemchr)
> > +libc_hidden_weak (wmemchr)
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v13 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
` (6 preceding siblings ...)
2022-06-22 22:16 ` [PATCH v12 " Noah Goldstein
@ 2022-06-22 22:54 ` Noah Goldstein
2022-06-22 22:54 ` [PATCH v13 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 23:51 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
8 siblings, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 22:54 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++---
sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
5 files changed, 229 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..ba6826d518
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,70 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..7cae11c228
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,102 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+#define ISA_SHOULD_BUILD(isa_build_level) \
+ (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v13 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 22:54 ` [PATCH v13 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 22:54 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 22:54 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86_64/isa-default-impl.h | 10 +
sysdeps/x86_64/memchr.S | 357 +-------------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 363 ++++++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 ++++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
sysdeps/x86_64/rawmemchr.S | 184 +----------
sysdeps/x86_64/wmemchr.S | 28 ++
17 files changed, 720 insertions(+), 604 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
index 34634668e5..7d7832b1f5 100644
--- a/sysdeps/x86_64/isa-default-impl.h
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -46,4 +46,14 @@
# error "Unsupported ISA Level!"
#endif
+#if IS_IN(rtld)
+# if !defined USE_MULTIARCH
+# error "RTLD version should only exist in multiarch build"
+# endif
+#else
+# if defined USE_MULTIARCH
+# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
+# endif
+#endif
+
#include ISA_DEFAULT_IMPL
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..20b43508c4 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR __memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
-strong_alias (memchr, __memchr)
+weak_alias (__memchr, memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..856c6261f8 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
-
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ const struct cpu_features *cpu_features = __get_cpu_features ();
+
+ /* NB: The X86_ISA_* feature check macros are evaluated at
+ compile time. */
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..39be5f7083 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (3)
# ifndef MEMCHR
# define MEMCHR __memchr_avx2
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..0dd4f1dcce 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (4)
# ifndef MEMCHR
# define MEMCHR __memchr_evex
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..8c561cd687 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,360 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
+#include <sysdep.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
-#endif
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
-#include "../memchr.S"
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..e2c2e20d85 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,192 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
-#endif
+#include <isa-level.h>
+#include <sysdep.h>
+
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
-#include "../rawmemchr.S"
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..b675a070d4 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,7 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
-#include "../memchr.S"
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..ba7e5202e6 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR __rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
-
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
+#include "isa-default-impl.h"
weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+libc_hidden_def (__rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..eef91e556b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,28 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR __wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
+
+libc_hidden_def (__wmemchr)
+weak_alias (__wmemchr, wmemchr)
+libc_hidden_weak (wmemchr)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
` (7 preceding siblings ...)
2022-06-22 22:54 ` [PATCH v13 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 23:51 ` Noah Goldstein
2022-06-22 23:51 ` [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-23 2:06 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
8 siblings, 2 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 23:51 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++---
sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
5 files changed, 229 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..ba6826d518
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,70 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+#endif
+
+#ifndef X86_IFUNC_IMPL_ADD_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+#endif
+#ifndef X86_IFUNC_IMPL_ADD_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..7cae11c228
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,102 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+#define ISA_SHOULD_BUILD(isa_build_level) \
+ (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 23:51 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 23:51 ` Noah Goldstein
2022-06-23 2:05 ` H.J. Lu
2022-06-23 17:14 ` Joseph Myers
2022-06-23 2:06 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 2 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-22 23:51 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
---
sysdeps/x86_64/isa-default-impl.h | 10 +
sysdeps/x86_64/memchr.S | 357 +-------------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 363 ++++++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 ++++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
sysdeps/x86_64/rawmemchr.S | 184 +----------
sysdeps/x86_64/wmemchr.S | 28 ++
17 files changed, 720 insertions(+), 604 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
index 34634668e5..7d7832b1f5 100644
--- a/sysdeps/x86_64/isa-default-impl.h
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -46,4 +46,14 @@
# error "Unsupported ISA Level!"
#endif
+#if IS_IN(rtld)
+# if !defined USE_MULTIARCH
+# error "RTLD version should only exist in multiarch build"
+# endif
+#else
+# if defined USE_MULTIARCH
+# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
+# endif
+#endif
+
#include ISA_DEFAULT_IMPL
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..20b43508c4 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR __memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
-strong_alias (memchr, __memchr)
+weak_alias (__memchr, memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..856c6261f8 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,24 +19,28 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
-
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ const struct cpu_features *cpu_features = __get_cpu_features ();
+
+ /* NB: The X86_ISA_* feature check macros are evaluated at
+ compile time. */
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (evex_rtm);
@@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
return OPTIMIZE (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
return OPTIMIZE (avx2);
}
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
return OPTIMIZE (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..39be5f7083 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (3)
# ifndef MEMCHR
# define MEMCHR __memchr_avx2
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..0dd4f1dcce 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,9 +16,10 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+#include <sysdep.h>
-# include <sysdep.h>
+#if ISA_SHOULD_BUILD (4)
# ifndef MEMCHR
# define MEMCHR __memchr_evex
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..8c561cd687 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,360 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
+#include <sysdep.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
-#endif
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
-#include "../memchr.S"
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..e2c2e20d85 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,192 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
-#endif
+#include <isa-level.h>
+#include <sysdep.h>
+
+/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
+ so we need this to build for ISA V2 builds. */
+#if ISA_SHOULD_BUILD (2)
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
-#include "../rawmemchr.S"
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..b675a070d4 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,7 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
-#include "../memchr.S"
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..ba7e5202e6 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR __rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
-
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
+#include "isa-default-impl.h"
weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+libc_hidden_def (__rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..30565b2067
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,28 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR __wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
+
+libc_hidden_def (__wmemchr)
+weak_alias (__wmemchr, wmemchr)
+libc_hidden_weak (wmemchr)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 23:51 ` [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-23 2:05 ` H.J. Lu
2022-06-23 17:14 ` Joseph Myers
1 sibling, 0 replies; 36+ messages in thread
From: H.J. Lu @ 2022-06-23 2:05 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 4:51 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Refactor files so that all implementations for in the multiarch
> directory.
> - Essentially moved sse2 {raw|w}memchr.S implementation to
> multiarch/{raw|w}memchr-sse2.S
>
> - The non-multiarch {raw|w}memchr.S file now only includes one of
> the implementations in the multiarch directory based on the
> compiled ISA level (only used for non-multiarch builds.
> Otherwise we go through the ifunc selector).
>
> 2. Add ISA level build guards to different implementations.
> - I.e memchr-avx2.S which is ISA level 3 will only build if
> compiled ISA level <= 3. Otherwise there is no reason to include
> it as we will always use one of the ISA level 4
> implementations (memchr-evex{-rtm}.S).
>
> 3. Add new multiarch/rtld-{raw}memchr.S that just include the
> non-multiarch {raw}memchr.S which will in turn select the best
> implementation based on the compiled ISA level.
>
> 4. Refactor the ifunc selector and ifunc implementation list to use
> the ISA level aware wrapper macros that allow functions below the
> compiled ISA level (with a guranteed replacement) to be skipped.
> - Guranteed replacement essentially means that for any ISA level
> build there must be a function that the baseline of the ISA
> supports. So for {raw|w}memchr.S since there is not ISA level 2
> function, the ISA level 2 build still includes the ISA level
> 1 (sse2) function. Once we reach the ISA level 3 build, however,
> {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
> level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
>
> And m32 with and without multiarch.
> ---
> sysdeps/x86_64/isa-default-impl.h | 10 +
> sysdeps/x86_64/memchr.S | 357 +-------------------
> sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +-
> sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
> sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +-
> sysdeps/x86_64/multiarch/memchr-evex.S | 5 +-
> sysdeps/x86_64/multiarch/memchr-sse2.S | 363 ++++++++++++++++++++-
> sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 ++++++++++-
> sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
> sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
> sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
> sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +-
> sysdeps/x86_64/rawmemchr.S | 184 +----------
> sysdeps/x86_64/wmemchr.S | 28 ++
> 17 files changed, 720 insertions(+), 604 deletions(-)
> create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
> create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> create mode 100644 sysdeps/x86_64/wmemchr.S
>
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> index 34634668e5..7d7832b1f5 100644
> --- a/sysdeps/x86_64/isa-default-impl.h
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -46,4 +46,14 @@
> # error "Unsupported ISA Level!"
> #endif
>
> +#if IS_IN(rtld)
> +# if !defined USE_MULTIARCH
> +# error "RTLD version should only exist in multiarch build"
> +# endif
> +#else
> +# if defined USE_MULTIARCH
> +# error "Multiarch build should not use ISA_DEFAULT_IMPL without RTLD"
> +# endif
> +#endif
> +
> #include ISA_DEFAULT_IMPL
> diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
> index a160fd9b00..20b43508c4 100644
> --- a/sysdeps/x86_64/memchr.S
> +++ b/sysdeps/x86_64/memchr.S
> @@ -15,358 +15,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define MEMCHR __memchr
>
> -#ifdef USE_AS_WMEMCHR
> -# define MEMCHR wmemchr
> -# define PCMPEQ pcmpeqd
> -# define CHAR_PER_VEC 4
> -#else
> -# define MEMCHR memchr
> -# define PCMPEQ pcmpeqb
> -# define CHAR_PER_VEC 16
> -#endif
> +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
>
> -/* fast SSE2 version with using pmaxub and 64 byte loop */
> +#include "isa-default-impl.h"
>
> - .text
> -ENTRY(MEMCHR)
> - movd %esi, %xmm1
> - mov %edi, %ecx
> -
> -#ifdef __ILP32__
> - /* Clear the upper 32 bits. */
> - movl %edx, %edx
> -#endif
> -#ifdef USE_AS_WMEMCHR
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> -#else
> - punpcklbw %xmm1, %xmm1
> - test %RDX_LP, %RDX_LP
> - jz L(return_null)
> - punpcklbw %xmm1, %xmm1
> -#endif
> -
> - and $63, %ecx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %ecx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - and $15, %ecx
> - and $-16, %rdi
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %ecx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - PCMPEQ %xmm1, %xmm0
> - /* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - /* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> - /* Check which byte is a match. */
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> - possible addition overflow. */
> - neg %rcx
> - add $16, %rcx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - sub %rcx, %rdx
> - jbe L(return_null)
> - add $16, %rdi
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - PCMPEQ %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - mov %rdi, %rcx
> - and $-64, %rdi
> - and $63, %ecx
> -#ifdef USE_AS_WMEMCHR
> - shr $2, %ecx
> -#endif
> - add %rcx, %rdx
> -
> - .p2align 4
> -L(align64_loop):
> - sub $(CHAR_PER_VEC * 4), %rdx
> - jbe L(exit_loop)
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - PCMPEQ %xmm1, %xmm0
> - PCMPEQ %xmm1, %xmm2
> - PCMPEQ %xmm1, %xmm3
> - PCMPEQ %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(exit_loop):
> - add $(CHAR_PER_VEC * 2), %edx
> - jle L(exit_loop_32)
> -
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - PCMPEQ %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - PCMPEQ %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32_1)
> - sub $CHAR_PER_VEC, %edx
> - jle L(return_null)
> -
> - PCMPEQ 48(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches48_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(exit_loop_32):
> - add $(CHAR_PER_VEC * 2), %edx
> - movdqa (%rdi), %xmm0
> - PCMPEQ %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches_1)
> - sub $CHAR_PER_VEC, %edx
> - jbe L(return_null)
> -
> - PCMPEQ 16(%rdi), %xmm1
> - pmovmskb %xmm1, %eax
> - test %eax, %eax
> - jnz L(matches16_1)
> - xor %eax, %eax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 16(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches32_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 32(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches48_1):
> - bsf %eax, %eax
> -#ifdef USE_AS_WMEMCHR
> - mov %eax, %esi
> - shr $2, %esi
> - sub %rsi, %rdx
> -#else
> - sub %rax, %rdx
> -#endif
> - jbe L(return_null)
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(return_null):
> - xor %eax, %eax
> - ret
> -END(MEMCHR)
> -
> -#ifndef USE_AS_WMEMCHR
> -strong_alias (memchr, __memchr)
> +weak_alias (__memchr, memchr)
> libc_hidden_builtin_def(memchr)
> -#endif
> diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
> index b8f7a12ea2..856c6261f8 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-evex.h
> +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
> @@ -19,24 +19,28 @@
>
> #include <init-arch.h>
>
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
>
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
> +
> +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
>
> static inline void *
> IFUNC_SELECTOR (void)
> {
> - const struct cpu_features* cpu_features = __get_cpu_features ();
> -
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> + const struct cpu_features *cpu_features = __get_cpu_features ();
> +
> + /* NB: The X86_ISA_* feature check macros are evaluated at
> + compile time. */
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + AVX_Fast_Unaligned_Load))
> {
> - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
> + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (evex_rtm);
> @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void)
> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
> return OPTIMIZE (avx2_rtm);
>
> - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> + Prefer_No_VZEROUPPER))
> return OPTIMIZE (avx2);
> }
>
> + /* This is unreachable (compile time checked) if ISA level >= 3
> + so no need for a robust fallback here. */
> return OPTIMIZE (sse2);
> }
> diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> index 883362f63d..bf52cf96d0 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> @@ -25,7 +25,8 @@
>
> /* Fill ARRAY of MAX elements with IFUNC implementations for function
> NAME supported on target machine and return the number of valid
> - entries. */
> + entries. Each set of implementations for a given function is sorted in
> + descending order by ISA level. */
>
> size_t
> __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/memchr.c. */
> IFUNC_IMPL (i, name, memchr,
> - IFUNC_IMPL_ADD (array, i, memchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __memchr_avx2)
> - IFUNC_IMPL_ADD (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __memchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex)
> - IFUNC_IMPL_ADD (array, i, memchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __memchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __memchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __memchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> + 1,
> + __memchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> IFUNC_IMPL (i, name, memcmp,
> @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> IFUNC_IMPL (i, name, rawmemchr,
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __rawmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __rawmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, rawmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __rawmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __rawmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __rawmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> + 1,
> + __rawmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/strlen.c. */
> IFUNC_IMPL (i, name, strlen,
> @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
>
> /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> IFUNC_IMPL (i, name, wmemchr,
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __wmemchr_avx2)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __wmemchr_avx2_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex)
> - IFUNC_IMPL_ADD (array, i, wmemchr,
> + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> (CPU_FEATURE_USABLE (AVX512VL)
> && CPU_FEATURE_USABLE (AVX512BW)
> && CPU_FEATURE_USABLE (BMI2)),
> __wmemchr_evex_rtm)
> - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + CPU_FEATURE_USABLE (AVX2),
> + __wmemchr_avx2)
> + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __wmemchr_avx2_rtm)
> + /* Can be lowered to V1 if a V2 implementation is added. */
> + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> + 1,
> + __wmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> IFUNC_IMPL (i, name, wmemcmp,
> diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
> index c5a256eb37..39be5f7083 100644
> --- a/sysdeps/x86_64/multiarch/memchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
> @@ -16,9 +16,10 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +#include <sysdep.h>
>
> -# include <sysdep.h>
> +#if ISA_SHOULD_BUILD (3)
>
> # ifndef MEMCHR
> # define MEMCHR __memchr_avx2
> diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
> index 0fd11b7632..0dd4f1dcce 100644
> --- a/sysdeps/x86_64/multiarch/memchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/memchr-evex.S
> @@ -16,9 +16,10 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> +#include <isa-level.h>
> +#include <sysdep.h>
>
> -# include <sysdep.h>
> +#if ISA_SHOULD_BUILD (4)
>
> # ifndef MEMCHR
> # define MEMCHR __memchr_evex
> diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
> index 2c6fdd41d6..8c561cd687 100644
> --- a/sysdeps/x86_64/multiarch/memchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
> @@ -16,13 +16,360 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#if IS_IN (libc)
> -# define memchr __memchr_sse2
> +#include <isa-level.h>
> +#include <sysdep.h>
>
> -# undef strong_alias
> -# define strong_alias(memchr, __memchr)
> -# undef libc_hidden_builtin_def
> -# define libc_hidden_builtin_def(memchr)
> -#endif
> +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> + so we need this to build for ISA V2 builds. */
> +#if ISA_SHOULD_BUILD (2)
> +
> +# ifndef MEMCHR
> +# define MEMCHR __memchr_sse2
> +# endif
> +# ifdef USE_AS_WMEMCHR
> +# define PCMPEQ pcmpeqd
> +# define CHAR_PER_VEC 4
> +# else
> +# define PCMPEQ pcmpeqb
> +# define CHAR_PER_VEC 16
> +# endif
> +
> +/* fast SSE2 version with using pmaxub and 64 byte loop */
> +
> + .text
> +ENTRY(MEMCHR)
> + movd %esi, %xmm1
> + mov %edi, %ecx
> +
> +# ifdef __ILP32__
> + /* Clear the upper 32 bits. */
> + movl %edx, %edx
> +# endif
> +# ifdef USE_AS_WMEMCHR
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> +# else
> + punpcklbw %xmm1, %xmm1
> + test %RDX_LP, %RDX_LP
> + jz L(return_null)
> + punpcklbw %xmm1, %xmm1
> +# endif
> +
> + and $63, %ecx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %ecx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + and $15, %ecx
> + and $-16, %rdi
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %ecx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + PCMPEQ %xmm1, %xmm0
> + /* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + /* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> + /* Check which byte is a match. */
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
> + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
> + possible addition overflow. */
> + neg %rcx
> + add $16, %rcx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + sub %rcx, %rdx
> + jbe L(return_null)
> + add $16, %rdi
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + PCMPEQ %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + mov %rdi, %rcx
> + and $-64, %rdi
> + and $63, %ecx
> +# ifdef USE_AS_WMEMCHR
> + shr $2, %ecx
> +# endif
> + add %rcx, %rdx
> +
> + .p2align 4
> +L(align64_loop):
> + sub $(CHAR_PER_VEC * 4), %rdx
> + jbe L(exit_loop)
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + PCMPEQ %xmm1, %xmm0
> + PCMPEQ %xmm1, %xmm2
> + PCMPEQ %xmm1, %xmm3
> + PCMPEQ %xmm1, %xmm4
>
> -#include "../memchr.S"
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(exit_loop):
> + add $(CHAR_PER_VEC * 2), %edx
> + jle L(exit_loop_32)
> +
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + PCMPEQ %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + PCMPEQ %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32_1)
> + sub $CHAR_PER_VEC, %edx
> + jle L(return_null)
> +
> + PCMPEQ 48(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches48_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(exit_loop_32):
> + add $(CHAR_PER_VEC * 2), %edx
> + movdqa (%rdi), %xmm0
> + PCMPEQ %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches_1)
> + sub $CHAR_PER_VEC, %edx
> + jbe L(return_null)
> +
> + PCMPEQ 16(%rdi), %xmm1
> + pmovmskb %xmm1, %eax
> + test %eax, %eax
> + jnz L(matches16_1)
> + xor %eax, %eax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 16(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches32_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 32(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches48_1):
> + bsf %eax, %eax
> +# ifdef USE_AS_WMEMCHR
> + mov %eax, %esi
> + shr $2, %esi
> + sub %rsi, %rdx
> +# else
> + sub %rax, %rdx
> +# endif
> + jbe L(return_null)
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(return_null):
> + xor %eax, %eax
> + ret
> +END(MEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> index 128f9ea637..d6bff28757 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_avx2
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_avx2
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> index ec942b77ba..dc1c450699 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __rawmemchr_evex
> -#define USE_AS_RAWMEMCHR 1
> +#ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_evex
> +#endif
> +#define USE_AS_RAWMEMCHR 1
> +#define MEMCHR RAWMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> index 3841c14c34..e2c2e20d85 100644
> --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
> @@ -16,14 +16,192 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -/* Define multiple versions only for the definition in libc. */
> -#if IS_IN (libc)
> -# define __rawmemchr __rawmemchr_sse2
> -
> -# undef weak_alias
> -# define weak_alias(__rawmemchr, rawmemchr)
> -# undef libc_hidden_def
> -# define libc_hidden_def(__rawmemchr)
> -#endif
> +#include <isa-level.h>
> +#include <sysdep.h>
> +
> +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
> + so we need this to build for ISA V2 builds. */
> +#if ISA_SHOULD_BUILD (2)
> +
> +# ifndef RAWMEMCHR
> +# define RAWMEMCHR __rawmemchr_sse2
> +# endif
> +
> + .text
> +ENTRY (RAWMEMCHR)
> + movd %rsi, %xmm1
> + mov %rdi, %rcx
> +
> + punpcklbw %xmm1, %xmm1
> + punpcklbw %xmm1, %xmm1
> +
> + and $63, %rcx
> + pshufd $0, %xmm1, %xmm1
> +
> + cmp $48, %rcx
> + ja L(crosscache)
> +
> + movdqu (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> +
> + jnz L(matches)
> + add $16, %rdi
> + and $-16, %rdi
> + jmp L(loop_prolog)
> +
> + .p2align 4
> +L(crosscache):
> + and $15, %rcx
> + and $-16, %rdi
> + movdqa (%rdi), %xmm0
> +
> + pcmpeqb %xmm1, %xmm0
> +/* Check if there is a match. */
> + pmovmskb %xmm0, %eax
> +/* Remove the leading bytes. */
> + sar %cl, %eax
> + test %eax, %eax
> + je L(unaligned_no_match)
> +/* Check which byte is a match. */
> + bsf %eax, %eax
> +
> + add %rdi, %rax
> + add %rcx, %rax
> + ret
> +
> + .p2align 4
> +L(unaligned_no_match):
> + add $16, %rdi
> +
> + .p2align 4
> +L(loop_prolog):
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm4
> + pcmpeqb %xmm1, %xmm4
> + add $64, %rdi
> + pmovmskb %xmm4, %eax
> + test %eax, %eax
> + jnz L(matches0)
> +
> + test $0x3f, %rdi
> + jz L(align64_loop)
> +
> + movdqa (%rdi), %xmm0
> + pcmpeqb %xmm1, %xmm0
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + movdqa 16(%rdi), %xmm2
> + pcmpeqb %xmm1, %xmm2
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
>
> -#include "../rawmemchr.S"
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + movdqa 48(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> + pmovmskb %xmm3, %eax
> +
> + add $64, %rdi
> + test %eax, %eax
> + jnz L(matches0)
> +
> + and $-64, %rdi
> +
> + .p2align 4
> +L(align64_loop):
> + movdqa (%rdi), %xmm0
> + movdqa 16(%rdi), %xmm2
> + movdqa 32(%rdi), %xmm3
> + movdqa 48(%rdi), %xmm4
> +
> + pcmpeqb %xmm1, %xmm0
> + pcmpeqb %xmm1, %xmm2
> + pcmpeqb %xmm1, %xmm3
> + pcmpeqb %xmm1, %xmm4
> +
> + pmaxub %xmm0, %xmm3
> + pmaxub %xmm2, %xmm4
> + pmaxub %xmm3, %xmm4
> + pmovmskb %xmm4, %eax
> +
> + add $64, %rdi
> +
> + test %eax, %eax
> + jz L(align64_loop)
> +
> + sub $64, %rdi
> +
> + pmovmskb %xmm0, %eax
> + test %eax, %eax
> + jnz L(matches)
> +
> + pmovmskb %xmm2, %eax
> + test %eax, %eax
> + jnz L(matches16)
> +
> + movdqa 32(%rdi), %xmm3
> + pcmpeqb %xmm1, %xmm3
> +
> + pcmpeqb 48(%rdi), %xmm1
> + pmovmskb %xmm3, %eax
> + test %eax, %eax
> + jnz L(matches32)
> +
> + pmovmskb %xmm1, %eax
> + bsf %eax, %eax
> + lea 48(%rdi, %rax), %rax
> + ret
> +
> + .p2align 4
> +L(matches0):
> + bsf %eax, %eax
> + lea -16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches):
> + bsf %eax, %eax
> + add %rdi, %rax
> + ret
> +
> + .p2align 4
> +L(matches16):
> + bsf %eax, %eax
> + lea 16(%rax, %rdi), %rax
> + ret
> +
> + .p2align 4
> +L(matches32):
> + bsf %eax, %eax
> + lea 32(%rax, %rdi), %rax
> + ret
> +
> +END (RAWMEMCHR)
> +#endif
> diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
> new file mode 100644
> index 0000000000..a14b192bed
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../memchr.S"
> diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> new file mode 100644
> index 0000000000..5d4110a052
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
> @@ -0,0 +1,18 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include "../rawmemchr.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> index 282854f1a1..2bf93fd84b 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_avx2
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_avx2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-avx2.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> index 06cd0f9f5a..5512d5cdc3 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
> @@ -1,4 +1,7 @@
> -#define MEMCHR __wmemchr_evex
> -#define USE_AS_WMEMCHR 1
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_evex
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> #include "memchr-evex.S"
> diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> index 70a965d552..b675a070d4 100644
> --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
> @@ -1,4 +1,7 @@
> -#define USE_AS_WMEMCHR 1
> -#define wmemchr __wmemchr_sse2
> +#ifndef WMEMCHR
> +# define WMEMCHR __wmemchr_sse2
> +#endif
> +#define USE_AS_WMEMCHR 1
> +#define MEMCHR WMEMCHR
>
> -#include "../memchr.S"
> +#include "memchr-sse2.S"
> diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
> index 4c1a3383b9..ba7e5202e6 100644
> --- a/sysdeps/x86_64/rawmemchr.S
> +++ b/sysdeps/x86_64/rawmemchr.S
> @@ -17,185 +17,13 @@
> License along with the GNU C Library; if not, see
> <https://www.gnu.org/licenses/>. */
>
> -#include <sysdep.h>
> +#define RAWMEMCHR __rawmemchr
>
> - .text
> -ENTRY (__rawmemchr)
> - movd %rsi, %xmm1
> - mov %rdi, %rcx
> +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
>
> - punpcklbw %xmm1, %xmm1
> - punpcklbw %xmm1, %xmm1
> -
> - and $63, %rcx
> - pshufd $0, %xmm1, %xmm1
> -
> - cmp $48, %rcx
> - ja L(crosscache)
> -
> - movdqu (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> -
> - jnz L(matches)
> - add $16, %rdi
> - and $-16, %rdi
> - jmp L(loop_prolog)
> -
> - .p2align 4
> -L(crosscache):
> - and $15, %rcx
> - and $-16, %rdi
> - movdqa (%rdi), %xmm0
> -
> - pcmpeqb %xmm1, %xmm0
> -/* Check if there is a match. */
> - pmovmskb %xmm0, %eax
> -/* Remove the leading bytes. */
> - sar %cl, %eax
> - test %eax, %eax
> - je L(unaligned_no_match)
> -/* Check which byte is a match. */
> - bsf %eax, %eax
> -
> - add %rdi, %rax
> - add %rcx, %rax
> - ret
> -
> - .p2align 4
> -L(unaligned_no_match):
> - add $16, %rdi
> -
> - .p2align 4
> -L(loop_prolog):
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm4
> - pcmpeqb %xmm1, %xmm4
> - add $64, %rdi
> - pmovmskb %xmm4, %eax
> - test %eax, %eax
> - jnz L(matches0)
> -
> - test $0x3f, %rdi
> - jz L(align64_loop)
> -
> - movdqa (%rdi), %xmm0
> - pcmpeqb %xmm1, %xmm0
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - movdqa 16(%rdi), %xmm2
> - pcmpeqb %xmm1, %xmm2
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - movdqa 48(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> - pmovmskb %xmm3, %eax
> -
> - add $64, %rdi
> - test %eax, %eax
> - jnz L(matches0)
> -
> - and $-64, %rdi
> -
> - .p2align 4
> -L(align64_loop):
> - movdqa (%rdi), %xmm0
> - movdqa 16(%rdi), %xmm2
> - movdqa 32(%rdi), %xmm3
> - movdqa 48(%rdi), %xmm4
> -
> - pcmpeqb %xmm1, %xmm0
> - pcmpeqb %xmm1, %xmm2
> - pcmpeqb %xmm1, %xmm3
> - pcmpeqb %xmm1, %xmm4
> -
> - pmaxub %xmm0, %xmm3
> - pmaxub %xmm2, %xmm4
> - pmaxub %xmm3, %xmm4
> - pmovmskb %xmm4, %eax
> -
> - add $64, %rdi
> -
> - test %eax, %eax
> - jz L(align64_loop)
> -
> - sub $64, %rdi
> -
> - pmovmskb %xmm0, %eax
> - test %eax, %eax
> - jnz L(matches)
> -
> - pmovmskb %xmm2, %eax
> - test %eax, %eax
> - jnz L(matches16)
> -
> - movdqa 32(%rdi), %xmm3
> - pcmpeqb %xmm1, %xmm3
> -
> - pcmpeqb 48(%rdi), %xmm1
> - pmovmskb %xmm3, %eax
> - test %eax, %eax
> - jnz L(matches32)
> -
> - pmovmskb %xmm1, %eax
> - bsf %eax, %eax
> - lea 48(%rdi, %rax), %rax
> - ret
> -
> - .p2align 4
> -L(matches0):
> - bsf %eax, %eax
> - lea -16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches):
> - bsf %eax, %eax
> - add %rdi, %rax
> - ret
> -
> - .p2align 4
> -L(matches16):
> - bsf %eax, %eax
> - lea 16(%rax, %rdi), %rax
> - ret
> -
> - .p2align 4
> -L(matches32):
> - bsf %eax, %eax
> - lea 32(%rax, %rdi), %rax
> - ret
> -
> -END (__rawmemchr)
> +#include "isa-default-impl.h"
>
> weak_alias (__rawmemchr, rawmemchr)
> -libc_hidden_builtin_def (__rawmemchr)
> +libc_hidden_def (__rawmemchr)
> diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
> new file mode 100644
> index 0000000000..30565b2067
> --- /dev/null
> +++ b/sysdeps/x86_64/wmemchr.S
> @@ -0,0 +1,28 @@
> +/* Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#define WMEMCHR __wmemchr
> +
> +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
> +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
> +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
> +
> +#include "isa-default-impl.h"
> +
> +libc_hidden_def (__wmemchr)
> +weak_alias (__wmemchr, wmemchr)
> +libc_hidden_weak (wmemchr)
> --
> 2.34.1
>
LGTM.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 23:51 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 23:51 ` [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-23 2:06 ` H.J. Lu
1 sibling, 0 replies; 36+ messages in thread
From: H.J. Lu @ 2022-06-23 2:06 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 4:51 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
>
> And m32 with and without multiarch.
> ---
> sysdeps/x86/init-arch.h | 4 +-
> sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++---
> sysdeps/x86/isa-level.h | 102 ++++++++++++++++++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++++
> 5 files changed, 229 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a2886a2532 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,9 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..ba6826d518
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,70 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +#include <stdlib.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +#endif
> +
> +#ifndef X86_IFUNC_IMPL_ADD_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +#endif
> +#ifndef X86_IFUNC_IMPL_ADD_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +#endif
> +
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> +
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..7cae11c228
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,102 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +
> +/*
> + * CPU Features that are hard coded as enabled depending on ISA build
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +#define ISA_SHOULD_BUILD(isa_build_level) \
> + (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
> + || defined ISA_DEFAULT_IMPL
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..34634668e5
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupported ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
LGTM.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 23:51 ` [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-23 2:05 ` H.J. Lu
@ 2022-06-23 17:14 ` Joseph Myers
2022-06-23 17:32 ` Noah Goldstein
1 sibling, 1 reply; 36+ messages in thread
From: Joseph Myers @ 2022-06-23 17:14 UTC (permalink / raw)
To: Noah Goldstein; +Cc: libc-alpha
One of these recent changes breaks the x86_64 --disable-multi-arch build.
In file included from ../sysdeps/x86_64/memchr.S:24:
../sysdeps/x86_64/isa-default-impl.h:51:4: error: #error "RTLD version should only exist in multiarch build"
51 | # error "RTLD version should only exist in multiarch build"
| ^~~~~
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-23 17:14 ` Joseph Myers
@ 2022-06-23 17:32 ` Noah Goldstein
2022-06-23 18:14 ` Noah Goldstein
0 siblings, 1 reply; 36+ messages in thread
From: Noah Goldstein @ 2022-06-23 17:32 UTC (permalink / raw)
To: Joseph Myers; +Cc: GNU C Library
On Thu, Jun 23, 2022 at 10:14 AM Joseph Myers <joseph@codesourcery.com> wrote:
>
> One of these recent changes breaks the x86_64 --disable-multi-arch build.
>
> In file included from ../sysdeps/x86_64/memchr.S:24:
> ../sysdeps/x86_64/isa-default-impl.h:51:4: error: #error "RTLD version should only exist in multiarch build"
> 51 | # error "RTLD version should only exist in multiarch build"
> | ^~~~~
>
Christ, I was using `--disable-mulatiarch` when I tested :/
Have fix will post when finished testing.
> --
> Joseph S. Myers
> joseph@codesourcery.com
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-23 17:32 ` Noah Goldstein
@ 2022-06-23 18:14 ` Noah Goldstein
0 siblings, 0 replies; 36+ messages in thread
From: Noah Goldstein @ 2022-06-23 18:14 UTC (permalink / raw)
To: Joseph Myers; +Cc: GNU C Library
On Thu, Jun 23, 2022 at 10:32 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Thu, Jun 23, 2022 at 10:14 AM Joseph Myers <joseph@codesourcery.com> wrote:
> >
> > One of these recent changes breaks the x86_64 --disable-multi-arch build.
> >
> > In file included from ../sysdeps/x86_64/memchr.S:24:
> > ../sysdeps/x86_64/isa-default-impl.h:51:4: error: #error "RTLD version should only exist in multiarch build"
> > 51 | # error "RTLD version should only exist in multiarch build"
> > | ^~~~~
> >
>
> Christ, I was using `--disable-mulatiarch` when I tested :/
>
> Have fix will post when finished testing.
Pushed fix.
> > --
> > Joseph S. Myers
> > joseph@codesourcery.com
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-06-23 18:15 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-21 16:18 [PATCH v1] stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] Noah Goldstein
2022-06-22 7:09 ` Siddhesh Poyarekar
2022-06-22 15:24 ` Noah Goldstein
2022-06-22 15:24 ` [PATCH v2] " Noah Goldstein
2022-06-22 15:30 ` Siddhesh Poyarekar
2022-06-22 17:11 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 17:12 ` [PATCH v8 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 17:50 ` H.J. Lu
2022-06-22 18:10 ` Noah Goldstein
2022-06-22 17:14 ` [PATCH v8 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 18:11 ` [PATCH v9 " Noah Goldstein
2022-06-22 18:11 ` [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 18:38 ` H.J. Lu
2022-06-22 18:50 ` Noah Goldstein
2022-06-22 20:58 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 20:58 ` [PATCH v10 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 21:51 ` H.J. Lu
2022-06-22 22:04 ` Noah Goldstein
2022-06-22 22:14 ` H.J. Lu
2022-06-22 22:16 ` Noah Goldstein
2022-06-22 21:38 ` [PATCH v10 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 21:51 ` Noah Goldstein
2022-06-22 21:48 ` [PATCH v11 " Noah Goldstein
2022-06-22 21:48 ` [PATCH v11 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 21:54 ` [PATCH v11 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 22:16 ` [PATCH v12 " Noah Goldstein
2022-06-22 22:16 ` [PATCH v12 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 22:54 ` [PATCH v13 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 22:54 ` [PATCH v13 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 23:51 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 23:51 ` [PATCH v14 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-23 2:05 ` H.J. Lu
2022-06-23 17:14 ` Joseph Myers
2022-06-23 17:32 ` Noah Goldstein
2022-06-23 18:14 ` Noah Goldstein
2022-06-23 2:06 ` [PATCH v14 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
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