From: Noah Goldstein <goldstein.w.n@gmail.com>
To: libc-alpha@sourceware.org
Subject: [PATCH v1 1/7] x86: Align entry for memrchr to 64-bytes.
Date: Thu, 23 Jun 2022 23:36:48 -0700 [thread overview]
Message-ID: <20220624063653.2126416-1-goldstein.w.n@gmail.com> (raw)
The function was tuned around 64-byte entry alignment and performs
better for all sizes with it.
As well different code boths where explicitly written to touch the
minimum number of cache line i.e sizes <= 32 touch only the entry
cache line.
---
Tested with:
for march in "--disable-multi-arch" ""; do for ISA in "-march=x86-64-v4" "-march=x86-64-v3" "" "-march=x86-64-v2"; do echo "START: ${ISA} - $march"; rm -rf glibc-dev/build; mkdir -p glibc-dev/build/glibc/; (cd glibc-dev/build/glibc/; unset LD_LIBRARY_PATH; glibc-dev/src/glibc/configure --prefix=/usr CC="gcc ${ISA}" $march; make -j7 --silent; make -r -C glibc-dev/src/glibc/string/ objdir=`pwd` check; make -r -C glibc-dev/src/glibc/wcsmbs/ objdir=`pwd` check;); echo "DONE: ${ISA} - $march"; objdump -d build/glibc/string/memchr.o; objdump -d build/glibc/string/rawmemchr.o; objdump -d build/glibc/wcsmbs/wmemchr.o; cat build/glibc/string/test-memchr.out; cat build/glibc/string/test-memchr.test-result; cat build/glibc/string/test-rawmemchr.out; cat build/glibc/string/test-rawmemchr.test-result; cat build/glibc/wcsmbs/test-wmemchr.out; cat build/glibc/wcsmbs/test-wmemchr.test-result; done; done
for march in "" "--disable-multi-arch"; do rm -rf build; mkdir -p build/glibc; (cd glibc-dev/build/glibc/; unset LD_LIBRARY_PATH; glibc-dev/src/glibc/configure CC="gcc -m32" CXX="g++ -m32" --prefix=/usr --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu $march; make -j7 --silent;) done
(cd glibc-dev/build/glibc/; unset LD_LIBRARY_PATH; glibc-dev/src/glibc/configure --prefix=/usr; make -j7 --silent; make -j7 check --silent);
5155 PASS
19 UNSUPPORTED
18 XFAIL
4 XPASS
sysdeps/x86_64/multiarch/memrchr-avx2.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sysdeps/x86_64/multiarch/memrchr-avx2.S b/sysdeps/x86_64/multiarch/memrchr-avx2.S
index 9c83c76d3c..f300d7daf4 100644
--- a/sysdeps/x86_64/multiarch/memrchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memrchr-avx2.S
@@ -35,7 +35,7 @@
# define VEC_SIZE 32
# define PAGE_SIZE 4096
.section SECTION(.text), "ax", @progbits
-ENTRY(MEMRCHR)
+ENTRY_P2ALIGN(MEMRCHR, 6)
# ifdef __ILP32__
/* Clear upper bits. */
and %RDX_LP, %RDX_LP
--
2.34.1
next reply other threads:[~2022-06-24 6:37 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 6:36 Noah Goldstein [this message]
2022-06-24 6:36 ` [PATCH v1 2/7] x86: Rename strstr_sse2 to strstr_generic as it uses string/strstr.c Noah Goldstein
2022-06-24 6:36 ` [PATCH v1 3/7] x86: Add macro for NOT of a cpu arch feature and improve comments Noah Goldstein
2022-06-24 14:32 ` H.J. Lu
2022-06-24 14:49 ` H.J. Lu
2022-06-24 16:43 ` Noah Goldstein
2022-06-24 20:10 ` [PATCH v2] x86: Fix backwards Prefer_No_VZEROUPPER check in ifunc-evex.h Noah Goldstein
2022-06-24 20:32 ` H.J. Lu
2022-06-24 21:26 ` Noah Goldstein
2022-06-24 21:36 ` H.J. Lu
2022-06-24 21:46 ` [PATCH v3] " Noah Goldstein
2022-06-24 22:15 ` H.J. Lu
2022-06-24 22:29 ` Noah Goldstein
2022-06-24 22:29 ` [PATCH v4] " Noah Goldstein
2022-06-24 22:41 ` H.J. Lu
2022-06-24 22:57 ` Noah Goldstein
2022-06-24 23:05 ` H.J. Lu
2022-06-24 23:16 ` Noah Goldstein
2022-06-24 23:15 ` [PATCH v5] " Noah Goldstein
2022-06-24 23:20 ` H.J. Lu
2022-06-24 6:36 ` [PATCH v1 4/7] x86: Add comment with ISA level for all targets support by GCC12.1 Noah Goldstein
2022-06-24 6:36 ` [PATCH v1 5/7] x86: Use ARCH_P_NOT to check Prefer_No_VZeroupper in ifunc-evex.h Noah Goldstein
2022-06-24 6:36 ` [PATCH v1 6/7] x86: Put wcs{n}len-sse4.1 in the sse4.1 text section Noah Goldstein
2022-06-24 6:36 ` [PATCH v1 7/7] x86: Remove unused file wmemcmp-sse4 Noah Goldstein
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