From: Noah Goldstein <goldstein.w.n@gmail.com>
To: libc-alpha@sourceware.org
Subject: [PATCH v2] x86: Add comment with ISA level for all targets support by GCC12.1
Date: Fri, 24 Jun 2022 09:42:16 -0700 [thread overview]
Message-ID: <20220624164216.2129400-5-goldstein.w.n@gmail.com> (raw)
In-Reply-To: <20220624164216.2129400-1-goldstein.w.n@gmail.com>
This is just a quality of life change to make it easier to see how the
ISA level will effect a given build.
---
sysdeps/x86/isa-level.h | 67 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index e1a30ed83e..f14ae5cc00 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -64,8 +64,71 @@
#define MINIMUM_X86_ISA_LEVEL \
(__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
-
-/*
+/* ISA levels for known GCC targets as of GCC12.1:
+ *
+ * amdfam10 -> 1
+ * athlon-fx -> 1
+ * athlon64 -> 1
+ * athlon64-sse3 -> 1
+ * atom -> 1
+ * barcelona -> 1
+ * bonnell -> 1
+ * btver1 -> 1
+ * core2 -> 1
+ * eden-x2 -> 1
+ * eden-x4 -> 1
+ * k8 -> 1
+ * k8-sse3 -> 1
+ * nano -> 1
+ * nano-1000 -> 1
+ * nano-2000 -> 1
+ * nano-3000 -> 1
+ * nano-x2 -> 1
+ * nano-x4 -> 1
+ * nocona -> 1
+ * opteron -> 1
+ * opteron-sse3 -> 1
+ * x86-64 -> 1
+ * bdver1 -> 2
+ * bdver2 -> 2
+ * bdver3 -> 2
+ * btver2 -> 2
+ * core-avx-i -> 2
+ * corei7 -> 2
+ * corei7-avx -> 2
+ * goldmont -> 2
+ * goldmont-plus -> 2
+ * ivybridge -> 2
+ * nehalem -> 2
+ * sandybridge -> 2
+ * silvermont -> 2
+ * slm -> 2
+ * tremont -> 2
+ * westmere -> 2
+ * x86-64-v2 -> 2
+ * alderlake -> 3
+ * bdver4 -> 3
+ * broadwell -> 3
+ * core-avx2 -> 3
+ * haswell -> 3
+ * knl -> 3
+ * knm -> 3
+ * skylake -> 3
+ * x86-64-v3 -> 3
+ * znver1 -> 3
+ * znver2 -> 3
+ * znver3 -> 3
+ * cannonlake -> 4
+ * cascadelake -> 4
+ * cooperlake -> 4
+ * icelake-client -> 4
+ * icelake-server -> 4
+ * rocketlake -> 4
+ * sapphirerapids -> 4
+ * skylake-avx512 -> 4
+ * tigerlake -> 4
+ * x86-64-v4 -> 4
+ *
* CPU Features that are hard coded as enabled/disabled depending on
* ISA build level.
* - Values > 0 features are always ENABLED if:
--
2.34.1
next prev parent reply other threads:[~2022-06-24 16:42 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 16:42 [PATCH v2] x86: Align entry for memrchr to 64-bytes Noah Goldstein
2022-06-24 16:42 ` [PATCH v2] x86: Rename strstr_sse2 to strstr_generic as it uses string/strstr.c Noah Goldstein
2022-06-24 17:06 ` H.J. Lu
2022-06-24 16:42 ` [PATCH v2] x86: Remove unused file wmemcmp-sse4 Noah Goldstein
2022-06-24 17:03 ` H.J. Lu
2022-06-24 16:42 ` [PATCH v2] x86: Put wcs{n}len-sse4.1 in the sse4.1 text section Noah Goldstein
2022-06-24 17:05 ` H.J. Lu
2022-07-14 3:02 ` Sunil Pandey
2022-06-24 16:42 ` Noah Goldstein [this message]
2022-06-24 17:02 ` [PATCH v2] x86: Add comment with ISA level for all targets support by GCC12.1 H.J. Lu
2022-06-24 17:15 ` [PATCH v2] x86: Align entry for memrchr to 64-bytes H.J. Lu
2022-07-14 2:59 ` Sunil Pandey
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