From: Noah Goldstein <goldstein.w.n@gmail.com>
To: libc-alpha@sourceware.org
Subject: [PATCH v1] x86: Add support for building strstr with explicit ISA level
Date: Tue, 28 Jun 2022 08:26:27 -0700 [thread overview]
Message-ID: <20220628152628.17802-2-goldstein.w.n@gmail.com> (raw)
In-Reply-To: <20220628152628.17802-1-goldstein.w.n@gmail.com>
Small changes for this function as the generic implementation remains
the same for all ISA levels.
Only changes are using the X86_ISA_CPU_FEATURE{S}_{USABLE|ARCH}_P
macros so that some of the checks at least can constant evaluate
and some comments explaining the ISA constraints on the function.
---
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 13 +++++++------
sysdeps/x86_64/multiarch/strstr.c | 10 +++++-----
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 0d28319905..a1bff560bc 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -620,12 +620,13 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/strstr.c. */
IFUNC_IMPL (i, name, strstr,
- IFUNC_IMPL_ADD (array, i, strstr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (AVX512DQ)
- && CPU_FEATURE_USABLE (BMI2)),
- __strstr_avx512)
+ /* All implementations of strstr are built at all ISA levels. */
+ IFUNC_IMPL_ADD (array, i, strstr,
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (AVX512DQ)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __strstr_avx512)
IFUNC_IMPL_ADD (array, i, strstr, 1, __strstr_sse2_unaligned)
IFUNC_IMPL_ADD (array, i, strstr, 1, __strstr_generic))
diff --git a/sysdeps/x86_64/multiarch/strstr.c b/sysdeps/x86_64/multiarch/strstr.c
index 2b83199245..3f86bfa5f2 100644
--- a/sysdeps/x86_64/multiarch/strstr.c
+++ b/sysdeps/x86_64/multiarch/strstr.c
@@ -49,13 +49,13 @@ IFUNC_SELECTOR (void)
const struct cpu_features *cpu_features = __get_cpu_features ();
if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_AVX512)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512DQ)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2))
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512DQ)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2))
return __strstr_avx512;
- if (CPU_FEATURES_ARCH_P (cpu_features, Fast_Unaligned_Load))
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, Fast_Unaligned_Load, ))
return __strstr_sse2_unaligned;
return __strstr_generic;
--
2.34.1
next prev parent reply other threads:[~2022-06-28 15:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-28 15:26 [PATCH v1] x86-64: Small improvements to dl-trampoline.S Noah Goldstein
2022-06-28 15:26 ` Noah Goldstein [this message]
2022-06-28 18:20 ` [PATCH v1] x86: Add support for building strstr with explicit ISA level H.J. Lu
2022-06-28 18:24 ` Noah Goldstein
2022-06-28 18:34 ` H.J. Lu
2022-06-28 18:38 ` Noah Goldstein
2022-06-28 15:26 ` [PATCH v1] x86: Add support for building {w}memcmp{eq} " Noah Goldstein
2022-06-29 18:52 ` H.J. Lu
2022-06-29 19:27 ` Noah Goldstein
2022-06-29 19:41 ` H.J. Lu
2022-06-29 19:44 ` Noah Goldstein
2022-06-29 19:48 ` H.J. Lu
2022-06-29 22:09 ` Noah Goldstein
2022-06-29 22:09 ` [PATCH v2] " Noah Goldstein
2022-06-29 22:49 ` H.J. Lu
2022-06-29 23:11 ` Noah Goldstein
2022-06-29 23:11 ` [PATCH v3] " Noah Goldstein
2022-07-01 22:56 ` H.J. Lu
2022-06-28 18:15 ` [PATCH v1] x86-64: Small improvements to dl-trampoline.S H.J. Lu
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