From: "dengjianbo@loongson.cn" <dengjianbo@loongson.cn>
To: "Xi Ruoyao" <xry111@xry111.site>,
adhemerval.zanella <adhemerval.zanella@linaro.org>,
libc-alpha <libc-alpha@sourceware.org>,
i.swmail <i.swmail@xen0n.name>
Cc: xuchenghua <xuchenghua@loongson.cn>,
joseph_myers <joseph_myers@mentor.com>,
caiyinyu <caiyinyu@loongson.cn>,
huangpei <huangpei@loongson.cn>
Subject: Re: Re: [PATCH 1/1] LoongArch: Add optimized functions.
Date: Fri, 16 Sep 2022 15:34:02 +0800 [thread overview]
Message-ID: <2022091615340204060516@loongson.cn> (raw)
In-Reply-To: <9051986d0096cb1d0de15b4925e5a744eaf2b81b.camel@xry111.site>
[-- Attachment #1: Type: text/plain, Size: 2110 bytes --]
Hi Ruoyao,
Thanks for your suggestions regarding this patch, we have modified the code and create a new patch, you can find it via https://sourceware.org/pipermail/libc-alpha/2022-September/142016.html. The reason to using .align 6 is to make the loop starts with a cache line. Now we have optimzed the code and reduced some instructions, so it's not necessary to use 64-byte alignment any longer and it's removed accordingly.
Best regards,
Deng Jianbo
From: Xi Ruoyao
Date: 2022-09-02 17:35
To: dengjianbo; adhemerval.zanella; libc-alpha; i.swmail
CC: xuchenghua; joseph_myers; caiyinyu
Subject: Re: [PATCH 1/1] LoongArch: Add optimized functions.
I've not really run the code, see below for some comments after a quick
view.
On Fri, 2022-09-02 at 16:39 +0800, dengjianbo wrote:
/* snip */
What is "ANDROID_CHANGES"? I can't find anything in Glibc building
system defining it and AFAIK Android is using another libc
implementation (I can't remember the name, but I'm sure it's not Glibc).
> +#ifdef ANDROID_CHANGES
> +LEAF(MEMMOVE_NAME, 0)
> +#else
> +LEAF(MEMMOVE_NAME)
/* snip */
> +start_unalign_proc:
> + pcaddi t1, 18
> + slli.d a6, a7, 3
> + add.d t1, t1, a6
> + jirl zero, t1, 0
"jr t1", to make the expression of all "jump register" operations
consistent. Likewise for all "jirl zero, [something], 0".
> +end:
> + move v0, t8
> + jr ra
Do not use MIPS-style v0 or v1 aliases. They mislead people to believe
"v0" was a different register than "a0".
/* snip */
> +#define L_ADDIU addi.d
> +#define L_ADDU add.d
> +#define L_SUBU sub.d
Do not use MIPS-style "U" suffix. LoongArch is not so MIPS-similar (we
don't have some "signaling arithmetic") and you don't want others to
believe so, do you? :)
> +LEAF(STRCHR)
> + .align 6
Hmm, any rational to force a 64-byte alignment here?
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
prev parent reply other threads:[~2022-09-16 7:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-02 8:39 [PATCH 0/1] " dengjianbo
2022-09-02 8:39 ` [PATCH 1/1] " dengjianbo
2022-09-02 9:35 ` Xi Ruoyao
2022-09-02 9:52 ` Xi Ruoyao
2022-09-16 7:34 ` dengjianbo [this message]
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