From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id 32CE23858C00 for ; Sun, 6 Nov 2022 19:32:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 32CE23858C00 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=google.com Received: by mail-pf1-x42b.google.com with SMTP id i3so8791027pfc.11 for ; Sun, 06 Nov 2022 11:32:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=02fh668zv1wDF1uRMmoWaGmIbjsGXMCAhHny1CzbuKo=; b=KrdE+r7rGngv+zgXjmD8G3IRKDIOD1iGCN6PMDjEd5A2PjdD3y9EhCVhK5L3iJp0pw 7x53yBbAXscvnz9AzaalO2i5FtrMpgX+RDyH0Ys4o+tehUTjuL3LeRGTNJ26RJoq86Ts 2qHOxbD7bLqQth4UXlmnVurbE5XbtPUR+x+n3hs2IeuBusRLowVu6z9UGd9sh796G9vD UYy6xlZp9ibkCc+3DUH3m//wh50T4Jbc/bUau4Zc4g5Bau3CbOKb/pfQos8b7UrZLl3J GNHfJVpEowYMKsUc77yNKNhVdoP/tGS81HUxFsyqgOcqHxRZVmFiBCKd6GPX0Zw0pwWi eM7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=02fh668zv1wDF1uRMmoWaGmIbjsGXMCAhHny1CzbuKo=; b=T2OtHVX1CJPa27AQvx6vXtwihOQAMD6O0SI70JCRu3yZFyYTdmCzGt5p3MuxQWuzCL cxi6RsiuHySI+1Wa3Jb2c5es8mbgb1QBIZxI+6ONqFuv29WUhv9hgLasC6HHxyKS64or zlCjaAYKWbRqPpx2VK6Atsckkwrd8DNsBziURkrTO2NiCcjk7aC8VaakK5hgGdUxpl8f 8DL3zn/8nI9w6fsbRjbzHrWlA/fxcDP0kOGs52mlgB4nuB0mQ1mlazszmTjNXhXQD3Vo bTVUQ8cf3/1vA5K77/9YwMMb1TfMyG9TnH8Z3s2kl2aGTMpaaclZoA//itDskLk8BO9A 4Ldw== X-Gm-Message-State: ACrzQf11LUbmBTra2mVUX9KBMl+/mPScJo7EHTi5GZ/yWRFAG5Mkuih+ eDKZCdXc48lNIv7oomps1eOA8g== X-Google-Smtp-Source: AMsMyM4AXj1IJV2GoNZDzyppg2cOhUDx7/AlaeOigri+lD+4YXQE8Yt+8nQkVB5LFp5GyWtdTr7c1g== X-Received: by 2002:a63:e211:0:b0:43b:f03e:3cc5 with SMTP id q17-20020a63e211000000b0043bf03e3cc5mr40138632pgh.256.1667763134770; Sun, 06 Nov 2022 11:32:14 -0800 (PST) Received: from google.com ([2620:15c:2ce:200:8836:d128:f95d:95f3]) by smtp.gmail.com with ESMTPSA id u14-20020a170902e5ce00b0017f778d4543sm3474857plf.241.2022.11.06.11.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 11:32:13 -0800 (PST) Date: Sun, 6 Nov 2022 11:32:10 -0800 From: Fangrui Song To: Andrew Pinski , Jakub Jelinek Cc: Adhemerval Zanella , libc-alpha@sourceware.org, Joseph Myers Subject: Re: [PATCH 01/11] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints Message-ID: <20221106193210.i6qvkstumiikkvn2@google.com> References: <20221028173532.876027-1-adhemerval.zanella@linaro.org> <20221028173532.876027-2-adhemerval.zanella@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-27.4 required=5.0 tests=BAYES_00,DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,USER_IN_DEF_DKIM_WL,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: [Fixing email address.. Really sorry for my mistake.] On 2022-11-01, Andrew Pinski via Libc-alpha wrote: > On Fri, Oct 28, 2022 at 10:36 AM Adhemerval Zanella via Libc-alpha > wrote: >> >> From: Fangrui Song >> >> An output constraint takes a lvalue. While GCC happily strips the >> incorrect lvalue to rvalue conversion, Clang rejects the code by >> default: > >For GCC this is https://gcc.gnu.org/bugzilla/show_bug.cgi?id=2803 . >I wrote about the ones in longlong.h (inside GCC sources) in comment >#11 back in 2004 when I tried to fix GCC's front-end to reject this. > >Thanks, >Andrew Thanks for the comment. Would GCC side consider https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html ? If GCC takes the patch to its diverged GMP 2.0 copy (released 1996), glibc can import the change. > > >> >> error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions >> --- >> stdlib/longlong.h | 186 +++++++++++++++++++++++----------------------- >> 1 file changed, 93 insertions(+), 93 deletions(-) >> >> diff --git a/stdlib/longlong.h b/stdlib/longlong.h >> index d8f76a43b5..303cc4e8d0 100644 >> --- a/stdlib/longlong.h >> +++ b/stdlib/longlong.h >> @@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); >> #if defined (__arc__) && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%r" ((USItype) (ah)), \ >> "rICal" ((USItype) (bh)), \ >> "%r" ((USItype) (al)), \ >> @@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); >> : "cc") >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "r" ((USItype) (ah)), \ >> "rICal" ((USItype) (bh)), \ >> "r" ((USItype) (al)), \ >> @@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); >> && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%r" ((USItype) (ah)), \ >> "rI" ((USItype) (bh)), \ >> "%r" ((USItype) (al)), \ >> "rI" ((USItype) (bl)) __CLOBBER_CC) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "r" ((USItype) (ah)), \ >> "rI" ((USItype) (bh)), \ >> "r" ((USItype) (al)), \ >> @@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); >> " addcs %0, %0, #65536\n" \ >> " adds %1, %1, %3, lsl #16\n" \ >> " adc %0, %0, %3, lsr #16" \ >> - : "=&r" ((USItype) (xh)), \ >> - "=r" ((USItype) (xl)), \ >> + : "=&r" (xh), \ >> + "=r" (xl), \ >> "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ >> : "r" ((USItype) (a)), \ >> "r" ((USItype) (b)) __CLOBBER_CC ); \ >> @@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__hppa) && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%rM" ((USItype) (ah)), \ >> "rM" ((USItype) (bh)), \ >> "%rM" ((USItype) (al)), \ >> "rM" ((USItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "rM" ((USItype) (ah)), \ >> "rM" ((USItype) (bh)), \ >> "rM" ((USItype) (al)), \ >> @@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%0" ((USItype) (ah)), \ >> "g" ((USItype) (bh)), \ >> "%1" ((USItype) (al)), \ >> "g" ((USItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "0" ((USItype) (ah)), \ >> "g" ((USItype) (bh)), \ >> "1" ((USItype) (al)), \ >> "g" ((USItype) (bl))) >> #define umul_ppmm(w1, w0, u, v) \ >> __asm__ ("mul{l} %3" \ >> - : "=a" ((USItype) (w0)), \ >> - "=d" ((USItype) (w1)) \ >> + : "=a" (w0), \ >> + "=d" (w1) \ >> : "%0" ((USItype) (u)), \ >> "rm" ((USItype) (v))) >> #define udiv_qrnnd(q, r, n1, n0, dv) \ >> __asm__ ("div{l} %4" \ >> - : "=a" ((USItype) (q)), \ >> - "=d" ((USItype) (r)) \ >> + : "=a" (q), \ >> + "=d" (r) \ >> : "0" ((USItype) (n0)), \ >> "1" ((USItype) (n1)), \ >> "rm" ((USItype) (dv))) >> @@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__x86_64__) && W_TYPE_SIZE == 64 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \ >> - : "=r" ((UDItype) (sh)), \ >> - "=&r" ((UDItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%0" ((UDItype) (ah)), \ >> "rme" ((UDItype) (bh)), \ >> "%1" ((UDItype) (al)), \ >> "rme" ((UDItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \ >> - : "=r" ((UDItype) (sh)), \ >> - "=&r" ((UDItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "0" ((UDItype) (ah)), \ >> "rme" ((UDItype) (bh)), \ >> "1" ((UDItype) (al)), \ >> "rme" ((UDItype) (bl))) >> #define umul_ppmm(w1, w0, u, v) \ >> __asm__ ("mul{q} %3" \ >> - : "=a" ((UDItype) (w0)), \ >> - "=d" ((UDItype) (w1)) \ >> + : "=a" (w0), \ >> + "=d" (w1) \ >> : "%0" ((UDItype) (u)), \ >> "rm" ((UDItype) (v))) >> #define udiv_qrnnd(q, r, n1, n0, dv) \ >> __asm__ ("div{q} %4" \ >> - : "=a" ((UDItype) (q)), \ >> - "=d" ((UDItype) (r)) \ >> + : "=a" (q), \ >> + "=d" (r) \ >> : "0" ((UDItype) (n0)), \ >> "1" ((UDItype) (n1)), \ >> "rm" ((UDItype) (dv))) >> @@ -609,8 +609,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> /* The cmp clears the condition bit. */ \ >> __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "0" ((USItype) (ah)), \ >> "r" ((USItype) (bh)), \ >> "1" ((USItype) (al)), \ >> @@ -619,8 +619,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> /* The cmp clears the condition bit. */ \ >> __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "0" ((USItype) (ah)), \ >> "r" ((USItype) (bh)), \ >> "1" ((USItype) (al)), \ >> @@ -631,16 +631,16 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__mc68000__) && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ >> - : "=d" ((USItype) (sh)), \ >> - "=&d" ((USItype) (sl)) \ >> + : "=d" (sh), \ >> + "=&d" (sl) \ >> : "%0" ((USItype) (ah)), \ >> "d" ((USItype) (bh)), \ >> "%1" ((USItype) (al)), \ >> "g" ((USItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ >> - : "=d" ((USItype) (sh)), \ >> - "=&d" ((USItype) (sl)) \ >> + : "=d" (sh), \ >> + "=&d" (sl) \ >> : "0" ((USItype) (ah)), \ >> "d" ((USItype) (bh)), \ >> "1" ((USItype) (al)), \ >> @@ -650,23 +650,23 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if (defined (__mc68020__) && !defined (__mc68060__)) >> #define umul_ppmm(w1, w0, u, v) \ >> __asm__ ("mulu%.l %3,%1:%0" \ >> - : "=d" ((USItype) (w0)), \ >> - "=d" ((USItype) (w1)) \ >> + : "=d" (w0), \ >> + "=d" (w1) \ >> : "%0" ((USItype) (u)), \ >> "dmi" ((USItype) (v))) >> #define UMUL_TIME 45 >> #define udiv_qrnnd(q, r, n1, n0, d) \ >> __asm__ ("divu%.l %4,%1:%0" \ >> - : "=d" ((USItype) (q)), \ >> - "=d" ((USItype) (r)) \ >> + : "=d" (q), \ >> + "=d" (r) \ >> : "0" ((USItype) (n0)), \ >> "1" ((USItype) (n1)), \ >> "dmi" ((USItype) (d))) >> #define UDIV_TIME 90 >> #define sdiv_qrnnd(q, r, n1, n0, d) \ >> __asm__ ("divs%.l %4,%1:%0" \ >> - : "=d" ((USItype) (q)), \ >> - "=d" ((USItype) (r)) \ >> + : "=d" (q), \ >> + "=d" (r) \ >> : "0" ((USItype) (n0)), \ >> "1" ((USItype) (n1)), \ >> "dmi" ((USItype) (d))) >> @@ -700,8 +700,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> " move%.l %/d2,%1\n" \ >> " add%.l %/d1,%/d0\n" \ >> " move%.l %/d0,%0" \ >> - : "=g" ((USItype) (xh)), \ >> - "=g" ((USItype) (xl)) \ >> + : "=g" (xh), \ >> + "=g" (xl) \ >> : "g" ((USItype) (a)), \ >> "g" ((USItype) (b)) \ >> : "d0", "d1", "d2", "d3", "d4") >> @@ -736,8 +736,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> " move%.l %/d2,%1\n" \ >> " add%.l %/d1,%/d0\n" \ >> " move%.l %/d0,%0" \ >> - : "=g" ((USItype) (xh)), \ >> - "=g" ((USItype) (xl)) \ >> + : "=g" (xh)), \ >> + "=g" (xl) \ >> : "g" ((USItype) (a)), \ >> "g" ((USItype) (b)) \ >> : "d0", "d1", "d2", "d3", "d4") >> @@ -751,7 +751,7 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__mc68020__) && !defined (__mcpu32__) >> #define count_leading_zeros(count, x) \ >> __asm__ ("bfffo %1{%b2:%b2},%0" \ >> - : "=d" ((USItype) (count)) \ >> + : "=d" (count) \ >> : "od" ((USItype) (x)), "n" (0)) >> /* Some ColdFire architectures have a ff1 instruction supported via >> __builtin_clz. */ >> @@ -764,16 +764,16 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__m88000__) && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%rJ" ((USItype) (ah)), \ >> "rJ" ((USItype) (bh)), \ >> "%rJ" ((USItype) (al)), \ >> "rJ" ((USItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "rJ" ((USItype) (ah)), \ >> "rJ" ((USItype) (bh)), \ >> "rJ" ((USItype) (al)), \ >> @@ -1000,16 +1000,16 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("a %1,%5\n\tae %0,%3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%0" ((USItype) (ah)), \ >> "r" ((USItype) (bh)), \ >> "%1" ((USItype) (al)), \ >> "r" ((USItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("s %1,%5\n\tse %0,%3" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "0" ((USItype) (ah)), \ >> "r" ((USItype) (bh)), \ >> "1" ((USItype) (al)), \ >> @@ -1038,8 +1038,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> " m r2,%3\n" \ >> " cas %0,r2,r0\n" \ >> " mfs r10,%1" \ >> - : "=r" ((USItype) (ph)), \ >> - "=r" ((USItype) (pl)) \ >> + : "=r" (ph), \ >> + "=r" (pl) \ >> : "%r" (__m0), \ >> "r" (__m1) \ >> : "r2"); \ >> @@ -1052,12 +1052,12 @@ extern UDItype __umulsidi3 (USItype, USItype); >> do { \ >> if ((x) >= 0x10000) \ >> __asm__ ("clz %0,%1" \ >> - : "=r" ((USItype) (count)) \ >> + : "=r" (count) \ >> : "r" ((USItype) (x) >> 16)); \ >> else \ >> { \ >> __asm__ ("clz %0,%1" \ >> - : "=r" ((USItype) (count)) \ >> + : "=r" (count) \ >> : "r" ((USItype) (x))); \ >> (count) += 16; \ >> } \ >> @@ -1119,8 +1119,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #define umul_ppmm(w1, w0, u, v) \ >> __asm__ ( \ >> "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \ >> - : "=r<" ((USItype)(w1)), \ >> - "=r<" ((USItype)(w0)) \ >> + : "=r<" (w1), \ >> + "=r<" (w0) \ >> : "r" ((USItype)(u)), \ >> "r" ((USItype)(v)) \ >> : "macl", "mach") >> @@ -1191,8 +1191,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "%rJ" ((USItype) (ah)), \ >> "rI" ((USItype) (bh)), \ >> "%rJ" ((USItype) (al)), \ >> @@ -1200,8 +1200,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> __CLOBBER_CC) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ >> - : "=r" ((USItype) (sh)), \ >> - "=&r" ((USItype) (sl)) \ >> + : "=r" (sh), \ >> + "=&r" (sl) \ >> : "rJ" ((USItype) (ah)), \ >> "rI" ((USItype) (bh)), \ >> "rJ" ((USItype) (al)), \ >> @@ -1213,7 +1213,7 @@ extern UDItype __umulsidi3 (USItype, USItype); >> register USItype __g1 asm ("g1"); \ >> __asm__ ("umul\t%2,%3,%1\n\t" \ >> "srlx\t%1, 32, %0" \ >> - : "=r" ((USItype) (w1)), \ >> + : "=r" (w1), \ >> "=r" (__g1) \ >> : "r" ((USItype) (u)), \ >> "r" ((USItype) (v))); \ >> @@ -1224,8 +1224,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> "udiv\t%3,%4,%0\n\t" \ >> "umul\t%0,%4,%1\n\t" \ >> "sub\t%3,%1,%1" \ >> - : "=&r" ((USItype) (__q)), \ >> - "=&r" ((USItype) (__r)) \ >> + : "=&r" (__q), \ >> + "=&r" (__r) \ >> : "r" ((USItype) (__n1)), \ >> "r" ((USItype) (__n0)), \ >> "r" ((USItype) (__d))) >> @@ -1233,14 +1233,14 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__sparc_v8__) >> #define umul_ppmm(w1, w0, u, v) \ >> __asm__ ("umul %2,%3,%1;rd %%y,%0" \ >> - : "=r" ((USItype) (w1)), \ >> - "=r" ((USItype) (w0)) \ >> + : "=r" (w1), \ >> + "=r" (w0) \ >> : "r" ((USItype) (u)), \ >> "r" ((USItype) (v))) >> #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ >> __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ >> - : "=&r" ((USItype) (__q)), \ >> - "=&r" ((USItype) (__r)) \ >> + : "=&r" (__q), \ >> + "=&r" (__r) \ >> : "r" ((USItype) (__n1)), \ >> "r" ((USItype) (__n0)), \ >> "r" ((USItype) (__d))) >> @@ -1250,8 +1250,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> instructions scan (ffs from high bit) and divscc. */ >> #define umul_ppmm(w1, w0, u, v) \ >> __asm__ ("umul %2,%3,%1;rd %%y,%0" \ >> - : "=r" ((USItype) (w1)), \ >> - "=r" ((USItype) (w0)) \ >> + : "=r" (w1), \ >> + "=r" (w0) \ >> : "r" ((USItype) (u)), \ >> "r" ((USItype) (v))) >> #define udiv_qrnnd(q, r, n1, n0, d) \ >> @@ -1294,8 +1294,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> " bl,a 1f\n" \ >> " add %1,%4,%1\n" \ >> "1: ! End of inline udiv_qrnnd" \ >> - : "=r" ((USItype) (q)), \ >> - "=r" ((USItype) (r)) \ >> + : "=r" (q), \ >> + "=r" (r) \ >> : "r" ((USItype) (n1)), \ >> "r" ((USItype) (n0)), \ >> "rI" ((USItype) (d)) \ >> @@ -1304,7 +1304,7 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #define count_leading_zeros(count, x) \ >> do { \ >> __asm__ ("scan %1,1,%0" \ >> - : "=r" ((USItype) (count)) \ >> + : "=r" (count) \ >> : "r" ((USItype) (x))); \ >> } while (0) >> /* Early sparclites return 63 for an argument of 0, but they warn that future >> @@ -1354,8 +1354,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> " mulscc %%g1,0,%%g1\n" \ >> " add %%g1,%%o5,%0\n" \ >> " rd %%y,%1" \ >> - : "=r" ((USItype) (w1)), \ >> - "=r" ((USItype) (w0)) \ >> + : "=r" (w1), \ >> + "=r" (w0) \ >> : "%rI" ((USItype) (u)), \ >> "r" ((USItype) (v)) \ >> : "g1", "o5" __AND_CLOBBER_CC) >> @@ -1387,8 +1387,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> " sub %1,%2,%1\n" \ >> "3: xnor %0,0,%0\n" \ >> " ! End of inline udiv_qrnnd" \ >> - : "=&r" ((USItype) (__q)), \ >> - "=&r" ((USItype) (__r)) \ >> + : "=&r" (__q), \ >> + "=&r" (__r) \ >> : "r" ((USItype) (__d)), \ >> "1" ((USItype) (__n1)), \ >> "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC) >> @@ -1407,8 +1407,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> "add\t%r3,%4,%0\n\t" \ >> "movcs\t%%xcc, 1, %2\n\t" \ >> "add\t%0, %2, %0" \ >> - : "=r" ((UDItype)(sh)), \ >> - "=&r" ((UDItype)(sl)), \ >> + : "=r" (sh), \ >> + "=&r" (sl), \ >> "+r" (__carry) \ >> : "%rJ" ((UDItype)(ah)), \ >> "rI" ((UDItype)(bh)), \ >> @@ -1424,8 +1424,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> "sub\t%r3,%4,%0\n\t" \ >> "movcs\t%%xcc, 1, %2\n\t" \ >> "sub\t%0, %2, %0" \ >> - : "=r" ((UDItype)(sh)), \ >> - "=&r" ((UDItype)(sl)), \ >> + : "=r" (sh), \ >> + "=&r" (sl), \ >> "+r" (__carry) \ >> : "%rJ" ((UDItype)(ah)), \ >> "rI" ((UDItype)(bh)), \ >> @@ -1459,8 +1459,8 @@ extern UDItype __umulsidi3 (USItype, USItype); >> "sllx %3,32,%3\n\t" \ >> "add %1,%3,%1\n\t" \ >> "add %5,%2,%0" \ >> - : "=r" ((UDItype)(wh)), \ >> - "=&r" ((UDItype)(wl)), \ >> + : "=r" (wh), \ >> + "=&r" (wl), \ >> "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ >> : "r" ((UDItype)(u)), \ >> "r" ((UDItype)(v)) \ >> @@ -1473,16 +1473,16 @@ extern UDItype __umulsidi3 (USItype, USItype); >> #if defined (__vax__) && W_TYPE_SIZE == 32 >> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ >> __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ >> - : "=g" ((USItype) (sh)), \ >> - "=&g" ((USItype) (sl)) \ >> + : "=g" (sh)), \ >> + "=&g" (sl) \ >> : "%0" ((USItype) (ah)), \ >> "g" ((USItype) (bh)), \ >> "%1" ((USItype) (al)), \ >> "g" ((USItype) (bl))) >> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ >> __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ >> - : "=g" ((USItype) (sh)), \ >> - "=&g" ((USItype) (sl)) \ >> + : "=g" (sh)), \ >> + "=&g" (sl) \ >> : "0" ((USItype) (ah)), \ >> "g" ((USItype) (bh)), \ >> "1" ((USItype) (al)), \ >> -- >> 2.34.1 >>