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[1.169.217.217]) by smtp.gmail.com with ESMTPSA id fa23-20020a056a002d1700b006259e883ee9sm650992pfb.189.2023.04.21.00.54.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Apr 2023 00:54:20 -0700 (PDT) From: Hau Hsu To: libc-alpha@sourceware.org, hongrong.hsu@sifive.com, jerry.shih@sifive.com, nick.knight@sifive.com, kito.cheng@sifive.com Cc: greentime.hu@sifive.com, alice.chan@sifive.com, andrew@sifive.com, vincent.chen@sifive.com, hau.hsu@sifive.com Subject: [PATCH v2 0/5] riscv: Vectorized mem*/str* function Date: Fri, 21 Apr 2023 15:54:00 +0800 Message-Id: <20230421075405.14892-1-hau.hsu@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I am submitting version 2 of the patch for adding vectorized mem*/str* functions for RISC-V. This patch builds upon the previous version (v1) available at https://patchwork.sourceware.org/project/glibc/list/?series=17710. In this version, we have included the __memcmpeq function and set lmul=1 for memcmp, which improves its generality. Jerry Shih (2): riscv: vectorized mem* functions riscv: vectorized str* functions Nick Knight (1): riscv: vectorized strchr and strnlen functions Vincent Chen (1): riscv: Enabling vectorized mem*/str* functions in build time Yun Hsiang (1): riscv: add vectorized __memcmpeq scripts/build-many-glibcs.py | 10 ++++ sysdeps/riscv/preconfigure | 19 +++++++ sysdeps/riscv/preconfigure.ac | 18 +++++++ sysdeps/riscv/rv32/rvv/Implies | 2 + sysdeps/riscv/rv64/rvv/Implies | 2 + sysdeps/riscv/rvv/memchr.S | 63 +++++++++++++++++++++++ sysdeps/riscv/rvv/memcmp.S | 71 ++++++++++++++++++++++++++ sysdeps/riscv/rvv/memcmpeq.S | 69 +++++++++++++++++++++++++ sysdeps/riscv/rvv/memcpy.S | 51 +++++++++++++++++++ sysdeps/riscv/rvv/memmove.S | 72 ++++++++++++++++++++++++++ sysdeps/riscv/rvv/memset.S | 51 +++++++++++++++++++ sysdeps/riscv/rvv/strcat.S | 72 ++++++++++++++++++++++++++ sysdeps/riscv/rvv/strchr.S | 53 +++++++++++++++++++ sysdeps/riscv/rvv/strcmp.S | 93 ++++++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strcpy.S | 56 ++++++++++++++++++++ sysdeps/riscv/rvv/strlen.S | 54 ++++++++++++++++++++ sysdeps/riscv/rvv/strncat.S | 83 ++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strncmp.S | 85 +++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strncpy.S | 86 +++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strnlen.S | 56 ++++++++++++++++++++ 20 files changed, 1066 insertions(+) create mode 100644 sysdeps/riscv/rv32/rvv/Implies create mode 100644 sysdeps/riscv/rv64/rvv/Implies create mode 100644 sysdeps/riscv/rvv/memchr.S create mode 100644 sysdeps/riscv/rvv/memcmp.S create mode 100644 sysdeps/riscv/rvv/memcmpeq.S create mode 100644 sysdeps/riscv/rvv/memcpy.S create mode 100644 sysdeps/riscv/rvv/memmove.S create mode 100644 sysdeps/riscv/rvv/memset.S create mode 100644 sysdeps/riscv/rvv/strcat.S create mode 100644 sysdeps/riscv/rvv/strchr.S create mode 100644 sysdeps/riscv/rvv/strcmp.S create mode 100644 sysdeps/riscv/rvv/strcpy.S create mode 100644 sysdeps/riscv/rvv/strlen.S create mode 100644 sysdeps/riscv/rvv/strncat.S create mode 100644 sysdeps/riscv/rvv/strncmp.S create mode 100644 sysdeps/riscv/rvv/strncpy.S create mode 100644 sysdeps/riscv/rvv/strnlen.S -- 2.37.1